def run(f, netlist):
f = NewlineReplacer(f)
# initialize the net-name aliasing
# Convert to all upper case because Pads seems to do that
# internally anyway and we'd rather do it here to catch shorts
# created by not preserving case. Plus we can eliminate lots of
# ECO changes that will show up during backannotation.
net_aliases = util_alias.build_net_aliases(
lambda net: net.name.upper(), netlist.nets)
# initialize the refdes aliasing
# Convert to all upper case because Pads seems to do that
# internally anyway and we'd rather do it here to catch name
# clashes created by not preserving case.
refdes_aliases = util_alias.build_refdes_aliases(
lambda package: package.refdes.upper(), netlist.packages)
# print out the header
f.write('!PADS-POWERPCB-V3.0-MILS!\n')
f.write('\n')
f.write('*PART*\n')
# print out the parts
for package in reversed(netlist.packages):
pattern = package.get_attribute('pattern', None)
# The above pattern should stay as 'pattern' and not 'footprint'
if pattern is not None:
f.write(pattern)
# print out the refdes with aliasing
f.write('%s\t%s\n' % (refdes_aliases[package],
package.get_attribute('footprint', 'unknown')))
# print out the net information
f.write('\n')
f.write('*NET*\n')
for net in reversed(netlist.nets):
f.write('*SIGNAL* %s\n' % net_aliases[net])
f.write(wrap(
' ' + ' '.join(
'%s.%s' % (refdes_aliases[pin.package], pin.number)
for pin in reversed(net.connections)),
78, '', ' '))
# print out the footer
f.write('\n')
f.write('*END*\n')
def run(f, netlist):
f = NewlineReplacer(f)
# initialize the net-name aliasing
# Convert to all upper case because Pads seems to do that
# internally anyway and we'd rather do it here to catch shorts
# created by not preserving case. Plus we can eliminate lots of
# ECO changes that will show up during backannotation.
net_aliases = util_alias.build_net_aliases(lambda net: net.name.upper(),
netlist.nets)
# initialize the refdes aliasing
# Convert to all upper case because Pads seems to do that
# internally anyway and we'd rather do it here to catch name
# clashes created by not preserving case.
refdes_aliases = util_alias.build_refdes_aliases(
lambda package: package.refdes.upper(), netlist.packages)
# print out the header
f.write('!PADS-POWERPCB-V3.0-MILS!\n')
f.write('\n')
f.write('*PART*\n')
# print out the parts
for package in reversed(netlist.packages):
pattern = package.get_attribute('pattern', None)
# The above pattern should stay as 'pattern' and not 'footprint'
if pattern is not None:
f.write(pattern)
# print out the refdes with aliasing
f.write('%s\t%s\n' % (refdes_aliases[package],
package.get_attribute('footprint', 'unknown')))
# print out the net information
f.write('\n')
f.write('*NET*\n')
for net in reversed(netlist.nets):
f.write('*SIGNAL* %s\n' % net_aliases[net])
f.write(
wrap(
' ' +
' '.join('%s.%s' % (refdes_aliases[pin.package], pin.number)
for pin in reversed(net.connections)), 78, '', ' '))
# print out the footer
f.write('\n')
f.write('*END*\n')
def run(f, netlist):
sys.stderr.write("""\
---------------------------------
gEDA/gnetlist FutureNet2 Backend
This backend is EXPERIMENTAL
Use at your own risk!
You may need to run the output netlist
through unix2dos before importing to
Ranger2 or other windows based layout tools
---------------------------------
""")
# initialize the net-name aliasing
net_aliases = util_alias.build_net_aliases(map_net_names, netlist.nets)
# initialize the refdes aliasing
refdes_aliases = util_alias.build_refdes_aliases(map_refdes, netlist.packages)
# write the header
f.write('PINLIST,2\n')
f.write('(DRAWING,GEDA.PIN,1-1\n')
# write the components
symcnt = 1
for package in reversed(netlist.packages):
f.write('(SYM,%s\n' % symcnt)
# write the reference designator
f.write('DATA,2,%s\n' % refdes_aliases[package])
# If there is a "value" attribute, output that.
# Otherwise output the "device" attribute (the symbol name).
val = package.get_attribute('value', None)
if val is None:
val = package.get_attribute('device', 'unknown')
f.write('DATA,3,%s\n' % val)
# write the footprint
f.write('DATA,4,%s\n' % package.get_attribute('footprint', 'unknown'))
# write the pins for this component
for pin in reversed(package.pins):
# PIN,,NetName,1-1,5,20/23,pinnum
f.write('PIN,,')
if pin.net.is_unconnected_pin:
f.write('#f')
else:
f.write(net_aliases[pin.net])
# XXX I've seen 20, 23, and 100 in the position where the
# "23" is here. Seems to be a property like signal vs
# power net. Not sure how to support that.
f.write(',1-1,5,23,')
f.write(pin.get_attribute('pinnumber', 'unknown'))
f.write('\n')
# close the part
f.write(')\n')
symcnt += 1
f.write(')\n')
# write the nets
for net in reversed(netlist.nets):
f.write('SIG,%s,1-1,5,%s\n' % (net_aliases[net], net_aliases[net]))
# terminating ")"
f.write(')\n')
def run(f, netlist):
sys.stderr.write("""\
---------------------------------
gEDA/gnetlist FutureNet2 Backend
This backend is EXPERIMENTAL
Use at your own risk!
You may need to run the output netlist
through unix2dos before importing to
Ranger2 or other windows based layout tools
---------------------------------
""")
# initialize the net-name aliasing
net_aliases = util_alias.build_net_aliases(map_net_names, netlist.nets)
# initialize the refdes aliasing
refdes_aliases = util_alias.build_refdes_aliases(map_refdes,
netlist.packages)
# write the header
f.write('PINLIST,2\n')
f.write('(DRAWING,GEDA.PIN,1-1\n')
# write the components
symcnt = 1
for package in reversed(netlist.packages):
f.write('(SYM,%s\n' % symcnt)
# write the reference designator
f.write('DATA,2,%s\n' % refdes_aliases[package])
# If there is a "value" attribute, output that.
# Otherwise output the "device" attribute (the symbol name).
val = package.get_attribute('value', None)
if val is None:
val = package.get_attribute('device', 'unknown')
f.write('DATA,3,%s\n' % val)
# write the footprint
f.write('DATA,4,%s\n' % package.get_attribute('footprint', 'unknown'))
# write the pins for this component
for pin in reversed(package.pins):
# PIN,,NetName,1-1,5,20/23,pinnum
f.write('PIN,,')
if pin.net.is_unconnected_pin:
f.write('#f')
else:
f.write(net_aliases[pin.net])
# XXX I've seen 20, 23, and 100 in the position where the
# "23" is here. Seems to be a property like signal vs
# power net. Not sure how to support that.
f.write(',1-1,5,23,')
f.write(pin.get_attribute('pinnumber', 'unknown'))
f.write('\n')
# close the part
f.write(')\n')
symcnt += 1
f.write(')\n')
# write the nets
for net in reversed(netlist.nets):
f.write('SIG,%s,1-1,5,%s\n' % (net_aliases[net], net_aliases[net]))
# terminating ")"
f.write(')\n')
def run(f, netlist):
# initialize the net-name and refdes aliasing
net_aliases = util_alias.build_net_aliases(map_net_names, netlist.nets)
refdes_aliases = util_alias.build_refdes_aliases(map_refdes,
netlist.packages)
# Write top Switcap netlist header
f.write('/* Switcap netlist produced by gnetlist (part of gEDA) */\n')
f.write('/* See http://www.geda-project.org/ for more information. */\n')
f.write('/* Switcap backend written by Dan McMahill */\n')
f.write('\n')
f.write('\n')
# Write the main TITLE and OPTIONS block
for package in reversed(netlist.packages):
device = package.get_attribute('device', None)
if device == 'SWITCAP-options':
# write options
# OPTIONS; OPT1; OPT2; ...; END;
# valid options are: WIDTH132 NOLIST REPORT NOOVRLAY GRID
f.write('OPTIONS; %s END;\n' % get_attrib(package, 'OPTIONS'))
f.write('\n')
elif device == 'SWITCAP-title':
# write title
# TITLE: my title;
# Can only have 64 characters in the title
# TODO: need to truncate to 64 chars
f.write('TITLE:%s;\n' % get_attrib(package, 'TITLE'))
f.write('\n')
f.write('TIMING;\n')
# Write the main TIMING block
for package in reversed(netlist.packages):
device = package.get_attribute('device', None)
if device == 'SWITCAP-clock':
# write clock definition
# CLOCK clock_name period (phi_start phi_stop)
f.write(
' CLOCK %s %s (%s %s);\n' %
(package.refdes, get_attrib(package, 'PERIOD'),
get_attrib(package, 'PSTART'), get_attrib(package, 'PSTOP')))
elif device == 'SWITCAP-timing':
# write master clock period
# PERIOD clock_period;
f.write(' PERIOD %s;\n' % get_attrib(package, 'PERIOD'))
f.write('END;\n')
f.write('\n')
f.write('CIRCUIT;\n')
# Write the main CIRCUIT block netlist
for package in reversed(netlist.packages):
device = package.get_attribute('device', None)
if device == 'SWITCAP-capacitor':
# write capacitor: refdes, nodes and value
# C### (N1 N2) value;
f.write(' %s (%s %s) %s;\n' %
(refdes_aliases[package],
net_aliases[package.pins_by_number['1'].net],
net_aliases[package.pins_by_number['2'].net],
get_attrib(package, 'value')))
elif device == 'SWITCAP-switch':
# write switch: refdes, nodes and clock
# S### (N1 N2) clk;
f.write(' %s (%s %s) %s;\n' %
(refdes_aliases[package],
net_aliases[package.pins_by_number['1'].net],
net_aliases[package.pins_by_number['2'].net],
get_attrib(package, 'clock')))
elif device == 'SWITCAP-vcvs':
# write voltage controlled voltage source: refdes, nodes and clock
# E### (OUTP OUTM INP INM) gain;
f.write(' %s (%s %s %s %s) %s;\n' %
(refdes_aliases[package],
net_aliases[package.pins_by_number['1'].net],
net_aliases[package.pins_by_number['2'].net],
net_aliases[package.pins_by_number['3'].net],
net_aliases[package.pins_by_number['4'].net],
get_attrib(package, 'gain')))
elif device == 'SWITCAP-vsrc':
# write voltage source: refdes and nodes
# V### (OUTP OUTM);
f.write(' %s (%s %s);\n' %
(refdes_aliases[package],
net_aliases[package.pins_by_number['1'].net],
net_aliases[package.pins_by_number['2'].net]))
f.write('END;\n')
f.write('\n')
# Write the main ANALYSIS block
for package in reversed(netlist.packages):
device = package.get_attribute('device', None)
if device == 'SWITCAP-analysis':
write_analysis(get_attrib(package, 'file'))
f.write('\n')
f.write('\n')
f.write('/* End of SWITCAP netlist */\n')
f.write('END;\n')
def run(f, netlist):
# initialize the net-name and refdes aliasing
net_aliases = util_alias.build_net_aliases(map_net_names, netlist.nets)
refdes_aliases = util_alias.build_refdes_aliases(map_refdes, netlist.packages)
# Write top Switcap netlist header
f.write('/* Switcap netlist produced by gnetlist (part of gEDA) */\n')
f.write('/* See http://www.geda-project.org/ for more information. */\n')
f.write('/* Switcap backend written by Dan McMahill */\n')
f.write('\n')
f.write('\n')
# Write the main TITLE and OPTIONS block
for package in reversed(netlist.packages):
device = package.get_attribute('device', None)
if device == 'SWITCAP-options':
# write options
# OPTIONS; OPT1; OPT2; ...; END;
# valid options are: WIDTH132 NOLIST REPORT NOOVRLAY GRID
f.write('OPTIONS; %s END;\n' % get_attrib(package, 'OPTIONS'))
f.write('\n')
elif device == 'SWITCAP-title':
# write title
# TITLE: my title;
# Can only have 64 characters in the title
# TODO: need to truncate to 64 chars
f.write('TITLE:%s;\n' % get_attrib(package, 'TITLE'))
f.write('\n')
f.write('TIMING;\n')
# Write the main TIMING block
for package in reversed(netlist.packages):
device = package.get_attribute('device', None)
if device == 'SWITCAP-clock':
# write clock definition
# CLOCK clock_name period (phi_start phi_stop)
f.write(' CLOCK %s %s (%s %s);\n' % (
package.refdes,
get_attrib(package, 'PERIOD'),
get_attrib(package, 'PSTART'),
get_attrib(package, 'PSTOP')))
elif device == 'SWITCAP-timing':
# write master clock period
# PERIOD clock_period;
f.write(' PERIOD %s;\n' % get_attrib(package, 'PERIOD'))
f.write('END;\n')
f.write('\n')
f.write('CIRCUIT;\n')
# Write the main CIRCUIT block netlist
for package in reversed(netlist.packages):
device = package.get_attribute('device', None)
if device == 'SWITCAP-capacitor':
# write capacitor: refdes, nodes and value
# C### (N1 N2) value;
f.write(' %s (%s %s) %s;\n' % (
refdes_aliases[package],
net_aliases[package.pins_by_number['1'].net],
net_aliases[package.pins_by_number['2'].net],
get_attrib(package, 'value')))
elif device == 'SWITCAP-switch':
# write switch: refdes, nodes and clock
# S### (N1 N2) clk;
f.write(' %s (%s %s) %s;\n' % (
refdes_aliases[package],
net_aliases[package.pins_by_number['1'].net],
net_aliases[package.pins_by_number['2'].net],
get_attrib(package, 'clock')))
elif device == 'SWITCAP-vcvs':
# write voltage controlled voltage source: refdes, nodes and clock
# E### (OUTP OUTM INP INM) gain;
f.write(' %s (%s %s %s %s) %s;\n' % (
refdes_aliases[package],
net_aliases[package.pins_by_number['1'].net],
net_aliases[package.pins_by_number['2'].net],
net_aliases[package.pins_by_number['3'].net],
net_aliases[package.pins_by_number['4'].net],
get_attrib(package, 'gain')))
elif device == 'SWITCAP-vsrc':
# write voltage source: refdes and nodes
# V### (OUTP OUTM);
f.write(' %s (%s %s);\n' % (
refdes_aliases[package],
net_aliases[package.pins_by_number['1'].net],
net_aliases[package.pins_by_number['2'].net]))
f.write('END;\n')
f.write('\n')
# Write the main ANALYSIS block
for package in reversed(netlist.packages):
device = package.get_attribute('device', None)
if device == 'SWITCAP-analysis':
write_analysis(get_attrib(package, 'file'))
f.write('\n')
f.write('\n')
f.write('/* End of SWITCAP netlist */\n')
f.write('END;\n')
