def dec16b(cpu, opcode, logger):
regInd = (opcode >> 4) & 3
cpu.Reg16(regInd, cpu.Reg16(regInd) - 1)
cpu.m_cycles, cpu.t_states = 1, 6
logger.info("DEC {}".format(IndexToReg.translate16Bit(regInd)))
def inc16(cpu, opcode, logger):
regInd = (opcode & 0x30) >> 4
cpu.Reg16(regInd, cpu.Reg16(regInd) + 1)
cpu.m_cycles, cpu.t_states = 1, 6
logger.info("INC {0}".format(IndexToReg.translate16Bit(regInd)))
def push(cpu, opcode, logger):
regInd = (opcode >> 4) & 3
value = cpu.Reg16(regInd, af=True)
cpu.ram[cpu.SP-1] = value >> 8
cpu.ram[cpu.SP-2] = value & 255
cpu.SP -= 2
cpu.m_cycles, cpu.t_states = 3, 11
logger.info("PUSH {}".format(IndexToReg.translate16Bit(regInd)))
def add_iy_rr(cpu, opcode, logger):
regInd = (opcode >> 4) & 3
val = cpu.Reg16(regInd, iy=True)
old = cpu.IY
cpu.IY = cpu.IY + val
cpu.NFlag = Bits.reset()
cpu.HFlag = Bits.carryFlagAdd16(old, cpu.IY)
cpu.CFlag = Bits.overflow(old, cpu.IY, bits=16)
cpu.m_cycles, cpu.t_states = 4, 15
logger.info("ADD IY, {}".format(IndexToReg.translate16Bit(regInd)))
def pop(cpu, opcode, logger):
regInd = (opcode >> 4) & 3
high = cpu.ram[cpu.SP+1]
low = cpu.ram[cpu.SP]
cpu.SP += 2
val = (high << 8) + low
cpu.Reg16(regInd, val, af=True)
cpu.m_cycles, cpu.t_states = 3, 7
logger.info("POP {}".format(IndexToReg.translate16Bit(regInd)))
def add16(cpu, opcode, logger):
regInd = (opcode & 0x30) >> 4
value = cpu.Reg16(regInd)
oldHL = cpu.HL
cpu.HL = cpu.HL + value
cpu.NFlag = Bits.reset()
cpu.CFlag = Bits.carryFlag16(oldHL, cpu.HL)
cpu.HFlag = Bits.carryFlag16(oldHL, cpu.HL, bits=11)
cpu.m_cycles, cpu.t_states = 3, 11
logger.info("ADD HL, {}".format(IndexToReg.translate16Bit(regInd)))
def ldNnRr(cpu, opcode, logger):
regInd = (opcode & 0x30) >> 4
high = cpu.ram[cpu.PC]
low = cpu.ram[cpu.PC]
addr = (high << 8) + low
value = cpu.Reg16(regInd)
cpu.ram[addr + 1] = value >> 8
cpu.ram[addr] = value & 0xFF
cpu.m_cycles, cpu.t_states = 6, 20
logger.info("LD ({:04X}), {}".format(addr, IndexToReg.translate16Bit(regInd)))
def ld16(cpu, opcode, logger):
regInd = (opcode & 0x30) >> 4
loValue = cpu.ram[cpu.PC]
hiValue = cpu.ram[cpu.PC]
value = (hiValue << 8) + loValue
cpu.Reg16(regInd, value)
cpu.m_cycles, cpu.t_states = 2, 10
logger.info("LD {}, {:04X}".format(
IndexToReg.translate16Bit(regInd),
value))
def ld16_nn(cpu, opcode, logger):
low = cpu.ram[cpu.PC]
high = cpu.ram[cpu.PC]
addr = (high << 8) + low
value_low = cpu.ram[addr]
value_high = cpu.ram[addr+1]
value = (value_high << 8) + value_low
regInd = (opcode >> 4) & 3
cpu.Reg16(regInd, value)
cpu.m_cycles, cpu.t_states = 6, 20
logger.info("LD {},({:0X})".format(IndexToReg.translate16Bit(regInd), addr))
def add_Hl_rr_c(cpu, opcode, logger):
regInd = (opcode >> 4) & 3
val = cpu.Reg16(regInd)
old = cpu.HL
cpu.HL = cpu.HL + val + (1 if cpu.CFlag else 0)
cpu.SFlag = Bits.signFlag(cpu.HL, bits=16)
cpu.ZFlag = Bits.isZero(cpu.HL)
cpu.HFlag = Bits.halfCarrySub16(old, cpu.HL)
cpu.PVFlag = Bits.overflow(old, cpu.HL, bits=16)
cpu.NFlag = Bits.reset()
cpu.CFlag = Bits.set() if (Bits.getNthBit(old, 15) == 1 and
Bits.getNthBit(cpu.HL, 15) == 0) else Bits.reset()
cpu.m_cycles, cpu.t_states = 4, 15
logger.info("ADC HL, {}".format(IndexToReg.translate16Bit(regInd)))
def sbc(cpu, opcode, logger):
regInd = (opcode & 0x30) >> 4
value = cpu.Reg16(regInd)
oldHL = cpu.HL
cpu.HL = cpu.HL - value - (1 if cpu.CFlag else 0)
cpu.SFlag = Bits.signFlag(cpu.HL, bits=16)
cpu.ZFlag = Bits.isZero(cpu.HL)
cpu.HFlag = Bits.halfCarrySub16(oldHL, cpu.HL)
cpu.PVFlag = Bits.overflow(oldHL, cpu.HL, bits=16)
cpu.NFlag = Bits.set()
cpu.CFlag = Bits.borrow(cpu.HL, bits=16)
cpu.m_cycles, cpu.t_states = 4, 15
logger.info("SBC HL, {}".format(IndexToReg.translate16Bit(regInd)))
def test_IndexToReg_translate16Bit_returns_IY_for_2_and_iy_True(self):
self.assertEquals("IY", IndexToReg.translate16Bit(2, iy=True))
def test_IndexToReg_translate16Bit_returns_HL_for_2(self):
self.assertEqual("HL", IndexToReg.translate16Bit(2))
def test_IndexToReg_translate16Bit_returns_SP_for_3(self):
self.assertEqual("SP", IndexToReg.translate16Bit(3))
def test_IndexToReg_translate16Bit_returns_IX_for_2_and_ix_True(self):
self.assertEqual("IX", IndexToReg.translate16Bit(2, ix=True))
def test_IndexToReg_translate16Bit_returns_BC_for_0(self):
self.assertEquals("BC", IndexToReg.translate16Bit(0))
def test_IndexToReg_translate16Bit_returns_DE_for_1(self):
self.assertEquals("DE", IndexToReg.translate16Bit(1))
def test_IndexToReg_translate16Bit_returns_HL_for_2(self):
self.assertEquals("HL", IndexToReg.translate16Bit(2))
def test_IndexToReg_translate16Bit_returns_DE_for_1(self):
self.assertEqual("DE", IndexToReg.translate16Bit(1))
def test_IndexToReg_translate16Bit_returns_SP_for_3(self):
self.assertEquals("SP", IndexToReg.translate16Bit(3))
def test_IndexToReg_translate16Bit_returns_IX_for_2_and_ix_True(self):
self.assertEquals("IX", IndexToReg.translate16Bit(2, ix=True))
def test_IndextoReg_translate16Bit_returns_AF_for_3_and_af_True(self):
self.assertEquals("AF", IndexToReg.translate16Bit(3, af=True))
def test_IndexToReg_translate16Bit_returns_BC_for_0(self):
self.assertEqual("BC", IndexToReg.translate16Bit(0))
