def combine_generic(name, arg): """Generate VHDL generic declaration.""" if len(arg) > 1: return (" %s : %s := %s" % (name, combine_type(arg[0]), str(arg[1]))) else: return (" %s : %s" % (name, combine_type(arg[0])))
def combine_port(name, arg): """Generate VHDL port declaration.""" return (" %s : %s %s" % (name, arg[0], combine_type(arg[1])))