def prologue(self):
simctrl = verilog.scope('example.simctrl_0_u')
# up timeout
simctrl.direct.sim_ctrl_timeout_i = 200
instances = dict([(i, verilog.scope('example.duv_0_u.arr[%d].arr' % i))
for i in range(4, 20)])
self.callbacks = [
arr_cb(simctrl.sim_ctrl_clk_op.set_type(verilog.vpiInt), instance,
None) for instance in instances.values()
]
def prologue(self) :
# initialize random seed with deterministic value
seed = test.plusargs().get('seed', 1)
random.seed(seed)
simctrl = verilog.scope('example.simctrl_0_u')
arr = dict([(i, verilog.scope('example.duv_0_u.arr[%d].arr' % i)) for i in range(1,self.MAX_INSTS)])
# up timeout beyond test time
simctrl.direct.sim_ctrl_timeout_i = self.TIMEOUT
# reduce time step
simctrl.direct.sim_ctrl_cycles_freq_i = 1
for scope in arr.values() :
scope.direct.verbose = 0 # display values
# register call back
cbClk0 = self.cb_fcty(simctrl.sim_ctrl_clk_op.set_type(verilog.vpiInt), simctrl, arr)
def prologue(self):
# initialize random seed with deterministic value
seed = test.plusargs().get('seed', 1)
random.seed(seed)
simctrl = verilog.scope('example.simctrl_0_u')
arr = dict([(i, verilog.scope('example.duv_0_u.arr[%d].arr' % i))
for i in range(1, self.MAX_INSTS)])
# up timeout beyond test time
simctrl.direct.sim_ctrl_timeout_i = self.TIMEOUT
# reduce time step
simctrl.direct.sim_ctrl_cycles_freq_i = 1
for scope in arr.values():
scope.direct.verbose = 0 # display values
# register call back
cbClk0 = self.cb_fcty(simctrl.sim_ctrl_clk_op.set_type(verilog.vpiInt),
simctrl, arr)
# Copyright (c) 2012, 2013 Rich Porter - see LICENSE for further details
import message
import test
import verilog
################################################################################
duv = verilog.scope('example.duv_0_u')
class thistest(test.test):
activity = 'simulation'
block = 'default'
name = 'test capacity'
def prologue(self):
message.note('Creating 1000 signal instances')
instances = [duv.single_bit for i in range(0, 1000)]
for idx, inst in enumerate(instances):
message.information('%(idx)d is %(val)d', idx=idx, val=int(inst))
def epilogue(self):
self.success()
def fatal(self):
'Should not be executed'
message.fatal('Should not be executed')
################################################################################
def prologue(self) :
# register simulation controller scope
self.simctrl = verilog.scope('example.simctrl_0_u')
# register reset callback to reset signal in simulation controller scope
self.rstCallback = rstCallback(self.simctrl.sim_ctrl_rst_op, self.assign)
# Copyright (c) 2012, 2013 Rich Porter - see LICENSE for further details
import message
import test
import verilog
################################################################################
duv = verilog.scope('example.duv_0_u')
# build reset callback on top of verilog abstraction
class rstCallback(verilog.callback) :
def __init__(self, obj, func) :
verilog.callback.__init__(self, name='reset callback', obj=obj, reason=verilog.callback.cbValueChange, func=func)
class thistest(test.test) :
activity='simulation'
block='default'
name='test mdb fmt'
def prologue(self) :
# register simulation controller scope
self.simctrl = verilog.scope('example.simctrl_0_u')
# register reset callback to reset signal in simulation controller scope
self.rstCallback = rstCallback(self.simctrl.sim_ctrl_rst_op, self.assign)
def assign(self) :
duv.direct.test_message = 1
self.rstCallback.remove()
def epilogue(self) :
self.success()
def fatal(self) :
'Should not be executed'
def prologue(self) :
simctrl = verilog.scope('example.simctrl_0_u')
# up timeout
simctrl.direct.sim_ctrl_timeout_i = 200
instances = dict([(i, verilog.scope('example.duv_0_u.arr[%d].arr' % i)) for i in range(4,20)])
self.callbacks = [arr_cb(simctrl.sim_ctrl_clk_op.set_type(verilog.vpiInt), instance, None) for instance in instances.values()]
# Copyright (c) 2012, 2013 Rich Porter - see LICENSE for further details
import atexit
import message
import test
import verilog
def root() :
return 'example'
simctrl = verilog.scope(root() + '.simctrl_0_u')
if test.plusargs().timeout :
simctrl.direct.sim_ctrl_timeout_i = verilog.vpiInt(test.plusargs().timeout)
# use verilog vpi cbEndOfSimulation callback
class cbEndOfSimulation(verilog.callback) :
def __init__(self) :
verilog.callback.__init__(self, name='PLI end of simulation callback', reason=verilog.callback.cbEndOfSimulation, func=self.execute)
def execute(self) :
message.note('vpi cbEndOfSimulation')
end = cbEndOfSimulation()
# show when python interpreter is closed down
def finalize() :
message.note('finalize')
atexit.register(finalize)
