def mkMain():
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
myaxi = axi.AxiMaster(m, 'myaxi', clk, rst)
myram = RAM(m, 'myram', clk, rst, numports=1)
df = dataflow.DataflowManager(m, clk, rst)
fsm = FSM(m, 'fsm', clk, rst)
# AXI read request
araddr = 1024
arlen = 64
ack, counter = myaxi.read_request_counter(araddr, arlen, cond=fsm)
fsm.If(ack).goto_next()
# AXI read dataflow (AXI -> Dataflow)
axi_data, axi_last, done = myaxi.read_dataflow()
sum = df.ReduceAdd(axi_data, reset=axi_last.prev(1))
# RAM write dataflow (Dataflow -> RAM)
wport = 0
waddr = 0
wlen = arlen
done = myram.write_dataflow(wport, waddr, sum, wlen, cond=fsm)
fsm.goto_next()
fsm.If(done).goto_next()
# AXI write request
awaddr = 1024
awlen = 64
ack, counter = myaxi.write_request_counter(awaddr, awlen, cond=fsm)
fsm.If(ack).goto_next()
# RAM read dataflow (RAM -> Dataflow)
rport = 0
raddr = 0
rlen = arlen
rdata, rlast, done = myram.read_dataflow(rport, raddr, rlen, cond=fsm)
fsm.goto_next()
# AXI write dataflow
done = myaxi.write_dataflow(rdata, counter)
fsm.If(done).goto_next()
# verify
sum = m.Reg('sum', 32, initval=0)
expected_sum = 0
for i in range(arlen):
expected_sum += (araddr + araddr + i) * (i + 1) // 2
seq = Seq(m, 'seq', clk, rst)
seq.If(Ands(myaxi.wdata.wvalid,
myaxi.wdata.wready))(sum.add(myaxi.wdata.wdata))
seq.Then().If(myaxi.wdata.wlast).Delay(1)(Systask(
'display', "sum=%d expected_sum=%d", sum, expected_sum))
return m
def mkMain():
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
myaxi = axi.AxiMaster(m, 'myaxi', clk, rst)
myaxi.disable_write()
myram = RAM(m, 'myram', clk, rst, numports=1)
df = dataflow.DataflowManager(m, clk, rst)
fsm = FSM(m, 'fsm', clk, rst)
# AXI read request
araddr = 1024
arlen = 64
ack, axi_counter = myaxi.read_request(araddr, arlen, cond=fsm)
fsm.If(ack).goto_next()
# AXI read dataflow (AXI -> Dataflow)
axi_data, axi_last, done = myaxi.read_dataflow()
sum = df.ReduceAdd(axi_data, reset=axi_last.prev(1))
# RAM write dataflow (Dataflow -> RAM)
wport = 0
waddr = 0
wlen = arlen
done = myram.write_dataflow(wport, waddr, sum, wlen, cond=fsm)
fsm.goto_next()
fsm.If(done).goto_next()
# verify
# read dataflow (RAM -> Dataflow)
rport = 0
raddr = 0
rlen = arlen
rdata, rlast, done = myram.read_dataflow(rport, raddr, rlen, cond=fsm)
fsm.goto_next()
fsm.If(done).goto_next()
rdata_data, rdata_valid = rdata.read()
rlast_data, rlast_valid = rlast.read()
sum = m.Reg('sum', 32, initval=0)
expected_sum = 0
for i in range(arlen):
expected_sum += (araddr + araddr + i) * (i + 1) // 2
seq = Seq(m, 'seq', clk, rst)
seq.If(rdata_valid)(
sum.add(rdata_data)
)
seq.Then().If(rlast_data == 1).Delay(1)(
Systask('display', 'sum=%d expected_sum=%d', sum, expected_sum)
)
return m
def mkMain():
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
myaxi = axi.AxiMaster(m, 'myaxi', clk, rst)
myaxi.disable_write()
myram = RAM(m, 'myram', clk, rst, numports=1)
df = dataflow.DataflowManager(m, clk, rst)
fsm = FSM(m, 'fsm', clk, rst)
# AXI read request
araddr = 1024
arlen = 64
ack, axi_counter = myaxi.read_request_counter(araddr, arlen, cond=fsm)
fsm.If(ack).goto_next()
# AXI read dataflow (AXI -> Dataflow)
axi_data, axi_last, done = myaxi.read_dataflow()
sum = df.ReduceAdd(axi_data, reset=axi_last.prev(1))
# RAM write dataflow (Dataflow -> RAM)
wport = 0
waddr = 0
wlen = arlen
done = myram.write_dataflow(wport, waddr, sum, wlen, cond=fsm)
fsm.goto_next()
fsm.If(done).goto_next()
# verify
# read dataflow (RAM -> Dataflow)
rport = 0
raddr = 0
rlen = arlen
rdata, rlast, done = myram.read_dataflow(rport, raddr, rlen, cond=fsm)
fsm.goto_next()
fsm.If(done).goto_next()
rdata_data, rdata_valid = rdata.read()
rlast_data, rlast_valid = rlast.read()
sum = m.Reg('sum', 32, initval=0)
expected_sum = 0
for i in range(arlen):
expected_sum += (araddr + araddr + i) * (i + 1) // 2
seq = Seq(m, 'seq', clk, rst)
seq.If(rdata_valid)(sum.add(rdata_data))
seq.Then().If(rlast_data == 1).Delay(1)(
Systask('display', 'sum=%d expected_sum=%d', sum, expected_sum),
If(NotEql(sum, expected_sum))(Display('# verify: FAILED')).Else(
Display('# verify: PASSED')))
return m
def mkMain(n=128, datawidth=32, numports=2):
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
addrwidth = int(math.log(n, 2)) * 2
myram = RAM(m, 'myram', clk, rst, datawidth, addrwidth, 2)
myram.disable_write(1)
df = dataflow.DataflowManager(m, clk, rst)
fsm = FSM(m, 'fsm', clk, rst)
# dataflow
value = df.Counter()
# write dataflow (Dataflow -> RAM)
wport = 0
waddr = 0
wlen = 64
done = myram.write_dataflow(wport, waddr, value, wlen, cond=fsm)
fsm.goto_next()
fsm.If(done).goto_next()
fsm.goto_next()
# read dataflow (RAM -> Dataflow)
rport = 1
raddr = 0
rlen = 32
rdata, rlast, done = myram.read_dataflow(rport, raddr, rlen, cond=fsm)
fsm.goto_next()
fsm.If(done).goto_next()
# verify
rdata_data, rdata_valid = rdata.read()
rlast_data, rlast_valid = rlast.read()
sum = m.Reg('sum', 32, initval=0)
expected_sum = (raddr + raddr + rlen - 1) * rlen // 2
seq = Seq(m, 'seq', clk, rst)
seq.If(rdata_valid)(
sum.add(rdata_data)
)
seq.Then().If(rlast_data == 1).Delay(1)(
Systask('display', 'sum=%d expected_sum=%d', sum, expected_sum)
)
return m
def mkMain(n=128, datawidth=32, numports=2):
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
addrwidth = int(math.log(n, 2)) * 2
myram = RAM(m, 'myram', clk, rst, datawidth, addrwidth, 2)
myram.disable_write(1)
df = dataflow.DataflowManager(m, clk, rst)
fsm = FSM(m, 'fsm', clk, rst)
# dataflow
value = df.Counter()
# write dataflow (Dataflow -> RAM)
wport = 0
waddr = 0
wlen = 64
done = myram.write_dataflow(wport, waddr, value, wlen, cond=fsm)
fsm.goto_next()
fsm.If(done).goto_next()
fsm.goto_next()
# read dataflow (RAM -> Dataflow)
rport = 1
raddr = 0
rlen = 32
rdata, rlast, done = myram.read_dataflow(rport, raddr, rlen, cond=fsm)
fsm.goto_next()
fsm.If(done).goto_next()
# verify
rdata_data, rdata_valid = rdata.read()
rlast_data, rlast_valid = rlast.read()
sum = m.Reg('sum', 32, initval=0)
expected_sum = (raddr + raddr + rlen - 1) * rlen // 2
seq = Seq(m, 'seq', clk, rst)
seq.If(rdata_valid)(sum.add(rdata_data))
seq.Then().If(rlast_data == 1).Delay(1)(
Systask('display', 'sum=%d expected_sum=%d', sum, expected_sum),
If(NotEql(sum, expected_sum))(Display('# verify: FAILED')).Else(
Display('# verify: PASSED')))
return m