def mkMain():
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
myaxi = axi.AxiLiteMaster(m, 'myaxi', clk, rst)
myaxi.disable_read()
fsm = FSM(m, 'fsm', clk, rst)
# write address (1)
awaddr = 1024
ack = myaxi.write_request(awaddr, cond=fsm)
fsm.If(ack).goto_next()
# write data (1)
wdata = m.Reg('wdata', 32, initval=1024)
ack = myaxi.write_data(wdata, cond=fsm)
fsm.If(ack)(
wdata.inc()
)
fsm.Then().goto_next()
# write address (2)
awaddr = 1024 + 1024
ack = myaxi.write_request(awaddr, cond=fsm)
fsm.If(ack).goto_next()
# write data (2)
ack = myaxi.write_data(wdata, cond=fsm)
fsm.If(ack)(
wdata.inc()
)
fsm.Then().goto_next()
fsm.goto_next()
fsm.goto_next()
sum = m.Reg('sum', 32, initval=0)
expected_sum = 1024 + 1025
seq = Seq(m, 'seq', clk, rst)
seq.If(Ands(myaxi.wdata.wvalid, myaxi.wdata.wready))(
sum.add(myaxi.wdata.wdata)
)
seq.Then().Delay(1)(
Systask('display', "sum=%d expected_sum=%d", sum, expected_sum),
If(fsm.here)(If(NotEql(sum, expected_sum))(
Display('# verify: FAILED')).Else(Display('# verify: PASSED')))
)
return m
def mkMain():
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
myaxi = axi.AxiLiteMaster(m, 'myaxi', clk, rst)
myaxi.disable_write()
fsm = FSM(m, 'fsm', clk, rst)
sum = m.Reg('sum', 32, initval=0)
# read address (1)
araddr = 1024
expected_sum = (araddr // 4)
ack = myaxi.read_request(araddr, cond=fsm)
fsm.If(ack).goto_next()
# read data (1)
data, valid = myaxi.read_data(cond=fsm)
fsm.If(valid)(
sum(sum + data)
)
fsm.Then().goto_next()
# read address (2)
araddr = 1024 + 1024
expected_sum += (araddr // 4)
ack = myaxi.read_request(araddr, cond=fsm)
fsm.If(ack).goto_next()
# read data (2)
data, valid = myaxi.read_data(cond=fsm)
fsm.If(valid)(
sum(sum + data)
)
fsm.Then().goto_next()
fsm(
Systask('display', 'sum=%d expected_sum=%d', sum, expected_sum)
)
fsm.goto_next()
fsm.make_always()
return m
def mkTest():
m = Module('test')
# target instance
main = mkMain()
# copy paras and ports
params = m.copy_params(main)
ports = m.copy_sim_ports(main)
clk = ports['CLK']
rst = ports['RST']
_axi = axi.AxiLiteMaster(m, '_axi', clk, rst, noio=True)
_axi.disable_write()
_axi.connect(ports, 'myaxi')
fsm = FSM(m, 'fsm', clk, rst)
sum = m.Reg('sum', 32, initval=0)
# read address (1)
araddr = 1024
expected_sum = araddr // 4
ack = _axi.read_request(araddr, cond=fsm)
fsm.If(ack).goto_next()
# read data (1)
data, valid = _axi.read_data(cond=fsm)
fsm.If(valid)(sum(sum + data))
fsm.Then().goto_next()
# read address (2)
araddr = 1024 + 1024
expected_sum += araddr // 4
ack = _axi.read_request(araddr, cond=fsm)
fsm.If(ack).goto_next()
# read data (2)
data, valid = _axi.read_data(cond=fsm)
fsm.If(valid)(sum(sum + data))
fsm.Then().goto_next()
fsm(Systask('display', 'sum=%d expected_sum=%d', sum, expected_sum))
fsm.goto_next()
uut = m.Instance(main,
'uut',
params=m.connect_params(main),
ports=m.connect_ports(main))
simulation.setup_waveform(m, uut, m.get_vars())
simulation.setup_clock(m, clk, hperiod=5)
init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
init.add(
Delay(1000 * 100),
Systask('finish'),
)
return m
def mkTest():
m = Module('test')
# target instance
main = mkMain()
# copy paras and ports
params = m.copy_params(main)
ports = m.copy_sim_ports(main)
clk = ports['CLK']
rst = ports['RST']
sum = ports['sum']
_axi = axi.AxiLiteMaster(m, '_axi', clk, rst, noio=True)
_axi.disable_read()
_axi.connect(ports, 'myaxi')
fsm = FSM(m, 'fsm', clk, rst)
for i in range(100):
fsm.goto_next()
# write address (1)
awaddr = 1024
wval = 100
expected_sum = wval
ack = _axi.write_request(awaddr, cond=fsm)
wdata = m.Reg('wdata', 32, initval=0)
fsm.If(ack)(
wdata(wval)
)
fsm.If(ack).goto_next()
# write data (1)
ack = _axi.write_data(wdata, cond=fsm)
fsm.If(ack).goto_next()
# write address (2)
wval = 200
expected_sum += wval
ack = _axi.write_request(awaddr, cond=fsm)
fsm.If(ack)(
wdata(wval)
)
fsm.If(ack).goto_next()
# write data (2)
ack = _axi.write_data(wdata, cond=fsm)
fsm.If(ack).goto_next()
for i in range(4):
fsm.goto_next()
fsm(
Systask('display', 'sum=%d expected_sum=%d', sum, expected_sum)
)
fsm.goto_next()
uut = m.Instance(main, 'uut',
params=m.connect_params(main),
ports=m.connect_ports(main))
simulation.setup_waveform(m, uut, m.get_vars())
simulation.setup_clock(m, clk, hperiod=5)
init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
init.add(
Delay(1000 * 100),
Systask('finish'),
)
return m