def mkMain():
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
sum = m.OutputReg('sum', 32, initval=0)
myaxi = axi.AxiLiteSlave(m, 'myaxi', clk, rst)
fsm = FSM(m, 'fsm', clk, rst)
# request
addr, readvalid, writevalid = myaxi.pull_request(cond=fsm)
rdata = m.Reg('rdata', 32, initval=0)
fsm.If(readvalid)(rdata(addr >> 2))
fsm.If(writevalid).goto(100)
fsm.If(readvalid).goto_next()
# read
ack = myaxi.push_read_data(rdata, cond=fsm)
fsm.If(ack)(rdata(rdata + 1))
fsm.If(ack).goto_next()
fsm.goto_init()
# write
fsm.set_index(100)
data, mask, valid = myaxi.pull_write_data(cond=fsm)
fsm.If(valid)(sum(sum + data))
fsm.Then().goto_next()
fsm.goto_init()
return m
def mkMain():
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
led = m.Output('LED', 32)
myaxi = axi.AxiLiteSlave(m, 'myaxi', clk, rst)
myaxi.disable_write()
fsm = FSM(m, 'fsm', clk, rst)
# read address
addr, valid = myaxi.pull_read_request(cond=fsm)
rdata = m.Reg('rdata', 32, initval=0)
fsm.If(valid)(rdata(addr >> 2))
fsm.If(valid).goto_next()
# read rdata
ack = myaxi.push_read_data(rdata, cond=fsm)
fsm.If(ack)(rdata(rdata + 1))
fsm.Then().goto_next()
fsm.goto_init()
return m
def mkMain():
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
sum = m.OutputReg('sum', 32, initval=0)
myaxi = axi.AxiLiteSlave(m, 'myaxi', clk, rst)
myaxi.disable_read()
fsm = FSM(m, 'fsm', clk, rst)
# write address
addr, valid = myaxi.pull_write_request(cond=fsm)
fsm.If(valid).goto_next()
# write data
data, mask, valid = myaxi.pull_write_data(cond=fsm)
fsm.If(valid)(
sum(sum + data)
)
fsm.Then().goto_next()
fsm.goto_init()
return m