def fixed_to_int(fsm, value, point):
point = vtypes.raw_value(point)
return fxd.fixed_to_int(value, point)
def mkTest():
m = Module('test')
# target instance
main = mkMain()
params = m.copy_params(main)
ports = m.copy_sim_ports(main)
clk = ports['CLK']
rst = ports['RST']
xdata = ports['xdata']
xvalid = ports['xvalid']
xready = ports['xready']
ydata = ports['ydata']
yvalid = ports['yvalid']
yready = ports['yready']
zdata = ports['zdata']
zvalid = ports['zvalid']
zready = ports['zready']
xdata_orig = m.RegLike(ports['xdata'], name='xdata_orig', initval=0)
ydata_orig = m.RegLike(ports['ydata'], name='ydata_orig', initval=0)
zdata_orig = m.WireLike(ports['zdata'], name='zdata_orig')
m.Always()(xdata(fixed.to_fixed(xdata_orig, 8)))
m.Always()(ydata(fixed.to_fixed(ydata_orig, 4)))
m.Assign(zdata_orig(fixed.fixed_to_int(zdata, 8)))
uut = m.Instance(main,
'uut',
params=m.connect_params(main),
ports=m.connect_ports(main))
reset_done = m.Reg('reset_done', initval=0)
reset_stmt = []
reset_stmt.append(reset_done(0))
reset_stmt.append(xdata(0))
reset_stmt.append(xvalid(0))
reset_stmt.append(ydata(0))
reset_stmt.append(yvalid(0))
reset_stmt.append(zready(0))
reset_stmt.append(xdata_orig(0))
reset_stmt.append(ydata_orig(0))
simulation.setup_waveform(m, uut, xdata_orig, ydata_orig, zdata_orig)
simulation.setup_clock(m, clk, hperiod=5)
init = simulation.setup_reset(m, rst, reset_stmt, period=100)
nclk = simulation.next_clock
init.add(
Delay(1000),
reset_done(1),
nclk(clk),
Delay(10000),
Systask('finish'),
)
def send(name, data, valid, ready, step=1, waitnum=10):
fsm = FSM(m, name + 'fsm', clk, rst)
count = m.TmpReg(32, initval=0)
fsm.add(valid(0))
fsm.goto_next(cond=reset_done)
for _ in range(waitnum):
fsm.goto_next()
fsm.add(valid(1))
fsm.goto_next()
fsm.add(data(data + step), cond=ready)
fsm.add(count.inc(), cond=ready)
fsm.add(valid(0), cond=AndList(count == 5, ready))
fsm.goto_next(cond=AndList(count == 5, ready))
for _ in range(waitnum):
fsm.goto_next()
fsm.add(valid(1))
fsm.add(data(data + step), cond=ready)
fsm.add(count.inc(), cond=ready)
fsm.add(valid(0), cond=AndList(count == 10, ready))
fsm.goto_next(cond=AndList(count == 10, ready))
fsm.make_always()
def receive(name, data, valid, ready, waitnum=10):
fsm = FSM(m, name + 'fsm', clk, rst)
fsm.add(ready(0))
fsm.goto_next(cond=reset_done)
fsm.goto_next()
yinit = fsm.current
fsm.add(ready(1), cond=valid)
fsm.goto_next(cond=valid)
for i in range(waitnum):
fsm.add(ready(0))
fsm.goto_next()
fsm.goto(yinit)
fsm.make_always()
send('x', xdata_orig, xvalid, xready, step=1, waitnum=10)
send('y', ydata_orig, yvalid, yready, step=1, waitnum=20)
receive('z', zdata, zvalid, zready, waitnum=50)
m.Always(Posedge(clk))(If(reset_done)(
If(AndList(xvalid, xready))(Systask('display', 'xdata=%d',
xdata_orig)),
If(AndList(yvalid, yready))(Systask('display', 'ydata=%d',
ydata_orig)),
If(AndList(zvalid, zready))(Systask('display', 'zdata=%d',
zdata_orig))))
return m
def fixed_to_int(fsm, value, point, signed=False):
return fixed.fixed_to_int(value, point, signed)
def mkTest():
m = Module('test')
# target instance
main = mkMain()
params = m.copy_params(main)
ports = m.copy_sim_ports(main)
clk = ports['CLK']
rst = ports['RST']
xdata = ports['xdata']
xvalid = ports['xvalid']
xready = ports['xready']
ydata = ports['ydata']
yvalid = ports['yvalid']
yready = ports['yready']
zdata = ports['zdata']
zvalid = ports['zvalid']
zready = ports['zready']
xdata_orig = m.RegLike(ports['xdata'], name='xdata_orig', initval=0)
ydata_orig = m.RegLike(ports['ydata'], name='ydata_orig', initval=0)
zdata_orig = m.WireLike(ports['zdata'], name='zdata_orig')
m.Always()(xdata(fixed.to_fixed(xdata_orig, 8)))
m.Always()(ydata(fixed.to_fixed(ydata_orig, 4)))
m.Assign(zdata_orig(fixed.fixed_to_int(zdata, 8)))
uut = m.Instance(main, 'uut',
params=m.connect_params(main),
ports=m.connect_ports(main))
reset_done = m.Reg('reset_done', initval=0)
reset_stmt = []
reset_stmt.append(reset_done(0))
reset_stmt.append(xdata(0))
reset_stmt.append(xvalid(0))
reset_stmt.append(ydata(0))
reset_stmt.append(yvalid(0))
reset_stmt.append(zready(0))
reset_stmt.append(xdata_orig(0))
reset_stmt.append(ydata_orig(0))
simulation.setup_waveform(m, uut, xdata_orig, ydata_orig, zdata_orig)
simulation.setup_clock(m, clk, hperiod=5)
init = simulation.setup_reset(m, rst, reset_stmt, period=100)
nclk = simulation.next_clock
init.add(
Delay(1000),
reset_done(1),
nclk(clk),
Delay(10000),
Systask('finish'),
)
def send(name, data, valid, ready, step=1, waitnum=10):
fsm = FSM(m, name + 'fsm', clk, rst)
count = m.TmpReg(32, initval=0)
fsm.add(valid(0))
fsm.goto_next(cond=reset_done)
for _ in range(waitnum):
fsm.goto_next()
fsm.add(valid(1))
fsm.goto_next()
fsm.add(data(data + step), cond=ready)
fsm.add(count.inc(), cond=ready)
fsm.add(valid(0), cond=AndList(count == 5, ready))
fsm.goto_next(cond=AndList(count == 5, ready))
for _ in range(waitnum):
fsm.goto_next()
fsm.add(valid(1))
fsm.add(data(data + step), cond=ready)
fsm.add(count.inc(), cond=ready)
fsm.add(valid(0), cond=AndList(count == 10, ready))
fsm.goto_next(cond=AndList(count == 10, ready))
fsm.make_always()
def receive(name, data, valid, ready, waitnum=10):
fsm = FSM(m, name + 'fsm', clk, rst)
fsm.add(ready(0))
fsm.goto_next(cond=reset_done)
fsm.goto_next()
yinit = fsm.current
fsm.add(ready(1), cond=valid)
fsm.goto_next(cond=valid)
for i in range(waitnum):
fsm.add(ready(0))
fsm.goto_next()
fsm.goto(yinit)
fsm.make_always()
send('x', xdata_orig, xvalid, xready, step=1, waitnum=10)
send('y', ydata_orig, yvalid, yready, step=-2, waitnum=20)
receive('z', zdata, zvalid, zready, waitnum=50)
m.Always(Posedge(clk))(
If(reset_done)(
If(AndList(xvalid, xready))(
Systask('display', 'xdata=%d', xdata_orig)
),
If(AndList(yvalid, yready))(
Systask('display', 'ydata=%d', ydata_orig)
),
If(AndList(zvalid, zready))(
Systask('display', 'zdata=%d', zdata_orig)
)
)
)
return m
def mkTest(n=8, datawidth=16, point=8):
m = Module('test')
main = mkFFT(n, datawidth, point)
params = m.copy_params(main)
ports = m.copy_sim_ports(main)
clk = ports['CLK']
rst = ports['RST']
din = [(ports['din' + str(i) + 're'], ports['din' + str(i) + 'im'])
for i in range(n)]
dout = [(ports['dout' + str(i) + 're'], ports['dout' + str(i) + 'im'])
for i in range(n)]
weight = [(ports['weight' + str(i) + 're'], ports['weight' + str(i) + 'im'])
for i in range(int(n * log2(n) / 2))]
_din = [(m.WireLike(re, name='_' + re.name, width=datawidth - point),
m.WireLike(im, name='_' + im.name, width=datawidth - point))
for re, im in din]
_dout = [(m.WireLike(re, name='_' + re.name, width=datawidth - point),
m.WireLike(im, name='_' + im.name, width=datawidth - point))
for re, im in dout]
_weight = [(m.WireLike(re, name='_' + re.name, width=datawidth - point),
m.WireLike(im, name='_' + im.name, width=datawidth - point))
for re, im in weight]
for (lre, lim), (rre, rim) in zip(_din, din):
m.Assign(lre(fixed.fixed_to_int(rre, point)))
m.Assign(lim(fixed.fixed_to_int(rim, point)))
for (lre, lim), (rre, rim) in zip(_dout, dout):
m.Assign(lre(fixed.fixed_to_int(rre, point)))
m.Assign(lim(fixed.fixed_to_int(rim, point)))
for (lre, lim), (rre, rim) in zip(_weight, weight):
m.Assign(lre(fixed.fixed_to_int(rre, point)))
m.Assign(lim(fixed.fixed_to_int(rim, point)))
uut = m.Instance(main, 'uut',
params=m.connect_params(main),
ports=m.connect_ports(main))
reset_done = m.Reg('reset_done', initval=0)
reset_stmt = []
reset_stmt.append(reset_done(0))
for i, (re, im) in enumerate(din):
reset_stmt.append(re(fixed.to_fixed(i, point)))
reset_stmt.append(im(fixed.to_fixed(i, point)))
weight_value = gen_weight(n)
for i, (re, im) in enumerate(weight):
wr, wi = weight_value[i]
reset_stmt.append(re(fixed.to_fixed(wr, point)))
reset_stmt.append(im(fixed.to_fixed(wi, point)))
simulation.setup_waveform(m, uut, *(_din + _dout + _weight))
simulation.setup_clock(m, clk, hperiod=5)
init = simulation.setup_reset(m, rst, reset_stmt, period=100)
nclk = simulation.next_clock
init.add(
Delay(1000),
reset_done(1),
nclk(clk),
Delay(10000),
Systask('finish'),
)
def dump(name, v, point):
return Systask('display', name + '= %f', fixed.fixed_to_real(v, point))
send_fsm = FSM(m, 'send_fsm', clk, rst)
send_fsm.goto_next(cond=reset_done)
# for i, (re, im) in enumerate(weight):
# send_fsm.add( dump('w[%d]re' % i, re, point) )
# send_fsm.add( dump('w[%d]im' % i, im, point) )
for i, (re, im) in enumerate(din):
send_fsm.add(re(fixed.to_fixed(i, point)))
send_fsm.add(im(fixed.to_fixed(i, point)))
# send_fsm.add( dump('din[%d]re' % i, re, point), delay=1 )
# send_fsm.add( dump('din[%d]im' % i, im, point), delay=1 )
send_fsm.goto_next()
for i, (re, im) in enumerate(din):
send_fsm.add(re(fixed.to_fixed(0, point)))
send_fsm.add(im(fixed.to_fixed(0, point)))
send_fsm.goto_next()
for _ in range(100):
# for i, (re, im) in enumerate(dout):
# send_fsm.add( dump('dout[%d]re' % i, re, point), delay=1 )
# send_fsm.add( dump('dout[%d]im' % i, im, point), delay=1 )
send_fsm.goto_next()
send_fsm.add(Systask('finish'))
send_fsm.make_always()
return m
def mkTest(n=8, datawidth=16, point=8):
m = Module('test')
main = mkFFT(n, datawidth, point)
params = m.copy_params(main)
ports = m.copy_sim_ports(main)
clk = ports['CLK']
rst = ports['RST']
din = [(ports['din' + str(i) + 're'], ports['din' + str(i) + 'im'])
for i in range(n)]
dout = [(ports['dout' + str(i) + 're'], ports['dout' + str(i) + 'im'])
for i in range(n)]
weight = [(ports['weight' + str(i) + 're'],
ports['weight' + str(i) + 'im'])
for i in range(int(n * log2(n) / 2))]
_din = [(m.WireLike(re, name='_' + re.name, width=datawidth - point),
m.WireLike(im, name='_' + im.name, width=datawidth - point))
for re, im in din]
_dout = [(m.WireLike(re, name='_' + re.name, width=datawidth - point),
m.WireLike(im, name='_' + im.name, width=datawidth - point))
for re, im in dout]
_weight = [(m.WireLike(re, name='_' + re.name, width=datawidth - point),
m.WireLike(im, name='_' + im.name, width=datawidth - point))
for re, im in weight]
for (lre, lim), (rre, rim) in zip(_din, din):
m.Assign(lre(fixed.fixed_to_int(rre, point)))
m.Assign(lim(fixed.fixed_to_int(rim, point)))
for (lre, lim), (rre, rim) in zip(_dout, dout):
m.Assign(lre(fixed.fixed_to_int(rre, point)))
m.Assign(lim(fixed.fixed_to_int(rim, point)))
for (lre, lim), (rre, rim) in zip(_weight, weight):
m.Assign(lre(fixed.fixed_to_int(rre, point)))
m.Assign(lim(fixed.fixed_to_int(rim, point)))
uut = m.Instance(main,
'uut',
params=m.connect_params(main),
ports=m.connect_ports(main))
reset_done = m.Reg('reset_done', initval=0)
reset_stmt = []
reset_stmt.append(reset_done(0))
for i, (re, im) in enumerate(din):
reset_stmt.append(re(fixed.to_fixed(i, point)))
reset_stmt.append(im(fixed.to_fixed(i, point)))
weight_value = gen_weight(n)
for i, (re, im) in enumerate(weight):
wr, wi = weight_value[i]
reset_stmt.append(re(fixed.to_fixed(wr, point)))
reset_stmt.append(im(fixed.to_fixed(wi, point)))
simulation.setup_waveform(m, uut, *(_din + _dout + _weight))
simulation.setup_clock(m, clk, hperiod=5)
init = simulation.setup_reset(m, rst, reset_stmt, period=100)
nclk = simulation.next_clock
init.add(
Delay(1000),
reset_done(1),
nclk(clk),
Delay(10000),
Systask('finish'),
)
def dump(name, v, point):
return Systask('display', name + '= %f', fixed.fixed_to_real(v, point))
send_fsm = FSM(m, 'send_fsm', clk, rst)
send_fsm.goto_next(cond=reset_done)
# for i, (re, im) in enumerate(weight):
# send_fsm.add( dump('w[%d]re' % i, re, point) )
# send_fsm.add( dump('w[%d]im' % i, im, point) )
for i, (re, im) in enumerate(din):
send_fsm.add(re(fixed.to_fixed(i, point)))
send_fsm.add(im(fixed.to_fixed(i, point)))
# send_fsm.add( dump('din[%d]re' % i, re, point), delay=1 )
# send_fsm.add( dump('din[%d]im' % i, im, point), delay=1 )
send_fsm.goto_next()
for i, (re, im) in enumerate(din):
send_fsm.add(re(fixed.to_fixed(0, point)))
send_fsm.add(im(fixed.to_fixed(0, point)))
send_fsm.goto_next()
for _ in range(100):
# for i, (re, im) in enumerate(dout):
# send_fsm.add( dump('dout[%d]re' % i, re, point), delay=1 )
# send_fsm.add( dump('dout[%d]im' % i, im, point), delay=1 )
send_fsm.goto_next()
send_fsm.add(Systask('finish'))
send_fsm.make_always()
return m
def fixed_to_int(fsm, value, point):
point = vtypes.raw_value(point)
return fxd.fixed_to_int(value, point)
