def test_fix_rule_019(self):
oRule = component.rule_019()
oRule.fix(oFileComment)
oRule.analyze(oFileComment)
self.assertEqual(oRule.violations, [])
self.assertEqual(oFileComment.lines[7].line, ' generic_1 : std_logic := \'0\';')
self.assertEqual(oFileComment.lines[12].line, ' port_2 : in std_logic;')
self.assertEqual(oFileComment.lines[14].line, ' port_4 : out std_logic;')
def test_rule_019(self):
oRule = component.rule_019()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'component')
self.assertEqual(oRule.identifier, '019')
dExpected = utils.add_violation_list([7, 12, 14])
oRule.analyze(oFileComment)
self.assertEqual(oRule.violations, dExpected)
def test_fix_rule_019(self):
oRule = component.rule_019()
oRule.fix(self.oFile)
lActual = self.oFile.get_lines()
self.assertEqual(lExpected, lActual)
oRule.analyze(self.oFile)
self.assertEqual(oRule.violations, [])
def test_rule_019(self):
oRule = component.rule_019()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'component')
self.assertEqual(oRule.identifier, '019')
lExpected = [6, 8, 9, 12, 14, 15, 23, 26, 31, 33, 35]
oRule.analyze(self.oFile)
self.assertEqual(
lExpected,
utils.extract_violation_lines_from_violation_object(
oRule.violations))