def test_rule_016(self):
self.maxDiff = None
oRule = signal.rule_016()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'signal')
self.assertEqual(oRule.identifier, '016')
dExpected = [5, 8, 20, 23, 27, 32, 42, 45, 49, 54, 60, 67]
dExpected = [{
'endLine': 6,
'line':
' signal sig1, sig2, sig3, sig4, sig5, sig6 : std_logic;',
'lineNumber': 5
}, {
'endLine': 13,
'line':
' signal siga, sigb, sigc, sigd, sige, sigf : std_logic; -- This is a comment',
'lineNumber': 8
}, {
'endLine': 21,
'line': ' signal sig1 : std_logic ;',
'lineNumber': 20
}, {
'endLine': 25,
'line': ' signal sig1 : std_logic ;',
'lineNumber': 23
}, {
'endLine': 30,
'line': ' signal sig1 : std_logic ;',
'lineNumber': 27
}, {
'endLine': 36,
'line': ' signal sig1 : std_logic ;',
'lineNumber': 32
}, {
'endLine': 43,
'line': ' signal sig1, sig2 : std_logic ;',
'lineNumber': 42
}, {
'endLine': 47,
'line': ' signal sig1, sig2 : std_logic ;',
'lineNumber': 45
}, {
'endLine': 52,
'line': ' signal sig1, sig2 : std_logic ;',
'lineNumber': 49
}, {
'endLine': 58,
'line': ' signal sig1, sig2 : std_logic ;',
'lineNumber': 54
}, {
'endLine': 65,
'line': ' signal sig1 , sig2 : std_logic ;',
'lineNumber': 60
}, {
'endLine': 73,
'line': ' signal sig1 , sig2 : std_logic ;',
'lineNumber': 67
}]
oRule.analyze(self.oFile)
self.assertEqual(oRule.violations, dExpected)
def test_fix_rule_016(self):
oRule = signal.rule_016()
oRule.fix(self.oFile)
oRule.analyze(self.oFile)
self.assertEqual(self.oFile.lines[5].line, ' signal sig1, sig2, sig3, sig4, sig5, sig6 : std_logic;')
self.assertTrue(self.oFile.lines[5].isSignal)
self.assertTrue(self.oFile.lines[5].insideSignal)
self.assertTrue(self.oFile.lines[5].isEndSignal)
self.assertEqual(self.oFile.lines[7].line, ' signal siga, sigb, sigc, sigd, sige, sigf : std_logic; -- This is a comment')
self.assertTrue(self.oFile.lines[7].isSignal)
self.assertTrue(self.oFile.lines[7].insideSignal)
self.assertTrue(self.oFile.lines[7].isEndSignal)
self.assertFalse(self.oFile.lines[7].isComment)
self.assertTrue(self.oFile.lines[7].hasComment)
self.assertTrue(self.oFile.lines[7].hasInlineComment)
self.assertEqual(self.oFile.lines[7].commentColumn, 77)
self.assertEqual(self.oFile.lines[12].line, ' signal sig1 : std_logic;')
self.assertEqual(self.oFile.lines[14].line, ' signal sig1 : std_logic ;')
self.assertEqual(self.oFile.lines[16].line, ' signal sig1 : std_logic ;')
self.assertEqual(self.oFile.lines[18].line, ' signal sig1 : std_logic ;')
self.assertEqual(self.oFile.lines[20].line, ' signal sig1 : std_logic ;')
self.assertEqual(self.oFile.lines[24].line, ' signal sig1, sig2 : std_logic;')
self.assertEqual(self.oFile.lines[26].line, ' signal sig1, sig2 : std_logic ;')
self.assertEqual(self.oFile.lines[28].line, ' signal sig1, sig2 : std_logic ;')
self.assertEqual(self.oFile.lines[30].line, ' signal sig1, sig2 : std_logic ;')
self.assertEqual(self.oFile.lines[32].line, ' signal sig1, sig2 : std_logic ;')
self.assertEqual(self.oFile.lines[34].line, ' signal sig1 , sig2 : std_logic ;')
self.assertEqual(self.oFile.lines[36].line, ' signal sig1 , sig2 : std_logic ;')
self.assertEqual(oRule.violations, [])
def test_fix_rule_016(self):
oRule = signal.rule_016()
oRule.fix(self.oFile)
lActual = self.oFile.get_lines()
self.assertEqual(lExpected, lActual)
oRule.analyze(self.oFile)
self.assertEqual(oRule.violations, [])
def test_rule_016(self):
oRule = signal.rule_016()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'signal')
self.assertEqual(oRule.identifier, '016')
lExpected = [5, 8, 20, 23, 27, 32, 42, 45, 49, 54, 60, 67]
oRule.analyze(self.oFile)
self.assertEqual(
lExpected,
utils.extract_violation_lines_from_violation_object(
oRule.violations))
def test_rule_016(self):
self.maxDiff = None
oRule = signal.rule_016()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'signal')
self.assertEqual(oRule.identifier, '016')
dExpected = [5,8,20,23,27,32,42,45,49,54,60,67]
lExpected = []
dViolation = utils.add_violation(5)
dViolation['endLine'] = 6
dViolation['line'] = ' signal sig1, sig2, sig3, sig4, sig5, sig6 : std_logic;'
lExpected.append(dViolation)
dViolation = utils.add_violation(8)
dViolation['endLine'] = 13
dViolation['line'] = ' signal siga, sigb, sigc, sigd, sige, sigf : std_logic; -- This is a comment'
lExpected.append(dViolation)
dViolation = utils.add_violation(20)
dViolation['endLine'] = 21
dViolation['line'] = ' signal sig1 : std_logic ;'
lExpected.append(dViolation)
dViolation = utils.add_violation(23)
dViolation['endLine'] = 25
dViolation['line'] = ' signal sig1 : std_logic ;'
lExpected.append(dViolation)
dViolation = utils.add_violation(27)
dViolation['endLine'] = 30
dViolation['line'] = ' signal sig1 : std_logic ;'
lExpected.append(dViolation)
dViolation = utils.add_violation(32)
dViolation['endLine'] = 36
dViolation['line'] = ' signal sig1 : std_logic ;'
lExpected.append(dViolation)
dViolation = utils.add_violation(42)
dViolation['endLine'] = 43
dViolation['line'] = ' signal sig1, sig2 : std_logic ;'
lExpected.append(dViolation)
dViolation = utils.add_violation(45)
dViolation['endLine'] = 47
dViolation['line'] = ' signal sig1, sig2 : std_logic ;'
lExpected.append(dViolation)
dViolation = utils.add_violation(49)
dViolation['endLine'] = 52
dViolation['line'] = ' signal sig1, sig2 : std_logic ;'
lExpected.append(dViolation)
dViolation = utils.add_violation(54)
dViolation['endLine'] = 58
dViolation['line'] = ' signal sig1, sig2 : std_logic ;'
lExpected.append(dViolation)
dViolation = utils.add_violation(60)
dViolation['endLine'] = 65
dViolation['line'] = ' signal sig1 , sig2 : std_logic ;'
lExpected.append(dViolation)
dViolation = utils.add_violation(67)
dViolation['endLine'] = 73
dViolation['line'] = ' signal sig1 , sig2 : std_logic ;'
lExpected.append(dViolation)
oRule.analyze(self.oFile)
self.assertEqual(oRule.violations, lExpected)