def _analyze(self, oFile, oLine, iLineNumber): sLine = utils.remove_comment(oLine.line) if sLine[-2:] == '--': sLine = sLine[:-2] if '-' in sLine: lLine = sLine.split() for sWord in lLine: if '-' in sWord: if sWord == '-': # already good. continue if re.match(r".*?'-'", sWord) is not None: # found a std_logic don't care. continue if re.match(r'(?:".*"|[^"\n])*?-', sWord) is None: # The - was in a quoted string. # e.g. found a std_logic_vector constant with a don't care. continue #if re.match('^.*\W-[0-9]', sWord) is not None: # # found a negative number # continue if re.match('^.*\w-', sWord): dViolation = utils.create_violation_dict(iLineNumber) self.add_violation(dViolation) elif not re.match('^.*-[0-9]+\)?$', sWord): dViolation = utils.create_violation_dict(iLineNumber) self.add_violation(dViolation) else: if re.match('^.*[\w+|\)][+|/|*]', sLine) or re.match( '^.*[+|/|*][\w+|\(]', sLine): if not re.match('^.*".*/.*"', sLine): dViolation = utils.create_violation_dict(iLineNumber) self.add_violation(dViolation)
def multiline_alignment_with_parenthesis(self, iColumn, oLine, iLineNumber, dParenthesis): ''' Checks the alignment of multiline statements taking parenthesis into account. Parameters: self: (rule object) iColumn: (integer) oLine: (line object) iLineNumber: (integer) dParenthesis: (dictionary) ''' for iIndex in range(dParenthesis[iLineNumber]['begin'], iLineNumber): iParenthesisColumn = _find_right_most_open_parenthesis(dParenthesis, iLineNumber) if iParenthesisColumn is None: if not dParenthesis[iLineNumber]['character'] == iColumn: self.add_violation(utils.create_violation_dict(iLineNumber)) self.dFix['violations'][iLineNumber] = {} self.dFix['violations'][iLineNumber]['column'] = iColumn else: if not dParenthesis[iLineNumber]['character'] == iParenthesisColumn + 1: self.add_violation(utils.create_violation_dict(iLineNumber)) self.dFix['violations'][iLineNumber] = {} self.dFix['violations'][iLineNumber]['column'] = iParenthesisColumn + 1 offset = iParenthesisColumn + 1 - dParenthesis[iLineNumber]['character'] for iIndex in range(len(dParenthesis[iLineNumber]['open'])): dParenthesis[iLineNumber]['open'][iIndex] += offset
def _analyze(self, oFile, oLine, iLineNumber): if oLine.isIfKeyword and not re.match('^\s*if\s*\(', oLine.lineNoComment.lower()): dViolation = utils.create_violation_dict(iLineNumber) self.add_violation(dViolation) if oLine.isElseIfKeyword and re.match('^\s*elsif\s+\w', oLine.lineNoComment.lower()): dViolation = utils.create_violation_dict(iLineNumber) self.add_violation(dViolation)
def _analyze(self, oFile, oLine, iLineNumber): if self.clock == 'event': if oLine.isClockStatement and re.match('^.*ing_edge\s*\(', oLine.lineLower): dViolation = utils.create_violation_dict(iLineNumber) self.add_violation(dViolation) elif self.clock == 'edge': if oLine.isClockStatement and '\'event' in oLine.lineLower: dViolation = utils.create_violation_dict(iLineNumber) self.add_violation(dViolation) else: raise Exception("clock option needs to be 'event' or 'edge', detected: {self.clock}")
def _analyze(self, oFile, oLine, iLineNumber): if oLine.isArchitectureKeyword: self.sLabel = oLine.line.split()[1] if oLine.isEndArchitecture and not re.match('^\s*end\s+architecture\s+\w+', oLine.line, re.IGNORECASE): if re.match('^\s*end\s+architecture', oLine.line, re.IGNORECASE): dViolation = utils.create_violation_dict(iLineNumber) dViolation['label'] = self.sLabel self.add_violation(dViolation) elif not re.match('^\s*end\s+\w+', oLine.line, re.IGNORECASE): dViolation = utils.create_violation_dict(iLineNumber) dViolation['label'] = self.sLabel self.add_violation(dViolation)
def _analyze(self, oFile, oLine, iLineNumber): if oLine.isFunctionKeyword and function_has_parameters(oLine.line): if not re.match('^\s*function\s+\w+\s\(', oLine.lineLower) and \ not re.match('^\s*impure\s+function\s+\w+\s\(', oLine.lineLower) and \ not re.match('^\s*pure\s+function\s+\w+\s\(', oLine.lineLower): dViolation = utils.create_violation_dict(iLineNumber) self.add_violation(dViolation)
def analyze(self, oFile): iMaxSignalIndex = 0 lIndexes = [] dSignals = {} for iLineNumber, oLine in enumerate(oFile.lines): if self._is_vsg_off(oLine): continue if oLine.isSignal and re.match('^\s*signal\s+\S+,\s*\S+\s*:', oLine.line, flags=re.IGNORECASE): dSignals[iLineNumber] = {} dSignals[iLineNumber]['comma'] = 0 for iIndex, sChar in enumerate(oLine.line): if dSignals[iLineNumber]['comma'] > 0 and not sChar == ' ': iMaxSignalIndex = max(iMaxSignalIndex, iIndex + 1) dSignals[iLineNumber]['signal'] = iIndex + 1 break if sChar == ',': dSignals[iLineNumber]['comma'] = iIndex + 1 lIndexes.append(iLineNumber) if oLine.isArchitectureBegin: for iIndex in lIndexes: dSignals[iIndex]['max'] = iMaxSignalIndex if iMaxSignalIndex > dSignals[iIndex]['signal']: dViolation = utils.create_violation_dict(iIndex) dViolation['comma'] = dSignals[iIndex]['comma'] dViolation['signal'] = dSignals[iIndex]['signal'] dViolation['max'] = dSignals[iIndex]['max'] self.add_violation(dViolation) lIndexes = []
def check_violations(self, lWords, iLineNumber): for sWord in lWords: if sWord.lower() in map(str.lower, self.dDatabase['procedure']): if sWord not in self.dDatabase['procedure']: dViolation = utils.create_violation_dict(iLineNumber) dViolation['procedure'] = sWord self.add_violation(dViolation)
def analyze(self, oFile): fCheckForBlanks = False fBlanksFound = False fNonBlanksFound = False fSkipProcess = False for iLineNumber, oLine in enumerate(oFile.lines): if not self._is_vsg_off(oLine): if oLine.insideProcess: if oLine.isProcessBegin and oLine.isSensitivityListEnd: fSkipProcess = True if oLine.isSensitivityListEnd and oFile.lines[ iLineNumber + 1].isProcessBegin: fSkipProcess = True if fSkipProcess: if oLine.isEndProcess: fSkipProcess = False continue # pragma: no cover if oLine.isProcessBegin: if fBlanksFound and not fNonBlanksFound: dViolation = utils.create_violation_dict( iLineNumber) self.add_violation(dViolation) fCheckForBlanks = False fBlanksFound = False fNonBlanksFound = False fSkipProcess = True if fCheckForBlanks: if oLine.isBlank: fBlanksFound = True else: fNonBlanksFound = True if oLine.isSensitivityListEnd: fCheckForBlanks = True
def are_there_spaces_after(self, sString, oLine, iLineNumber, iSpaces): ''' Checks if a space is after the string given. The string is considered a whole word. Allowances are made for end of line and semicolons. Parameters: self: (rule object) sString: (string) oLine: (line object) iLineNumber: (integer) iSpaces: (integer) ''' sSpaces = ' ' * iSpaces if not sString.lower() in oLine.lineLower: return if re.match('^.*' + sString + ';', oLine.lineLower): return if re.match('^.*' + sString + '$', oLine.lineLower): return if re.match('^.*' + sString + sSpaces + '\S', oLine.lineLower): return if not re.match('^.*\s+' + sString + sSpaces + '\S', oLine.lineLower) and \ not re.match('^\s*' + sString + sSpaces + '\S', oLine.lineLower) and \ not re.match('^.*\S\s' + sString + '\'', oLine.lineLower): self.add_violation(utils.create_violation_dict(iLineNumber))
def analyze(self, oFile): fCheckForBlanks = False fSkipProcess = False iBlankCount = 0 iFailingLineNumber = 0 for iLineNumber, oLine in enumerate(oFile.lines): if not self._is_vsg_off(oLine): if oLine.insideProcess: if oLine.isProcessBegin and oLine.isSensitivityListEnd: fSkipProcess = True if oLine.isSensitivityListEnd and oFile.lines[ iLineNumber + 1].isProcessBegin: fSkipProcess = True if fSkipProcess: if oLine.isEndProcess: fSkipProcess = False continue # pragma: no cover if fCheckForBlanks: if oLine.isBlank: iBlankCount += 1 else: if not iBlankCount == 1 and not oLine.isProcessBegin: dViolation = utils.create_violation_dict( iFailingLineNumber) self.add_violation(dViolation) fSkipProcess = True fCheckForBlanks = False iBlankCount = 0 if oLine.isSensitivityListEnd: fCheckForBlanks = True iFailingLineNumber = iLineNumber
def indent_of_comments_above_item(self, oFile, iLine, iIndentLevel): ''' Checks the indent level of consecutive comment lines above the line number given. Parameters: self: (rule object) oFile: (vhdlFile object) iLine: (integer) ''' for iIndex in range(iLine - 1, 0, -1): oLine = oFile.lines[iIndex] if oLine.begins_with_token(parser.comment, True): if oLine.get_indent_value() != len( iIndentLevel * self.indentSize * ' '): dViolation = utils.create_violation_dict(iIndex) dViolation['indent'] = iIndentLevel self.add_violation(dViolation) else: oLine.indentLevel = iIndentLevel else: break
def _analyze(self, oFile, oLine, iLineNumber): if oLine.isPackageKeyword: if len(oLine.line.split()) > 2: if re.match('^\s*package\s+\S+\s+is', oLine.lineLower): if not re.match('^\s*package\s\S+\sis', oLine.lineLower): dViolation = utils.create_violation_dict(iLineNumber) self.add_violation(dViolation)
def _analyze(self, oFile, oLine, iLineNumber): if oLine.isInstantiationDeclaration and not oLine.isDirectInstantiationDeclaration: if re.match('^\s*\w+\s*:\s*component', oLine.line, flags=re.IGNORECASE): dViolation = utils.create_violation_dict(iLineNumber) self.add_violation(dViolation)
def _analyze(self, oFile, oLine, iLineNumber): if oLine.isGenerateLabel: self.sGenerateName = oLine.line.lstrip().split(':')[0] if oLine.isGenerateEnd and not re.match('^\s*\S+\s+\S+\s+\S+', oLine.line): dViolation = utils.create_violation_dict(iLineNumber) dViolation['label'] = self.sGenerateName self.add_violation(dViolation)
def indent_of_comments_above(self, oFile, iLineNumber): ''' Checks the indent level of consecutive comment lines above the line number given. Parameters: self: (rule object) oFile: (vhdlFile object) iLineNumber: (integer) ''' iIndex = 0 while iLineNumber - iIndex > 1: iIndex += 1 iPreviousIndex = iLineNumber - iIndex if not oFile.lines[iPreviousIndex].isComment: break else: if not oFile.lines[iPreviousIndex].line.index( '--' ) == oFile.lines[iLineNumber].indentLevel * self.indentSize: dViolation = utils.create_violation_dict(iPreviousIndex) dViolation['indent'] = oFile.lines[iLineNumber].indentLevel self.add_violation(dViolation) else: oFile.lines[iPreviousIndex].indentLevel = oFile.lines[ iLineNumber].indentLevel
def _analyze(self, oFile, oLine, iLineNumber): if oLine.isEntityDeclaration: self.sEntityName = utils.extract_entity_identifier(oLine)[0] if oLine.isEndEntityDeclaration and re.match('^\s*end\s+entity', oLine.line, re.IGNORECASE): if not re.match('^\s*end\s+entity\s+\w+', oLine.line, re.IGNORECASE): dViolation = utils.create_violation_dict(iLineNumber) dViolation['entity'] = self.sEntityName self.add_violation(dViolation)
def _analyze(self, oFile, oLine, iLineNumber): if oLine.isInstantiationPortAssignment: if re.match('^\s*\S+\s*=>\s*.*\s*,\s*\S+\s*=>', oLine.line): sTemp = re.match('(^\s*\S+\s*=>\s*.*\s*),\s*\S+\s*=>', oLine.line).group(0) if sTemp.count('(') == sTemp.count(')'): dViolation = utils.create_violation_dict(iLineNumber) self.add_violation(dViolation)
def _analyze(self, oFile, oLine, iLineNumber): if oLine.isPortDeclaration: sLine = oLine.line.split(':')[1] if '(' in sLine: sLine = sLine.split('(')[0] if not utils.is_port_mode(sLine.split()[0]): dViolation = utils.create_violation_dict(iLineNumber) self.add_violation(dViolation)
def _analyze(self, oFile, oLine, iLineNumber): sLine = oLine.lineNoComment if re.match('^.*\)[and|nand|or|nor|xor|xnor]', sLine, flags=re.IGNORECASE): dViolation = utils.create_violation_dict(iLineNumber) self.add_violation(dViolation) if re.match('^.* and\(', sLine, flags=re.IGNORECASE): dViolation = utils.create_violation_dict(iLineNumber) self.add_violation(dViolation) if re.match('^.* nand\(', sLine, flags=re.IGNORECASE): dViolation = utils.create_violation_dict(iLineNumber) self.add_violation(dViolation) if re.match('^.* or\(', sLine, flags=re.IGNORECASE): dViolation = utils.create_violation_dict(iLineNumber) self.add_violation(dViolation) if re.match('^.* nor\(', sLine, flags=re.IGNORECASE): dViolation = utils.create_violation_dict(iLineNumber) self.add_violation(dViolation) if re.match('^.* xor\(', sLine, flags=re.IGNORECASE): dViolation = utils.create_violation_dict(iLineNumber) self.add_violation(dViolation) if re.match('^.* xnor\(', sLine, flags=re.IGNORECASE): dViolation = utils.create_violation_dict(iLineNumber) self.add_violation(dViolation)
def _analyze(self, oFile, oLine, iLineNumber): if oLine.insideInstantiation: if ',' in oLine.lineNoComment: lLine = oLine.lineNoComment.split(',') for sString in lLine[:-1]: if '=>' not in sString: dViolation = utils.create_violation_dict(iLineNumber) self.add_violation(dViolation) break
def _analyze(self, oFile, oLine, iLineNumber): if oLine.__dict__['hasInlineComment']: match = has_comment_re.match(oLine.line) if match is None: return idx = match.start("comment") if oLine.line[idx - 1] != ' ': dViolation = utils.create_violation_dict(iLineNumber) self.add_violation(dViolation)
def _analyze(self, oFile, oLine, iLineNumber): if oLine.isGenerateLabel: self.lGenerateNames.append(utils.extract_label(oLine)[0]) if oLine.isGenerateEnd and not oLine.isGenerateEndLabel: dViolation = utils.create_violation_dict(iLineNumber) dViolation['label'] = self.lGenerateNames.pop() self.add_violation(dViolation) if oLine.isGenerateEnd and oLine.isGenerateEndLabel: self.lGenerateNames.pop()
def _update_violation(self, iLineNumber, sLine): dViolation = utils.create_violation_dict(iLineNumber) dViolation['slice_index'] = [] iStartIndex = 0 while sLine.find(' else', iStartIndex) > 0: iIndex = sLine.find(' else', iStartIndex) + len(' else') dViolation['slice_index'].append(iIndex) iStartIndex = iIndex self.add_violation(dViolation)
def _analyze(self, oFile, oLine, iLineNumber): if oLine.isProcessKeyword: if oLine.isProcessLabel: self.previousLabel = utils.extract_label(oLine)[0] self.fProcessHadBeginLabel = True if oLine.isEndProcess: if not oLine.isProcessEndLabel: dViolation = utils.create_violation_dict(iLineNumber) if self.fProcessHadBeginLabel: dViolation['processLabel'] = self.previousLabel self.add_violation(dViolation) self.fProcessHadBeginLabel = False
def _analyze(self, oFile, oLine, iLineNumber): if oLine.insideClockProcess: if oLine.isSequentialEnd: self.sequentialStatement += oLine.lineNoComment + " " if not re.match('^\s*.*\safter\s', self.sequentialStatement): dViolation = utils.create_violation_dict(iLineNumber) self.add_violation(dViolation) self.sequentialStatement = "" elif oLine.insideSequential: self.sequentialStatement += oLine.lineNoComment + " " elif oLine.isSequential: self.sequentialStatement = oLine.lineNoComment + " "
def _analyze(self, oFile, oLine, iLineNumber): if oLine.insideSensitivityList: self.sSensitivityList += oLine.lineNoComment if not re.match('^\s*\)', oLine.lineNoComment): self.iCount += 1 if oLine.isSensitivityListEnd: if self.iCount == self.sSensitivityList.count(',') + 1: if self.iCount > 1: dViolation = utils.create_violation_dict(iLineNumber) self.add_violation(dViolation) self.iCount = 0 self.sSensitivityList = ''
def _analyze(self, oFile, oLine, iLineNumber): if oLine.isSignal: self.sFullLine = '' self.iFailureLine = iLineNumber if oLine.insideSignal: self.sFullLine += oLine.line if oLine.isEndSignal: if not oLine.isSignal: dViolation = utils.create_violation_dict(self.iFailureLine) dViolation['endLine'] = iLineNumber dViolation['line'] = self.sFullLine self.add_violation(dViolation)
def check_for_blanks(self, dVars, oLine, iLineNumber): if dVars['fCheckForBlanks']: if oLine.isBlank: dVars['iBlankCount'] += 1 if not oLine.isBlank and not oLine.isProcessBegin: dVars['iBlankCount'] = 0 if oLine.isProcessBegin: if not dVars['iBlankCount'] == 1: dViolation = utils.create_violation_dict(iLineNumber) self.add_violation(dViolation) dVars['fSkipProcess'] = True dVars['fCheckForBlanks'] = False dVars['iBlankCount'] = 0
def _analyze(self, oFile, oLine, iLineNumber): if oLine.isArchitectureKeyword: self.ofMissing = False # Search for of statement if self.ofMissing and re.match('^\s*of', oLine.line, re.IGNORECASE): self.ofMissing = False self.dViolation['of_line'] = iLineNumber self.add_violation(self.dViolation) # Check architecture statement for "of" if oLine.isArchitectureKeyword and not re.match( '^\s*architecture\s+\w+\s+of', oLine.line, re.IGNORECASE): self.dViolation = utils.create_violation_dict(iLineNumber) self.ofMissing = True