def run(
architecture_file,
circuit_file,
include_files,
output_netlist,
command_runner=vtr.CommandRunner(),
temp_dir=Path("."),
odin_args="--adder_type default",
log_filename="odin.out",
odin_exec=None,
odin_config=None,
min_hard_mult_size=3,
min_hard_adder_size=1,
):
"""
Runs ODIN II on the specified architecture file and circuit file
.. note :: Usage: vtr.odin.run(<architecture_file>,<circuit_file>,<output_netlist>,[OPTIONS])
Arguments
=========
architecture_file :
Architecture file to target
circuit_file :
Circuit file to optimize
output_netlist :
File name to output the resulting circuit to
Other Parameters
----------------
command_runner :
A CommandRunner object used to run system commands
temp_dir :
Directory to run in (created if non-existent)
odin_args:
A dictionary of keyword arguments to pass on to ODIN II
log_filename :
File to log result to
odin_exec:
ODIN II executable to be run
odin_config:
The ODIN II configuration file
min_hard_mult_size :
Tells ODIN II the minimum multiplier size that should be implemented using
hard multiplier (if available)
min_hard_adder_size :
Tells ODIN II the minimum adder size that should be implemented
using hard adder (if available).
"""
temp_dir = Path(temp_dir) if not isinstance(temp_dir, Path) else temp_dir
temp_dir.mkdir(parents=True, exist_ok=True)
if odin_args is None:
odin_args = OrderedDict()
# Verify that files are Paths or convert them to Paths and check that they exist
architecture_file = vtr.verify_file(architecture_file, "Architecture")
circuit_file = vtr.verify_file(circuit_file, "Circuit")
output_netlist = vtr.verify_file(output_netlist, "Output netlist", False)
if odin_exec is None:
odin_exec = str(vtr.paths.odin_exe_path)
if odin_config is None:
odin_base_config = str(vtr.paths.odin_cfg_path)
else:
odin_base_config = str(Path(odin_config).resolve())
# Copy the config file
odin_config = "odin_config.xml"
odin_config_full_path = str(temp_dir / odin_config)
shutil.copyfile(odin_base_config, odin_config_full_path)
# Create a list showing all (.v) and (.vh) files
circuit_list = create_circuits_list(circuit_file, include_files)
init_config_file(
odin_config_full_path,
circuit_list,
architecture_file.name,
output_netlist.name,
vtr.determine_memory_addr_width(str(architecture_file)),
min_hard_mult_size,
min_hard_adder_size,
)
cmd = [odin_exec]
use_odin_simulation = False
if "use_odin_simulation" in odin_args:
use_odin_simulation = True
del odin_args["use_odin_simulation"]
for arg, value in odin_args.items():
if isinstance(value, bool) and value:
cmd += ["--" + arg]
elif isinstance(value, (str, int, float)):
cmd += ["--" + arg, str(value)]
else:
pass
cmd += ["-U0"]
if "disable_odin_xml" in odin_args:
del odin_args["disable_odin_xml"]
cmd += [
"-a",
architecture_file.name,
"-V",
circuit_list,
"-o",
output_netlist.name,
]
else:
cmd += ["-c", odin_config]
command_runner.run_system_command(cmd,
temp_dir=temp_dir,
log_filename=log_filename,
indent_depth=1)
if use_odin_simulation:
sim_dir = temp_dir / "simulation_init"
sim_dir.mkdir()
cmd = [
odin_exec,
"-b",
output_netlist.name,
"-a",
architecture_file.name,
"-sim_dir",
str(sim_dir),
"-g",
"100",
"--best_coverage",
"-U0",
]
command_runner.run_system_command(
cmd,
temp_dir=temp_dir,
log_filename="sim_produce_vector.out",
indent_depth=1,
)
def run(
architecture_file,
circuit_file,
include_files,
output_netlist,
command_runner=vtr.CommandRunner(),
temp_dir=Path("."),
yosys_args="",
log_filename="yosys.out",
yosys_exec=None,
yosys_script=None,
min_hard_mult_size=3,
min_hard_adder_size=1,
):
"""
Runs YOSYS on the specified architecture file and circuit file
.. note :: Usage: vtr.yosys.run(<architecture_file>,<circuit_file>,<output_netlist>,[OPTIONS])
Arguments
=========
architecture_file :
Architecture file to target
circuit_file :
Circuit file to optimize
output_netlist :
File name to output the resulting circuit to
Other Parameters
----------------
command_runner :
A CommandRunner object used to run system commands
temp_dir :
Directory to run in (created if non-existent)
yosys_args:
A dictionary of keyword arguments to pass on to YOSYS
log_filename :
File to log result to
yosys_exec:
YOSYS executable to be run
yosys_script:
The YOSYS script file
"""
temp_dir = Path(temp_dir) if not isinstance(temp_dir, Path) else temp_dir
temp_dir.mkdir(parents=True, exist_ok=True)
if yosys_args is None:
yosys_args = OrderedDict()
# Verify that files are Paths or convert them to Paths and check that they exist
architecture_file = vtr.verify_file(architecture_file, "Architecture")
circuit_file = vtr.verify_file(circuit_file, "Circuit")
output_netlist = vtr.verify_file(output_netlist, "Output netlist", False)
if yosys_exec is None:
yosys_exec = str(vtr.paths.yosys_exe_path)
if yosys_script is None:
yosys_base_script = str(vtr.paths.yosys_script_path)
else:
yosys_base_script = str(Path(yosys_script).resolve())
# Copy the script file
yosys_script = "synthesis.ys"
yosys_script_full_path = str(temp_dir / yosys_script)
shutil.copyfile(yosys_base_script, yosys_script_full_path)
# Copy the yosys models file
yosys_models = YOSYS_LIB_FILES["YSMDL"]
yosys_base_models = str(vtr.paths.yosys_lib_path /
YOSYS_LIB_FILES["YSMDL"])
yosys_models_full_path = str(temp_dir / yosys_models)
shutil.copyfile(yosys_base_models, yosys_models_full_path)
# Copy the VTR memory blocks file
yosys_spram = YOSYS_LIB_FILES["SPRAM"]
yosys_dpram = YOSYS_LIB_FILES["DPRAM"]
yosys_spram_rename = YOSYS_LIB_FILES["SPRAMR"]
yosys_dpram_rename = YOSYS_LIB_FILES["DPRAMR"]
yosys_base_spram = str(vtr.paths.yosys_lib_path / YOSYS_LIB_FILES["SPRAM"])
yosys_base_dpram = str(vtr.paths.yosys_lib_path / YOSYS_LIB_FILES["DPRAM"])
yosys_base_spram_rename = str(vtr.paths.yosys_lib_path /
YOSYS_LIB_FILES["SPRAMR"])
yosys_base_dpram_rename = str(vtr.paths.yosys_lib_path /
YOSYS_LIB_FILES["DPRAMR"])
yosys_spram_full_path = str(temp_dir / yosys_spram)
yosys_dpram_full_path = str(temp_dir / yosys_dpram)
yosys_spram_rename_full_path = str(temp_dir / yosys_spram_rename)
yosys_dpram_rename_full_path = str(temp_dir / yosys_dpram_rename)
shutil.copyfile(yosys_base_spram, yosys_spram_full_path)
shutil.copyfile(yosys_base_dpram, yosys_dpram_full_path)
shutil.copyfile(yosys_base_spram_rename, yosys_spram_rename_full_path)
shutil.copyfile(yosys_base_dpram_rename, yosys_dpram_rename_full_path)
# Create a list showing all (.v) and (.vh) files
circuit_list = create_circuits_list(circuit_file, include_files)
init_script_file(
yosys_script_full_path,
yosys_models_full_path,
yosys_spram_full_path,
yosys_dpram_full_path,
yosys_spram_rename_full_path,
yosys_dpram_rename_full_path,
circuit_list,
output_netlist.name,
vtr.determine_memory_addr_width(str(architecture_file)),
min_hard_mult_size,
min_hard_adder_size,
)
cmd = [yosys_exec]
for arg, value in yosys_args.items():
if isinstance(value, bool) and value:
cmd += ["--" + arg]
elif isinstance(value, (str, int, float)):
cmd += ["--" + arg, str(value)]
else:
pass
cmd += ["-s", yosys_script]
command_runner.run_system_command(cmd,
temp_dir=temp_dir,
log_filename=log_filename,
indent_depth=1)