def parse(self, code, include_paths=None, cache=None, defines=None):
"""
Helper function to parse
"""
self.write_file("file_name.sv", code)
cache = cache if cache is not None else {}
parser = VerilogParser(database=cache)
include_paths = include_paths if include_paths is not None else []
design_file = parser.parse("file_name.sv", include_paths, defines)
return design_file
def parse(self, code, include_paths=None, cache=None, defines=None):
"""
Helper function to parse
"""
self.write_file("file_name.sv", code)
cache = cache if cache is not None else {}
parser = VerilogParser(database=cache)
include_paths = include_paths if include_paths is not None else []
design_file = parser.parse(code, "file_name.sv", include_paths, defines)
return design_file
def _create_project(self):
"""
Create Project instance
"""
database = self._create_database()
self._project = Project(
vhdl_parser=CachedVHDLParser(database=database),
verilog_parser=VerilogParser(database=database),
depend_on_package_body=self._simulator_factory.package_users_depend_on_bodies())
def __init__(self, depend_on_package_body=False, database=None):
"""
depend_on_package_body - Package users depend also on package body
"""
self._database = database
self._vhdl_parser = VHDLParser(database=self._database)
self._verilog_parser = VerilogParser(database=self._database)
self._libraries = OrderedDict()
# Mapping between library lower case name and real library name
self._lower_library_names_dict = {}
self._source_files_in_order = []
self._manual_dependencies = []
self._depend_on_package_body = depend_on_package_body
self._builtin_libraries = set(["ieee", "std"])
def __init__(self,
depend_on_components=False,
depend_on_package_body=False,
vhdl_parser=VHDLParser(),
verilog_parser=VerilogParser()):
"""
depend_on_package_body - Package users depend also on package body
"""
self._vhdl_parser = vhdl_parser
self._verilog_parser = verilog_parser
self._libraries = OrderedDict()
self._source_files_in_order = []
self._manual_dependencies = []
self._depend_on_components = depend_on_components
self._depend_on_package_body = depend_on_package_body
def __init__(self,
depend_on_package_body=False,
vhdl_parser=None,
verilog_parser=None):
"""
depend_on_package_body - Package users depend also on package body
"""
self._vhdl_parser = VHDLParser() if vhdl_parser is None else vhdl_parser
self._verilog_parser = VerilogParser() if verilog_parser is None else verilog_parser
self._libraries = OrderedDict()
# Mapping between library lower case name and real library name
self._lower_libray_names_dict = {}
self._source_files_in_order = []
self._manual_dependencies = []
self._depend_on_package_body = depend_on_package_body