def test_file_type_of(self): self.assertEqual(file_type_of("file.vhd"), "vhdl") self.assertEqual(file_type_of("file.vhdl"), "vhdl") self.assertEqual(file_type_of("file.sv"), "verilog") self.assertEqual(file_type_of("file.v"), "verilog") self.assertEqual(file_type_of("file.vams"), "verilog") self.assertRaises(RuntimeError, file_type_of, "file.foo")
def test_file_type_of(self): self.assertEqual(file_type_of("file.vhd"), "vhdl") self.assertEqual(file_type_of("file.vhdl"), "vhdl") self.assertEqual(file_type_of("file.sv"), "systemverilog") self.assertEqual(file_type_of("file.v"), "verilog") self.assertEqual(file_type_of("file.vams"), "verilog") self.assertRaises(RuntimeError, file_type_of, "file.foo")
def add_source_file(self, file_name, library_name, preprocessors=None, include_dirs=None, defines=None): """ Add source file to library :param file_name: The name of the file :param library_name: The name of the library to add the file into :param include_dirs: A list of include directories :param defines: A dictionary containing Verilog defines to be set :returns: The :class:`.SourceFile` which was added :example: .. code-block:: python prj.add_source_file("file.vhd", "lib") """ file_type = file_type_of(file_name) if file_type == "verilog": include_dirs = include_dirs if include_dirs is not None else [] include_dirs = add_verilog_include_dir(include_dirs) file_name = self._preprocess(library_name, abspath(file_name), preprocessors) return SourceFile(self._project.add_source_file(file_name, library_name, file_type=file_type, include_dirs=include_dirs, defines=defines), self._project, self)
def _find_test_cases(code, file_name): """ Finds all if run("something") strings in file """ is_verilog = file_type_of(file_name) in VERILOG_FILE_TYPES if is_verilog: regexp = _RE_VERILOG_TEST_CASE else: code = remove_comments(code) regexp = _RE_VHDL_TEST_CASE test_cases = [match.group("name") for match in regexp.finditer(code)] unique = set() not_unique = set() for test_case in test_cases: if test_case in unique and test_case not in not_unique: # @TODO line number information could be useful LOGGER.error('Duplicate test case "%s" in %s', test_case, file_name) not_unique.add(test_case) unique.add(test_case) if not_unique: raise RuntimeError('Duplicate test cases') return test_cases
def _parse(self, entity, architecture_name, verilog): """ Parse file for run strings and pragmas """ scope = create_scope(entity.library_name, entity.name) other_file = self._cfg.file_to_scan_for_tests(scope) if other_file is not None: file_name = other_file verilog = file_type_of(other_file) == "verilog" elif verilog: file_name = entity.file_name else: file_name = entity.architecture_names[architecture_name] code = ostools.read_file(file_name) pragmas = self.find_pragmas(code, file_name) # @TODO use presence of runner_cfg as tb_filter instead of tb_* has_runner_cfg = verilog or ("runner_cfg" in entity.generic_names) if has_runner_cfg: run_strings = self.find_run_strings(code, file_name, verilog) else: run_strings = [] return pragmas, run_strings
def add_source_file(self, library_name, file_name, contents): """ Convenient wrapper arround project.add_source_file """ write_file(file_name, contents) source_file = self.project.add_source_file(file_name, library_name, file_type=file_type_of(file_name)) return source_file
def add_source_file(self, library_name, file_name, contents, defines=None): """ Convenient wrapper arround project.add_source_file """ write_file(file_name, contents) source_file = self.project.add_source_file(file_name, library_name, file_type=file_type_of(file_name), defines=defines) return source_file
def add_source_file(self, file_name, library_name, preprocessors=None, include_dirs=None): """ Add source file to library """ file_type = file_type_of(file_name) if file_type == "verilog": include_dirs = include_dirs if include_dirs is not None else [] add_verilog_include_dir(include_dirs) file_name = self._preprocess(library_name, abspath(file_name), preprocessors) self._project.add_source_file(file_name, library_name, file_type=file_type, include_dirs=include_dirs)
def test_add_source_file_has_no_parse_verilog(self): for no_parse in (True, False): project = Project() file_name = "file.v" write_file(file_name, """ module mod; endmodule """) project.add_library("lib", "work_path") source_file = project.add_source_file(file_name, "lib", file_type=file_type_of(file_name), no_parse=no_parse) self.assertEqual(len(source_file.design_units), int(not no_parse))
def test_add_source_file_has_no_parse_vhdl(self): for no_parse in (True, False): project = Project() file_name = "file.vhd" write_file(file_name, """ entity ent is end entity; """) project.add_library("lib", "work_path") source_file = project.add_source_file(file_name, "lib", file_type=file_type_of(file_name), no_parse=no_parse) self.assertEqual(len(source_file.design_units), int(not no_parse))
def _find_tests(code, file_name, line_offsets=None): """ Finds all tests within a file including implicit tests where there is only a test suite returns a list to Test objects """ if line_offsets is None: line_offsets = _get_line_offsets(code) is_verilog = file_type_of(file_name) in VERILOG_FILE_TYPES if is_verilog: code = _remove_verilog_comments(code) regexp = _RE_VERILOG_TEST_CASE suite_regexp = _RE_VERILOG_TEST_SUITE else: code = remove_vhdl_comments(code) regexp = _RE_VHDL_TEST_CASE suite_regexp = _RE_VHDL_TEST_SUITE tests = [ Test(name=match.group("name"), location=FileLocation.from_match(file_name, match, "name", line_offsets)) for match in regexp.finditer(code) ] _check_duplicate_tests(tests) if not tests: # Implicit test, use the test suite start as lineno match = suite_regexp.search(code) if match: location = FileLocation.from_match(file_name, match, 0, line_offsets) else: LOGGER.warning("Found no tests or test suite within %s", file_name) location = FileLocation.from_line_offsets(file_name, 0, 0, line_offsets) tests = [Test(None, location=location)] return tests
def _find_tests(code, file_name, line_offsets=None): """ Finds all tests within a file including implicit tests where there is only a test suite returns a list to Test objects """ if line_offsets is None: line_offsets = _get_line_offsets(code) is_verilog = file_type_of(file_name) in VERILOG_FILE_TYPES if is_verilog: code = _remove_verilog_comments(code) regexp = _RE_VERILOG_TEST_CASE suite_regexp = _RE_VERILOG_TEST_SUITE else: code = remove_vhdl_comments(code) regexp = _RE_VHDL_TEST_CASE suite_regexp = _RE_VHDL_TEST_SUITE tests = [Test(name=match.group("name"), location=FileLocation.from_match(file_name, match, "name", line_offsets)) for match in regexp.finditer(code)] _check_duplicate_tests(tests) if not tests: # Implicit test, use the test suite start as lineno match = suite_regexp.search(code) if match: location = FileLocation.from_match(file_name, match, 0, line_offsets) else: LOGGER.warning("Found no tests or test suite within %s", file_name) location = FileLocation.from_line_offsets(file_name, 0, 0, line_offsets) tests = [Test(None, location=location)] return tests