def test_runtime_error_on_missing_gtkwave(self, find_executable): executables = {} def find_executable_side_effect(name): return executables[name] find_executable.side_effect = find_executable_side_effect executables["gtkwave"] = ["path"] GHDLInterface(prefix="prefix", output_path="") executables["gtkwave"] = [] GHDLInterface(prefix="prefix", output_path="") self.assertRaises(RuntimeError, GHDLInterface, prefix="prefix", output_path="", gui=True)
def test_elaborate_e_project(self): design_unit = Entity("tb_entity", file_name=str(Path("tempdir") / "file.vhd")) design_unit.original_file_name = str(Path("tempdir") / "other_path" / "original_file.vhd") design_unit.generic_names = ["runner_cfg", "tb_path"] config = Configuration("name", design_unit, sim_options={"ghdl.elab_e": True}) simif = GHDLInterface(prefix="prefix", output_path="") simif._vhdl_standard = VHDL.standard("2008") # pylint: disable=protected-access simif._project = Project() # pylint: disable=protected-access simif._project.add_library("lib", "lib_path") # pylint: disable=protected-access self.assertEqual( simif._get_command( # pylint: disable=protected-access config, str(Path("output_path") / "ghdl"), True, True, None ), [ str(Path("prefix") / "ghdl"), "-e", "--std=08", "--work=lib", "--workdir=lib_path", "-Plib_path", "-o", str(Path("output_path") / "ghdl" / "tb_entity-arch"), "tb_entity", "arch", ], )
def test_compile_project_extra_flags(self, check_output): simif = GHDLInterface(prefix="prefix", output_path="") write_file("file.vhd", "") project = Project() project.add_library("lib", "lib_path") source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl") source_file.set_compile_option("ghdl.flags", ["custom", "flags"]) simif.compile_project(project) check_output.assert_called_once_with( [ str(Path("prefix") / "ghdl"), "-a", "--workdir=lib_path", "--work=lib", "--std=08", "-Plib_path", "custom", "flags", "file.vhd", ], env=simif.get_env(), )
def test_compile_project_verilog_error(self): simif = GHDLInterface(prefix="prefix", output_path="") write_file("file.v", "") project = Project() project.add_library("lib", "lib_path") project.add_source_file("file.v", "lib", file_type="verilog") self.assertRaises(CompileError, simif.compile_project, project)
def test_compile_project_93(self, check_output): simif = GHDLInterface(prefix="prefix", output_path="") write_file("file.vhd", "") project = Project() project.add_library("lib", "lib_path") project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard=VHDL.standard("93")) simif.compile_project(project) check_output.assert_called_once_with( [ str(Path("prefix") / "ghdl"), "-a", "--workdir=lib_path", "--work=lib", "--std=93", "-Plib_path", "file.vhd", ], env=simif.get_env(), )