def test_compile_source_files_continue_on_error(self): simif = create_simulator_interface() project = Project() project.add_library("lib", "lib_path") write_file("file1.vhd", "") file1 = project.add_source_file("file1.vhd", "lib", file_type="vhdl") write_file("file2.vhd", "") file2 = project.add_source_file("file2.vhd", "lib", file_type="vhdl") write_file("file3.vhd", "") file3 = project.add_source_file("file3.vhd", "lib", file_type="vhdl") project.add_manual_dependency(file2, depends_on=file1) def compile_source_file_command(source_file): if source_file == file1: return ["command1"] elif source_file == file2: return ["command2"] elif source_file == file3: return ["command3"] def check_output_side_effect(command, **kwargs): # pylint: disable=missing-docstring if command == ["command1"]: raise subprocess.CalledProcessError(returncode=-1, cmd=command, output="bad stuff") return "" simif.compile_source_file_command.side_effect = compile_source_file_command with mock.patch("vunit.simulator_interface.check_output", autospec=True) as check_output: check_output.side_effect = check_output_side_effect printer = MockPrinter() self.assertRaises(CompileError, simif.compile_source_files, project, printer=printer, continue_on_error=True) self.assertEqual( printer.output, """\ Compiling into lib: file3.vhd passed Compiling into lib: file1.vhd failed === Command used: === command1 === Command output: === bad stuff Compiling into lib: file2.vhd skipped Compile failed """) self.assertEqual(len(check_output.mock_calls), 2) check_output.assert_has_calls([ mock.call(["command1"], env=simif.get_env()), mock.call(["command3"], env=simif.get_env()) ], any_order=True) self.assertEqual(project.get_files_in_compile_order(incremental=True), [file1, file2])
def test_simulate_fail(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None simif = IncisiveInterface(prefix="prefix", output_path=self.output_path) config = make_config() self.assertFalse( simif.simulate("suite_output_path", "test_suite_name", config)) elaborate_args_file = join("suite_output_path", simif.name, "irun_elaborate.args") simulate_args_file = join("suite_output_path", simif.name, "irun_simulate.args") run_command.assert_has_calls([ mock.call( [join("prefix", "irun"), "-f", basename(elaborate_args_file)], cwd=dirname(elaborate_args_file), env=simif.get_env(), ), mock.call( [join("prefix", "irun"), "-f", basename(simulate_args_file)], cwd=dirname(simulate_args_file), env=simif.get_env(), ), ])
def test_compile_source_files(self): simif = create_simulator_interface() simif.compile_source_file_command.side_effect = iter([["command1"], ["command2"]]) project = Project() project.add_library("lib", "lib_path") write_file("file1.vhd", "") file1 = project.add_source_file("file1.vhd", "lib", file_type="vhdl") write_file("file2.vhd", "") file2 = project.add_source_file("file2.vhd", "lib", file_type="vhdl") project.add_manual_dependency(file2, depends_on=file1) with mock.patch("vunit.simulator_interface.check_output", autospec=True) as check_output: check_output.side_effect = iter(["", ""]) printer = MockPrinter() simif.compile_source_files(project, printer=printer) check_output.assert_has_calls([ mock.call(["command1"], env=simif.get_env()), mock.call(["command2"], env=simif.get_env()), ]) self.assertEqual( printer.output, """\ Compiling into lib: file1.vhd passed Compiling into lib: file2.vhd passed Compile passed """, ) self.assertEqual(project.get_files_in_compile_order(incremental=True), [])
def test_simulate_extra_flags(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None simif = IncisiveInterface(prefix="prefix", output_path=self.output_path) config = make_config( sim_options={"incisive.irun_sim_flags": ["custom", "flags"]}) self.assertTrue( simif.simulate("sim_output_path", "test_suite_name", config)) elaborate_args_file = join('sim_output_path', 'irun_elaborate.args') simulate_args_file = join('sim_output_path', 'irun_simulate.args') run_command.assert_has_calls([ mock.call( [join('prefix', 'irun'), '-f', basename(elaborate_args_file)], cwd=dirname(elaborate_args_file), env=simif.get_env()), mock.call( [join('prefix', 'irun'), '-f', basename(simulate_args_file)], cwd=dirname(simulate_args_file), env=simif.get_env()), ]) args = read_file(elaborate_args_file).splitlines() self.assertIn("custom", args) self.assertIn("flags", args) args = read_file(simulate_args_file).splitlines() self.assertIn("custom", args) self.assertIn("flags", args)
def test_simulate_generics_and_parameters(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None simif = IncisiveInterface(prefix="prefix", output_path=self.output_path) config = make_config(verilog=True, generics={"genstr": "genval", "genint": 1, "genbool": True}) self.assertTrue(simif.simulate("suite_output_path", "test_suite_name", config)) elaborate_args_file = join('suite_output_path', simif.name, 'irun_elaborate.args') simulate_args_file = join('suite_output_path', simif.name, 'irun_simulate.args') run_command.assert_has_calls([ mock.call([join('prefix', 'irun'), '-f', basename(elaborate_args_file)], cwd=dirname(elaborate_args_file), env=simif.get_env()), mock.call([join('prefix', 'irun'), '-f', basename(simulate_args_file)], cwd=dirname(simulate_args_file), env=simif.get_env()), ]) for args_file in [elaborate_args_file, simulate_args_file]: args = read_file(args_file).splitlines() self.assertIn('-gpg "modulename.genstr => \\"genval\\""', args) self.assertIn('-gpg "modulename.genint => 1"', args) self.assertIn('-gpg "modulename.genbool => \\"True\\""', args)
def test_simulate_generics_and_parameters(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None simif = IncisiveInterface(prefix="prefix", output_path=self.output_path) config = make_config(verilog=True, generics={ "genstr": "genval", "genint": 1, "genbool": True }) self.assertTrue( simif.simulate("sim_output_path", "test_suite_name", config)) elaborate_args_file = join('sim_output_path', 'irun_elaborate.args') simulate_args_file = join('sim_output_path', 'irun_simulate.args') run_command.assert_has_calls([ mock.call( [join('prefix', 'irun'), '-f', basename(elaborate_args_file)], cwd=dirname(elaborate_args_file), env=simif.get_env()), mock.call( [join('prefix', 'irun'), '-f', basename(simulate_args_file)], cwd=dirname(simulate_args_file), env=simif.get_env()), ]) for args_file in [elaborate_args_file, simulate_args_file]: args = read_file(args_file).splitlines() self.assertIn('-gpg "modulename.genstr => \\"genval\\""', args) self.assertIn('-gpg "modulename.genint => 1"', args) self.assertIn('-gpg "modulename.genbool => \\"True\\""', args)
def test_simulate_extra_flags(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None simif = IncisiveInterface(prefix="prefix", output_path=self.output_path) config = SimConfig(options={"incisive.irun_sim_flags": ["custom", "flags"]}) self.assertTrue(simif.simulate("sim_output_path", "lib", "modulename", None, config)) elaborate_args_file = join("sim_output_path", "irun_elaborate.args") simulate_args_file = join("sim_output_path", "irun_simulate.args") run_command.assert_has_calls( [ mock.call( [join("prefix", "irun"), "-f", basename(elaborate_args_file)], cwd=dirname(elaborate_args_file) ), mock.call( [join("prefix", "irun"), "-f", basename(simulate_args_file)], cwd=dirname(simulate_args_file) ), ] ) args = read_file(elaborate_args_file).splitlines() self.assertIn("custom", args) self.assertIn("flags", args) args = read_file(simulate_args_file).splitlines() self.assertIn("custom", args) self.assertIn("flags", args)
def test_simulate_hdlvar(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, hdlvar="custom_hdlvar") config = make_config() self.assertTrue( simif.simulate("sim_output_path", "test_suite_name", config)) elaborate_args_file = join('sim_output_path', 'irun_elaborate.args') simulate_args_file = join('sim_output_path', 'irun_simulate.args') run_command.assert_has_calls([ mock.call( [join('prefix', 'irun'), '-f', basename(elaborate_args_file)], cwd=dirname(elaborate_args_file), env=simif.get_env()), mock.call( [join('prefix', 'irun'), '-f', basename(simulate_args_file)], cwd=dirname(simulate_args_file), env=simif.get_env()), ]) for args_file in [elaborate_args_file, simulate_args_file]: args = read_file(args_file).splitlines() self.assertIn('-hdlvar "custom_hdlvar"', args)
def test_simulate_gui(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None project = Project() project.add_library("lib", "lib_path") write_file("file.vhd", "") project.add_source_file("file.vhd", "lib", file_type="vhdl") simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, gui=True) with mock.patch("vunit.simulator_interface.check_output", autospec=True, return_value="") as dummy: simif.compile_project(project) config = make_config() self.assertTrue( simif.simulate("sim_output_path", "test_suite_name", config)) elaborate_args_file = join('sim_output_path', 'irun_elaborate.args') simulate_args_file = join('sim_output_path', 'irun_simulate.args') run_command.assert_has_calls([ mock.call( [join('prefix', 'irun'), '-f', basename(elaborate_args_file)], cwd=dirname(elaborate_args_file), env=simif.get_env()), mock.call( [join('prefix', 'irun'), '-f', basename(simulate_args_file)], cwd=dirname(simulate_args_file), env=simif.get_env()), ]) self.assertEqual( read_file(elaborate_args_file).splitlines(), [ '-elaborate', '-nocopyright', '-licqueue', '-errormax 10', '-nowarn WRMNZD', '-nowarn DLCPTH', '-nowarn DLCVAR', '-ncerror EVBBOL', '-ncerror EVBSTR', '-ncerror EVBNAT', '-work work', '-nclibdirname "%s"' % join(self.output_path, "libraries"), '-cdslib "%s"' % join(self.output_path, "cds.lib"), '-log "sim_output_path/irun_elaborate.log"', '-quiet', '-reflib "lib_path"', '-access +rwc', '-gui', '-top lib.ent:arch' ]) self.assertEqual( read_file(simulate_args_file).splitlines(), [ '-nocopyright', '-licqueue', '-errormax 10', '-nowarn WRMNZD', '-nowarn DLCPTH', '-nowarn DLCVAR', '-ncerror EVBBOL', '-ncerror EVBSTR', '-ncerror EVBNAT', '-work work', '-nclibdirname "%s"' % join(self.output_path, "libraries"), '-cdslib "%s"' % join(self.output_path, "cds.lib"), '-log "sim_output_path/irun_simulate.log"', '-quiet', '-reflib "lib_path"', '-access +rwc', '-gui', '-top lib.ent:arch' ])
def test_compile_source_files_continue_on_error(self): simif = create_simulator_interface() project = Project() project.add_library("lib", "lib_path") write_file("file1.vhd", "") file1 = project.add_source_file("file1.vhd", "lib", file_type="vhdl") write_file("file2.vhd", "") file2 = project.add_source_file("file2.vhd", "lib", file_type="vhdl") write_file("file3.vhd", "") file3 = project.add_source_file("file3.vhd", "lib", file_type="vhdl") project.add_manual_dependency(file2, depends_on=file1) def compile_source_file_command(source_file): """ Dummy compile command """ if source_file == file1: return ["command1"] if source_file == file2: return ["command2"] if source_file == file3: return ["command3"] raise AssertionError def check_output_side_effect(command, env=None): # pylint: disable=missing-docstring, unused-argument if command == ["command1"]: raise subprocess.CalledProcessError(returncode=-1, cmd=command, output="bad stuff") return "" simif.compile_source_file_command.side_effect = compile_source_file_command with mock.patch("vunit.simulator_interface.check_output", autospec=True) as check_output: check_output.side_effect = check_output_side_effect printer = MockPrinter() self.assertRaises(CompileError, simif.compile_source_files, project, printer=printer, continue_on_error=True) self.assertEqual(printer.output, """\ Compiling into lib: file3.vhd passed Compiling into lib: file1.vhd failed === Command used: === command1 === Command output: === bad stuff Compiling into lib: file2.vhd skipped Compile failed """) self.assertEqual(len(check_output.mock_calls), 2) check_output.assert_has_calls([mock.call(["command1"], env=simif.get_env()), mock.call(["command3"], env=simif.get_env())], any_order=True) self.assertEqual(project.get_files_in_compile_order(incremental=True), [file1, file2])
def test_simulate_fail(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None simif = IncisiveInterface(prefix="prefix", output_path=self.output_path) config = SimConfig() self.assertFalse(simif.simulate("sim_output_path", "lib", "modulename", None, config)) elaborate_args_file = join('sim_output_path', 'irun_elaborate.args') simulate_args_file = join('sim_output_path', 'irun_simulate.args') run_command.assert_has_calls([ mock.call([join('prefix', 'irun'), '-f', basename(elaborate_args_file)], cwd=dirname(elaborate_args_file)), mock.call([join('prefix', 'irun'), '-f', basename(simulate_args_file)], cwd=dirname(simulate_args_file)), ])
def test_elaborate(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None simif = IncisiveInterface(prefix="prefix", output_path=self.output_path) config = make_config(verilog=True) self.assertTrue( simif.simulate("sim_output_path", "test_suite_name", config, elaborate_only=True)) elaborate_args_file = join('sim_output_path', 'irun_elaborate.args') run_command.assert_has_calls([ mock.call( [join('prefix', 'irun'), '-f', basename(elaborate_args_file)], cwd=dirname(elaborate_args_file), env=simif.get_env()), ]) self.assertEqual( read_file(elaborate_args_file).splitlines(), [ '-elaborate', '-nocopyright', '-licqueue', '-errormax 10', '-nowarn WRMNZD', '-nowarn DLCPTH', '-nowarn DLCVAR', '-ncerror EVBBOL', '-ncerror EVBSTR', '-ncerror EVBNAT', '-work work', '-nclibdirname "%s"' % join(self.output_path, "libraries"), '-cdslib "%s"' % join(self.output_path, "cds.lib"), '-log "sim_output_path/irun_elaborate.log"', '-quiet', '-access +r', '-input "@run"', '-input "@catch {if {#vunit_pkg::__runner__.exit_without_errors == 1} {exit 0} else {exit 42}}"', '-input "@catch {if {#run_pkg.runner.exit_without_errors == \\"TRUE\\"} {exit 0} else {exit 42}}"', '-top lib.modulename:sv' ])
def test_simulate_fail(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None simif = IncisiveInterface(prefix="prefix", output_path=self.output_path) config = make_config() self.assertFalse(simif.simulate("suite_output_path", "test_suite_name", config)) elaborate_args_file = join('suite_output_path', simif.name, 'irun_elaborate.args') simulate_args_file = join('suite_output_path', simif.name, 'irun_simulate.args') run_command.assert_has_calls([ mock.call([join('prefix', 'irun'), '-f', basename(elaborate_args_file)], cwd=dirname(elaborate_args_file), env=simif.get_env()), mock.call([join('prefix', 'irun'), '-f', basename(simulate_args_file)], cwd=dirname(simulate_args_file), env=simif.get_env()), ])
def test_elaborate(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None simif = IncisiveInterface(prefix="prefix", output_path=self.output_path) config = make_config(verilog=True) self.assertTrue(simif.simulate("suite_output_path", "test_suite_name", config, elaborate_only=True)) elaborate_args_file = join('suite_output_path', simif.name, 'irun_elaborate.args') run_command.assert_has_calls([ mock.call([join('prefix', 'irun'), '-f', basename(elaborate_args_file)], cwd=dirname(elaborate_args_file), env=simif.get_env()), ]) self.assertEqual( read_file(elaborate_args_file).splitlines(), ['-elaborate', '-nocopyright', '-licqueue', '-errormax 10', '-nowarn WRMNZD', '-nowarn DLCPTH', '-nowarn DLCVAR', '-ncerror EVBBOL', '-ncerror EVBSTR', '-ncerror EVBNAT', '-work work', '-nclibdirname "%s"' % join(self.output_path, "libraries"), '-cdslib "%s"' % join(self.output_path, "cds.lib"), '-log "%s"' % join("suite_output_path", simif.name, "irun_elaborate.log"), '-quiet', '-access +r', '-input "@run"', '-top lib.modulename:sv'])
def test_compile_source_files(self): simif = create_simulator_interface() simif.compile_source_file_command.side_effect = iter([["command1"], ["command2"]]) project = Project() project.add_library("lib", "lib_path") write_file("file1.vhd", "") file1 = project.add_source_file("file1.vhd", "lib", file_type="vhdl") write_file("file2.vhd", "") file2 = project.add_source_file("file2.vhd", "lib", file_type="vhdl") project.add_manual_dependency(file2, depends_on=file1) with mock.patch("vunit.simulator_interface.run_command", autospec=True) as run_command: run_command.side_effect = iter([True, True]) simif.compile_source_files(project) run_command.assert_has_calls([mock.call(["command1"]), mock.call(["command2"])]) self.assertEqual(project.get_files_in_compile_order(incremental=True), [])
def test_simulate_fail(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None simif = IncisiveInterface(prefix="prefix", output_path=self.output_path) config = SimConfig() self.assertFalse(simif.simulate("sim_output_path", "lib", "modulename", None, config)) elaborate_args_file = join("sim_output_path", "irun_elaborate.args") simulate_args_file = join("sim_output_path", "irun_simulate.args") run_command.assert_has_calls( [ mock.call( [join("prefix", "irun"), "-f", basename(elaborate_args_file)], cwd=dirname(elaborate_args_file) ), mock.call( [join("prefix", "irun"), "-f", basename(simulate_args_file)], cwd=dirname(simulate_args_file) ), ] )
def test_compile_source_files_continue_on_error(self): simif = create_simulator_interface() project = Project() project.add_library("lib", "lib_path") write_file("file1.vhd", "") file1 = project.add_source_file("file1.vhd", "lib", file_type="vhdl") write_file("file2.vhd", "") file2 = project.add_source_file("file2.vhd", "lib", file_type="vhdl") write_file("file3.vhd", "") file3 = project.add_source_file("file3.vhd", "lib", file_type="vhdl") project.add_manual_dependency(file2, depends_on=file1) def compile_source_file_command(source_file): if source_file == file1: return ["command1"] elif source_file == file2: return ["command2"] elif source_file == file3: return ["command3"] def run_command_side_effect(command, **kwargs): if command == ["command1"]: return False else: return True simif.compile_source_file_command.side_effect = compile_source_file_command with mock.patch("vunit.simulator_interface.run_command", autospec=True) as run_command: run_command.side_effect = run_command_side_effect self.assertRaises(CompileError, simif.compile_source_files, project, continue_on_error=True) self.assertEqual(len(run_command.mock_calls), 2) run_command.assert_has_calls([ mock.call(["command1"], env=simif.get_env()), mock.call(["command3"], env=simif.get_env()) ], any_order=True) self.assertEqual(project.get_files_in_compile_order(incremental=True), [file1, file2])
def test_simulate_hdlvar(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, hdlvar="custom_hdlvar") config = make_config() self.assertTrue(simif.simulate("suite_output_path", "test_suite_name", config)) elaborate_args_file = join('suite_output_path', simif.name, 'irun_elaborate.args') simulate_args_file = join('suite_output_path', simif.name, 'irun_simulate.args') run_command.assert_has_calls([ mock.call([join('prefix', 'irun'), '-f', basename(elaborate_args_file)], cwd=dirname(elaborate_args_file), env=simif.get_env()), mock.call([join('prefix', 'irun'), '-f', basename(simulate_args_file)], cwd=dirname(simulate_args_file), env=simif.get_env()), ]) for args_file in [elaborate_args_file, simulate_args_file]: args = read_file(args_file).splitlines() self.assertIn('-hdlvar "custom_hdlvar"', args)
def test_tb_filter_warning_on_runner_cfg_but_not_matching_tb_pattern(self): design_unit = Entity('entity_ok_but_warning') design_unit.generic_names = ["runner_cfg"] with mock.patch("vunit.test_bench_list.LOGGER", autospec=True) as logger: self.assertTrue(tb_filter(design_unit)) logger.warning.assert_has_calls([ mock.call( '%s %s has runner_cfg %s but the file name and the %s name does not match regex %s\n' 'in file %s', 'Entity', 'entity_ok_but_warning', 'generic', 'entity', '^(tb_.*)|(.*_tb)$', design_unit.file_name) ])
def test_simulate_hdlvar(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, hdlvar="custom_hdlvar") config = SimConfig() self.assertTrue(simif.simulate("sim_output_path", "lib", "modulename", None, config)) elaborate_args_file = join("sim_output_path", "irun_elaborate.args") simulate_args_file = join("sim_output_path", "irun_simulate.args") run_command.assert_has_calls( [ mock.call( [join("prefix", "irun"), "-f", basename(elaborate_args_file)], cwd=dirname(elaborate_args_file) ), mock.call( [join("prefix", "irun"), "-f", basename(simulate_args_file)], cwd=dirname(simulate_args_file) ), ] ) for args_file in [elaborate_args_file, simulate_args_file]: args = read_file(args_file).splitlines() self.assertIn('-hdlvar "custom_hdlvar"', args)
def test_compile_source_files(self): simif = create_simulator_interface() simif.compile_source_file_command.side_effect = iter([["command1"], ["command2"]]) project = Project() project.add_library("lib", "lib_path") write_file("file1.vhd", "") file1 = project.add_source_file("file1.vhd", "lib", file_type="vhdl") write_file("file2.vhd", "") file2 = project.add_source_file("file2.vhd", "lib", file_type="vhdl") project.add_manual_dependency(file2, depends_on=file1) with mock.patch("vunit.simulator_interface.check_output", autospec=True) as check_output: check_output.side_effect = iter(["", ""]) printer = MockPrinter() simif.compile_source_files(project, printer=printer) check_output.assert_has_calls([mock.call(["command1"], env=simif.get_env()), mock.call(["command2"], env=simif.get_env())]) self.assertEqual(printer.output, """\ Compiling into lib: file1.vhd passed Compiling into lib: file2.vhd passed Compile passed """) self.assertEqual(project.get_files_in_compile_order(incremental=True), [])
def test_simulate_extra_flags(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None simif = IncisiveInterface(prefix="prefix", output_path=self.output_path) config = make_config(sim_options={"incisive.irun_sim_flags": ["custom", "flags"]}) self.assertTrue(simif.simulate("suite_output_path", "test_suite_name", config)) elaborate_args_file = join('suite_output_path', simif.name, 'irun_elaborate.args') simulate_args_file = join('suite_output_path', simif.name, 'irun_simulate.args') run_command.assert_has_calls([ mock.call([join('prefix', 'irun'), '-f', basename(elaborate_args_file)], cwd=dirname(elaborate_args_file), env=simif.get_env()), mock.call([join('prefix', 'irun'), '-f', basename(simulate_args_file)], cwd=dirname(simulate_args_file), env=simif.get_env()), ]) args = read_file(elaborate_args_file).splitlines() self.assertIn("custom", args) self.assertIn("flags", args) args = read_file(simulate_args_file).splitlines() self.assertIn("custom", args) self.assertIn("flags", args)
def test_add_single_file_manual_dependencies(self, add_manual_dependency): # pylint: disable=protected-access ui = self._create_ui() lib = ui.add_library("lib") file_name1 = self.create_entity_file(1) file_name2 = self.create_entity_file(2) file1 = lib.add_source_file(file_name1) file2 = lib.add_source_file(file_name2) add_manual_dependency.assert_has_calls([]) file1.depends_on(file2) add_manual_dependency.assert_has_calls([ mock.call(ui._project, file1._source_file, depends_on=file2._source_file)])
def test_tb_filter_warning_on_missing_runner_cfg_when_matching_tb_pattern( self): design_unit = Module('tb_module_not_ok') design_unit.generic_names = [] with mock.patch("vunit.test_bench_list.LOGGER", autospec=True) as logger: self.assertFalse(tb_filter(design_unit)) logger.warning.assert_has_calls([ mock.call( '%s %s matches testbench name regex %s ' 'but has no %s runner_cfg and will therefore not be run.\n' 'in file %s', 'Module', 'tb_module_not_ok', '^(tb_.*)|(.*_tb)$', 'parameter', design_unit.file_name) ])
def test_simulate_generics_and_parameters(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None simif = IncisiveInterface(prefix="prefix", output_path=self.output_path) config = SimConfig(generics={"genstr": "genval", "genint": 1, "genbool": True}) self.assertTrue(simif.simulate("sim_output_path", "lib", "modulename", None, config)) elaborate_args_file = join("sim_output_path", "irun_elaborate.args") simulate_args_file = join("sim_output_path", "irun_simulate.args") run_command.assert_has_calls( [ mock.call( [join("prefix", "irun"), "-f", basename(elaborate_args_file)], cwd=dirname(elaborate_args_file) ), mock.call( [join("prefix", "irun"), "-f", basename(simulate_args_file)], cwd=dirname(simulate_args_file) ), ] ) for args_file in [elaborate_args_file, simulate_args_file]: args = read_file(args_file).splitlines() self.assertIn('-gpg "modulename.genstr => \\"genval\\""', args) self.assertIn('-gpg "modulename.genint => 1"', args) self.assertIn('-gpg "modulename.genbool => \\"True\\""', args)
def test_compile_source_files_continue_on_error(self): simif = create_simulator_interface() project = Project() project.add_library("lib", "lib_path") write_file("file1.vhd", "") file1 = project.add_source_file("file1.vhd", "lib", file_type="vhdl") write_file("file2.vhd", "") file2 = project.add_source_file("file2.vhd", "lib", file_type="vhdl") write_file("file3.vhd", "") file3 = project.add_source_file("file3.vhd", "lib", file_type="vhdl") project.add_manual_dependency(file2, depends_on=file1) def compile_source_file_command(source_file): if source_file == file1: return ["command1"] elif source_file == file2: return ["command2"] elif source_file == file3: return ["command3"] def run_command_side_effect(command): if command == ["command1"]: return False else: return True simif.compile_source_file_command.side_effect = compile_source_file_command with mock.patch("vunit.simulator_interface.run_command", autospec=True) as run_command: run_command.side_effect = run_command_side_effect self.assertRaises(CompileError, simif.compile_source_files, project, continue_on_error=True) self.assertEqual(len(run_command.mock_calls), 2) run_command.assert_has_calls([mock.call(["command1"]), mock.call(["command3"])], any_order=True) self.assertEqual(project.get_files_in_compile_order(incremental=True), [file1, file2])
def test_add_single_file_manual_dependencies(self, add_manual_dependency): # pylint: disable=protected-access ui = self._create_ui() lib = ui.add_library("lib") file_name1 = self.create_entity_file(1) file_name2 = self.create_entity_file(2) file1 = lib.add_source_file(file_name1) file2 = lib.add_source_file(file_name2) add_manual_dependency.assert_has_calls([]) file1.depends_on(file2) add_manual_dependency.assert_has_calls([ mock.call(ui._project, file1._source_file, depends_on=file2._source_file) ])
def test_tb_filter_warning_on_missing_runner_cfg_when_matching_tb_pattern(self, tempdir): design_unit = Module('tb_module_not_ok', file_name=join(tempdir, "file.vhd")) design_unit.generic_names = [] with mock.patch("vunit.test_bench_list.LOGGER", autospec=True) as logger: self.assertFalse(tb_filter(design_unit)) logger.warning.assert_has_calls([ mock.call('%s %s matches testbench name regex %s ' 'but has no %s runner_cfg and will therefore not be run.\n' 'in file %s', 'Module', 'tb_module_not_ok', '^(tb_.*)|(.*_tb)$', 'parameter', design_unit.file_name)])
def test_tb_filter_warning_on_runner_cfg_but_not_matching_tb_pattern(self, tempdir): design_unit = Entity('entity_ok_but_warning', file_name=join(tempdir, "file.vhd")) design_unit.generic_names = ["runner_cfg"] with mock.patch("vunit.test_bench_list.LOGGER", autospec=True) as logger: self.assertTrue(tb_filter(design_unit)) logger.warning.assert_has_calls([ mock.call('%s %s has runner_cfg %s but the file name and the %s name does not match regex %s\n' 'in file %s', 'Entity', 'entity_ok_but_warning', 'generic', 'entity', '^(tb_.*)|(.*_tb)$', design_unit.file_name)])
def test_elaborate(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None simif = IncisiveInterface(prefix="prefix", output_path=self.output_path) config = make_config(verilog=True) self.assertTrue( simif.simulate("suite_output_path", "test_suite_name", config, elaborate_only=True)) elaborate_args_file = join("suite_output_path", simif.name, "irun_elaborate.args") run_command.assert_has_calls([ mock.call( [join("prefix", "irun"), "-f", basename(elaborate_args_file)], cwd=dirname(elaborate_args_file), env=simif.get_env(), ) ]) self.assertEqual( read_file(elaborate_args_file).splitlines(), [ "-elaborate", "-nocopyright", "-licqueue", "-errormax 10", "-nowarn WRMNZD", "-nowarn DLCPTH", "-nowarn DLCVAR", "-ncerror EVBBOL", "-ncerror EVBSTR", "-ncerror EVBNAT", "-work work", '-nclibdirname "%s"' % join(self.output_path, "libraries"), '-cdslib "%s"' % join(self.output_path, "cds.lib"), '-log "%s"' % join("suite_output_path", simif.name, "irun_elaborate.log"), "-quiet", "-access +r", '-input "@run"', "-top lib.modulename:sv", ], )
def test_warning_on_missing_runner_cfg_when_matching_tb_pattern(self): project = ProjectStub() lib = project.add_library("lib") module = lib.add_module("tb_module_not_ok") with mock.patch("vunit.test_scanner.LOGGER", autospec=True) as logger: tests = self.test_scanner.from_project(project, entity_filter=tb_filter) logger.warning.assert_has_calls([ mock.call('%s %s matches testbench name regex %s ' 'but has no %s runner_cfg and will therefore not be run.\n' 'in file %s', 'Module', 'tb_module_not_ok', '(tb_.*)|(.*_tb)', 'parameter', module.file_name)]) self.assert_has_tests(tests, [])
def test_warning_on_runner_cfg_but_not_matching_tb_pattern(self): project = ProjectStub() lib = project.add_library("lib") entity = lib.add_entity("entity_ok_but_warning", generic_names=["runner_cfg"]) with mock.patch("vunit.test_scanner.LOGGER", autospec=True) as logger: tests = self.test_scanner.from_project(project, entity_filter=tb_filter) logger.warning.assert_has_calls([ mock.call('%s %s has runner_cfg %s but the file name and the %s name does not match regex %s\n' 'in file %s', 'Entity', 'entity_ok_but_warning', 'generic', 'entity', '(tb_.*)|(.*_tb)', entity.file_name)]) self.assert_has_tests(tests, ["lib.entity_ok_but_warning.all"])
def test_add_fileset_manual_dependencies(self, add_manual_dependency): # pylint: disable=protected-access ui = self._create_ui() lib = ui.add_library("lib") self.create_file("foo1.vhd") self.create_file("foo2.vhd") self.create_file("foo3.vhd") self.create_file("bar.vhd") foo_files = lib.add_source_files("foo*.vhd") bar_file = lib.add_source_file("bar.vhd") add_manual_dependency.assert_has_calls([]) foo_files.depends_on(bar_file) add_manual_dependency.assert_has_calls([ mock.call(ui._project, foo_file._source_file, depends_on=bar_file._source_file) for foo_file in foo_files])
def test_add_fileset_manual_dependencies(self, add_manual_dependency): # pylint: disable=protected-access ui = self._create_ui() lib = ui.add_library("lib") self.create_file("foo1.vhd") self.create_file("foo2.vhd") self.create_file("foo3.vhd") self.create_file("bar.vhd") foo_files = lib.add_source_files("foo*.vhd") bar_file = lib.add_source_file("bar.vhd") add_manual_dependency.assert_has_calls([]) foo_files.depends_on(bar_file) add_manual_dependency.assert_has_calls([ mock.call(ui._project, foo_file._source_file, depends_on=bar_file._source_file) for foo_file in foo_files ])
def test_tb_filter_warning_on_missing_runner_cfg_when_matching_tb_pattern( self, tempdir ): design_unit = Module("tb_module_not_ok", file_name=join(tempdir, "file.vhd")) design_unit.generic_names = [] with mock.patch("vunit.test_bench_list.LOGGER", autospec=True) as logger: self.assertFalse(tb_filter(design_unit)) logger.warning.assert_has_calls( [ mock.call( "%s %s matches testbench name regex %s " "but has no %s runner_cfg and will therefore not be run.\n" "in file %s", "Module", "tb_module_not_ok", "^(tb_.*)|(.*_tb)$", "parameter", design_unit.file_name, ) ] )
def test_tb_filter_warning_on_runner_cfg_but_not_matching_tb_pattern(self, tempdir): design_unit = Entity( "entity_ok_but_warning", file_name=join(tempdir, "file.vhd") ) design_unit.generic_names = ["runner_cfg"] with mock.patch("vunit.test_bench_list.LOGGER", autospec=True) as logger: self.assertTrue(tb_filter(design_unit)) logger.warning.assert_has_calls( [ mock.call( "%s %s has runner_cfg %s but the file name and the %s name does not match regex %s\n" "in file %s", "Entity", "entity_ok_but_warning", "generic", "entity", "^(tb_.*)|(.*_tb)$", design_unit.file_name, ) ] )
def test_elaborate(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None simif = IncisiveInterface(prefix="prefix", output_path=self.output_path) config = SimConfig() self.assertTrue(simif.simulate("sim_output_path", "lib", "modulename", None, config, elaborate_only=True)) elaborate_args_file = join("sim_output_path", "irun_elaborate.args") run_command.assert_has_calls( [mock.call([join("prefix", "irun"), "-f", basename(elaborate_args_file)], cwd=dirname(elaborate_args_file))] ) self.assertEqual( read_file(elaborate_args_file).splitlines(), [ "-elaborate", "-nocopyright", "-licqueue", "-errormax 10", "-nowarn WRMNZD", "-nowarn DLCPTH", "-nowarn DLCVAR", "-ncerror EVBBOL", "-ncerror EVBSTR", "-ncerror EVBNAT", "-work work", '-nclibdirname "%s"' % join(self.output_path, "libraries"), '-cdslib "%s"' % join(self.output_path, "cds.lib"), '-log "sim_output_path/irun_elaborate.log"', "-quiet", "-access +r", '-input "@run"', '-input "@catch {if {#vunit_pkg::__runner__.exit_without_errors == 1} {exit 0} else {exit 42}}"', '-input "@catch {if {#run_base_pkg.runner.exit_without_errors == \\"TRUE\\"} {exit 0} else {exit 42}}"', "-top lib.modulename:sv", ], )
def test_simulate_gui(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None project = Project() project.add_library("lib", "lib_path") write_file("file.vhd", "") project.add_source_file("file.vhd", "lib", file_type="vhdl") simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, gui=True) with mock.patch("vunit.simulator_interface.check_output", autospec=True, return_value="") as dummy: simif.compile_project(project) config = make_config() self.assertTrue(simif.simulate("suite_output_path", "test_suite_name", config)) elaborate_args_file = join('suite_output_path', simif.name, 'irun_elaborate.args') simulate_args_file = join('suite_output_path', simif.name, 'irun_simulate.args') run_command.assert_has_calls([ mock.call([join('prefix', 'irun'), '-f', basename(elaborate_args_file)], cwd=dirname(elaborate_args_file), env=simif.get_env()), mock.call([join('prefix', 'irun'), '-f', basename(simulate_args_file)], cwd=dirname(simulate_args_file), env=simif.get_env()), ]) self.assertEqual( read_file(elaborate_args_file).splitlines(), ['-elaborate', '-nocopyright', '-licqueue', '-errormax 10', '-nowarn WRMNZD', '-nowarn DLCPTH', '-nowarn DLCVAR', '-ncerror EVBBOL', '-ncerror EVBSTR', '-ncerror EVBNAT', '-work work', '-nclibdirname "%s"' % join(self.output_path, "libraries"), '-cdslib "%s"' % join(self.output_path, "cds.lib"), '-log "%s"' % join("suite_output_path", simif.name, "irun_elaborate.log"), '-quiet', '-reflib "lib_path"', '-access +rwc', '-gui', '-top lib.ent:arch']) self.assertEqual( read_file(simulate_args_file).splitlines(), ['-nocopyright', '-licqueue', '-errormax 10', '-nowarn WRMNZD', '-nowarn DLCPTH', '-nowarn DLCVAR', '-ncerror EVBBOL', '-ncerror EVBSTR', '-ncerror EVBNAT', '-work work', '-nclibdirname "%s"' % join(self.output_path, "libraries"), '-cdslib "%s"' % join(self.output_path, "cds.lib"), '-log "%s"' % join("suite_output_path", simif.name, "irun_simulate.log"), '-quiet', '-reflib "lib_path"', '-access +rwc', '-gui', '-top lib.ent:arch'])
def test_simulate_gui(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None project = Project() project.add_library("lib", "lib_path") write_file("file.vhd", "") project.add_source_file("file.vhd", "lib", file_type="vhdl") simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, gui=True) with mock.patch("vunit.simulator_interface.run_command", autospec=True, return_value=True) as dummy: simif.compile_project(project) config = SimConfig() self.assertTrue(simif.simulate("sim_output_path", "lib", "ent", "arch", config)) elaborate_args_file = join("sim_output_path", "irun_elaborate.args") simulate_args_file = join("sim_output_path", "irun_simulate.args") run_command.assert_has_calls( [ mock.call( [join("prefix", "irun"), "-f", basename(elaborate_args_file)], cwd=dirname(elaborate_args_file) ), mock.call( [join("prefix", "irun"), "-f", basename(simulate_args_file)], cwd=dirname(simulate_args_file) ), ] ) self.assertEqual( read_file(elaborate_args_file).splitlines(), [ "-elaborate", "-nocopyright", "-licqueue", "-errormax 10", "-nowarn WRMNZD", "-nowarn DLCPTH", "-nowarn DLCVAR", "-ncerror EVBBOL", "-ncerror EVBSTR", "-ncerror EVBNAT", "-work work", '-nclibdirname "%s"' % join(self.output_path, "libraries"), '-cdslib "%s"' % join(self.output_path, "cds.lib"), '-log "sim_output_path/irun_elaborate.log"', "-quiet", '-reflib "lib_path"', "-access +rwc", "-gui", "-top lib.ent:arch", ], ) self.assertEqual( read_file(simulate_args_file).splitlines(), [ "-nocopyright", "-licqueue", "-errormax 10", "-nowarn WRMNZD", "-nowarn DLCPTH", "-nowarn DLCVAR", "-ncerror EVBBOL", "-ncerror EVBSTR", "-ncerror EVBNAT", "-work work", '-nclibdirname "%s"' % join(self.output_path, "libraries"), '-cdslib "%s"' % join(self.output_path, "cds.lib"), '-log "sim_output_path/irun_simulate.log"', "-quiet", '-reflib "lib_path"', "-access +rwc", "-gui", "-top lib.ent:arch", ], )
def test_simulate_verilog(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None simif = IncisiveInterface(prefix="prefix", output_path=self.output_path) project = Project() project.add_library("lib", "lib_path") write_file("file.vhd", "") project.add_source_file("file.vhd", "lib", file_type="vhdl") with mock.patch("vunit.simulator_interface.run_command", autospec=True, return_value=True) as dummy: simif.compile_project(project) config = SimConfig() self.assertTrue(simif.simulate("sim_output_path", "lib", "modulename", None, config)) elaborate_args_file = join('sim_output_path', 'irun_elaborate.args') simulate_args_file = join('sim_output_path', 'irun_simulate.args') run_command.assert_has_calls([ mock.call([join('prefix', 'irun'), '-f', basename(elaborate_args_file)], cwd=dirname(elaborate_args_file)), mock.call([join('prefix', 'irun'), '-f', basename(simulate_args_file)], cwd=dirname(simulate_args_file)), ]) self.assertEqual( read_file(elaborate_args_file).splitlines(), ['-elaborate', '-nocopyright', '-licqueue', '-errormax 10', '-nowarn WRMNZD', '-nowarn DLCPTH', '-nowarn DLCVAR', '-ncerror EVBBOL', '-ncerror EVBSTR', '-ncerror EVBNAT', '-work work', '-nclibdirname "%s"' % join(self.output_path, "libraries"), '-cdslib "%s"' % join(self.output_path, "cds.lib"), '-log "sim_output_path/irun_elaborate.log"', '-quiet', '-reflib "lib_path"', '-access +r', '-input "@run"', '-input "@catch {if {#vunit_pkg::__runner__.exit_without_errors == 1} {exit 0} else {exit 42}}"', '-input "@catch {if {#run_base_pkg.runner.exit_without_errors == \\"TRUE\\"} {exit 0} else {exit 42}}"', '-top lib.modulename:sv']) self.assertEqual( read_file(simulate_args_file).splitlines(), ['-nocopyright', '-licqueue', '-errormax 10', '-nowarn WRMNZD', '-nowarn DLCPTH', '-nowarn DLCVAR', '-ncerror EVBBOL', '-ncerror EVBSTR', '-ncerror EVBNAT', '-work work', '-nclibdirname "%s"' % join(self.output_path, "libraries"), '-cdslib "%s"' % join(self.output_path, "cds.lib"), '-log "sim_output_path/irun_simulate.log"', '-quiet', '-reflib "lib_path"', '-access +r', '-input "@run"', '-input "@catch {if {#vunit_pkg::__runner__.exit_without_errors == 1} {exit 0} else {exit 42}}"', '-input "@catch {if {#run_base_pkg.runner.exit_without_errors == \\"TRUE\\"} {exit 0} else {exit 42}}"', '-top lib.modulename:sv'])
def test_simulate_verilog(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None simif = IncisiveInterface(prefix="prefix", output_path=self.output_path) project = Project() project.add_library("lib", "lib_path") write_file("file.vhd", "") project.add_source_file("file.vhd", "lib", file_type="vhdl") with mock.patch("vunit.simulator_interface.check_output", autospec=True, return_value="") as dummy: simif.compile_project(project) config = make_config(verilog=True) self.assertTrue( simif.simulate("suite_output_path", "test_suite_name", config)) elaborate_args_file = join("suite_output_path", simif.name, "irun_elaborate.args") simulate_args_file = join("suite_output_path", simif.name, "irun_simulate.args") run_command.assert_has_calls([ mock.call( [join("prefix", "irun"), "-f", basename(elaborate_args_file)], cwd=dirname(elaborate_args_file), env=simif.get_env(), ), mock.call( [join("prefix", "irun"), "-f", basename(simulate_args_file)], cwd=dirname(simulate_args_file), env=simif.get_env(), ), ]) self.assertEqual( read_file(elaborate_args_file).splitlines(), [ "-elaborate", "-nocopyright", "-licqueue", "-errormax 10", "-nowarn WRMNZD", "-nowarn DLCPTH", "-nowarn DLCVAR", "-ncerror EVBBOL", "-ncerror EVBSTR", "-ncerror EVBNAT", "-work work", '-nclibdirname "%s"' % join(self.output_path, "libraries"), '-cdslib "%s"' % join(self.output_path, "cds.lib"), '-log "%s"' % join("suite_output_path", simif.name, "irun_elaborate.log"), "-quiet", '-reflib "lib_path"', "-access +r", '-input "@run"', "-top lib.modulename:sv", ], ) self.assertEqual( read_file(simulate_args_file).splitlines(), [ "-nocopyright", "-licqueue", "-errormax 10", "-nowarn WRMNZD", "-nowarn DLCPTH", "-nowarn DLCVAR", "-ncerror EVBBOL", "-ncerror EVBSTR", "-ncerror EVBNAT", "-work work", '-nclibdirname "%s"' % join(self.output_path, "libraries"), '-cdslib "%s"' % join(self.output_path, "cds.lib"), '-log "%s"' % join("suite_output_path", simif.name, "irun_simulate.log"), "-quiet", '-reflib "lib_path"', "-access +r", '-input "@run"', "-top lib.modulename:sv", ], )