def _describe_location(*codes): """ Helper to test describe_location """ contents = {} location = None for idx, code in enumerate(codes): filename = "filename%i" % idx contents[filename] = code start = code.index("S") if "E" in code: end = code.index("E") else: end = start location = ((filename, (start, end)), location) with mock.patch("vunit.parsing.tokenizer.read_file", autospec=True) as mock_read_file: with mock.patch("vunit.parsing.tokenizer.file_exists", autospec=True) as mock_file_exists: def file_exists_side_effect(filename): return filename in contents def read_file_side_effect(filename): return contents[filename] mock_file_exists.side_effect = file_exists_side_effect mock_read_file.side_effect = read_file_side_effect retval = describe_location(location=location) return retval
def test_find_implicit_test_verilog(self): with mock.patch("vunit.test_bench.LOGGER") as logger: test, = _find_tests("""\ `TEST_SUITE""", file_name="file_name.sv") self.assertEqual(test.name, None) self.assertEqual(test.location.file_name, "file_name.sv") self.assertEqual(test.location.lineno, 2) assert not logger.warning.called with mock.patch("vunit.test_bench.LOGGER") as logger: test, = _find_tests("""\ TEST_SUITE """, file_name="file_name.sv") self.assertEqual(test.name, None) self.assertEqual(test.location.file_name, "file_name.sv") self.assertEqual(test.location.lineno, 1) assert logger.warning.called with mock.patch("vunit.test_bench.LOGGER") as logger: test, = _find_tests("""\ """, file_name="file_name.sv") self.assertEqual(test.name, None) self.assertEqual(test.location.file_name, "file_name.sv") self.assertEqual(test.location.lineno, 1) assert logger.warning.called
def test_find_implicit_test_vhdl(self): with mock.patch("vunit.test_bench.LOGGER") as logger: test, = _find_tests("""\ test_runner_setup( """, file_name="file_name.vhd") self.assertEqual(test.name, None) self.assertEqual(test.location.file_name, "file_name.vhd") self.assertEqual(test.location.lineno, 2) assert not logger.warning.called with mock.patch("vunit.test_bench.LOGGER") as logger: test, = _find_tests("""\ test_runner_setup """, file_name="file_name.vhd") self.assertEqual(test.name, None) self.assertEqual(test.location.file_name, "file_name.vhd") self.assertEqual(test.location.lineno, 1) assert logger.warning.called with mock.patch("vunit.test_bench.LOGGER") as logger: test, = _find_tests("""\ """, file_name="file_name.vhd") self.assertEqual(test.name, None) self.assertEqual(test.location.file_name, "file_name.vhd") self.assertEqual(test.location.lineno, 1) assert logger.warning.called
def test_compile_source_files_check_output_error(self): simif = create_simulator_interface() simif.compile_source_file_command.return_value = ["command"] project = Project() project.add_library("lib", "lib_path") write_file("file.vhd", "") source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl") with mock.patch("vunit.simulator_interface.check_output", autospec=True) as check_output: def check_output_side_effect(command, env=None): # pylint: disable=missing-docstring, unused-argument raise subprocess.CalledProcessError(returncode=-1, cmd=command, output="bad stuff") check_output.side_effect = check_output_side_effect printer = MockPrinter() self.assertRaises(CompileError, simif.compile_source_files, project, printer=printer) self.assertEqual(printer.output, """\ Compiling into lib: file.vhd failed === Command used: === command === Command output: === bad stuff Compile failed """) check_output.assert_called_once_with(["command"], env=simif.get_env()) self.assertEqual(project.get_files_in_compile_order(incremental=True), [source_file])
def _create_cds_file(contents): """ Create a CDSFile object with 'contents' """ with mock.patch("vunit.cds_file.read_file", autospec=True) as read_file: read_file.return_value = contents return CDSFile.parse("file_name")
def _check_written_as(self, cds, contents): with mock.patch("vunit.cds_file.write_file", autospec=True) as write_file: cds.write("filename") self.assertEqual(len(write_file.mock_calls), 1) args = write_file.mock_calls[0][1] self.assertEqual(args[0], "filename") self.assertEqual(args[1], contents)
def test_simulate_gui(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None project = Project() project.add_library("lib", "lib_path") write_file("file.vhd", "") project.add_source_file("file.vhd", "lib", file_type="vhdl") simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, gui=True) with mock.patch("vunit.simulator_interface.check_output", autospec=True, return_value="") as dummy: simif.compile_project(project) config = make_config() self.assertTrue( simif.simulate("sim_output_path", "test_suite_name", config)) elaborate_args_file = join('sim_output_path', 'irun_elaborate.args') simulate_args_file = join('sim_output_path', 'irun_simulate.args') run_command.assert_has_calls([ mock.call( [join('prefix', 'irun'), '-f', basename(elaborate_args_file)], cwd=dirname(elaborate_args_file), env=simif.get_env()), mock.call( [join('prefix', 'irun'), '-f', basename(simulate_args_file)], cwd=dirname(simulate_args_file), env=simif.get_env()), ]) self.assertEqual( read_file(elaborate_args_file).splitlines(), [ '-elaborate', '-nocopyright', '-licqueue', '-errormax 10', '-nowarn WRMNZD', '-nowarn DLCPTH', '-nowarn DLCVAR', '-ncerror EVBBOL', '-ncerror EVBSTR', '-ncerror EVBNAT', '-work work', '-nclibdirname "%s"' % join(self.output_path, "libraries"), '-cdslib "%s"' % join(self.output_path, "cds.lib"), '-log "sim_output_path/irun_elaborate.log"', '-quiet', '-reflib "lib_path"', '-access +rwc', '-gui', '-top lib.ent:arch' ]) self.assertEqual( read_file(simulate_args_file).splitlines(), [ '-nocopyright', '-licqueue', '-errormax 10', '-nowarn WRMNZD', '-nowarn DLCPTH', '-nowarn DLCVAR', '-ncerror EVBBOL', '-ncerror EVBSTR', '-ncerror EVBNAT', '-work work', '-nclibdirname "%s"' % join(self.output_path, "libraries"), '-cdslib "%s"' % join(self.output_path, "cds.lib"), '-log "sim_output_path/irun_simulate.log"', '-quiet', '-reflib "lib_path"', '-access +rwc', '-gui', '-top lib.ent:arch' ])
def test_create_output_path_on_linux(self): with mock.patch("sys.platform", new="linux"): with mock.patch("os.environ", new={}): output_path = "output_path" test_name = "_" * 400 test_output = create_output_path(output_path, test_name) self.assertEqual(test_output, join(abspath(output_path), test_name + "_" + hash_string(test_name))) output_path = "output_path" test_name = "123._-+" test_output = create_output_path(output_path, test_name) self.assertEqual(test_output, join(abspath(output_path), test_name + "_" + hash_string(test_name))) output_path = "output_path" test_name = "#<>:" safe_name = "____" test_output = create_output_path(output_path, test_name) self.assertEqual(test_output, join(abspath(output_path), safe_name + "_" + hash_string(test_name)))
def test_tb_filter_match_prefix_and_suffix_only(self): """ Issue #263 """ with mock.patch("vunit.test_bench_list.LOGGER", autospec=True) as logger: design_unit = Entity("mul_tbl_scale") self.assertFalse(tb_filter(design_unit)) self.assertFalse(logger.warning.called)
def check_stdout(ui, expected): " Check that stdout matches expected " with mock.patch("sys.stdout", autospec=True) as stdout: self._run_main(ui) text = "".join([call[1][0] for call in stdout.write.mock_calls]) # @TODO not always in the same order in Python3 due to dependency graph print(text) self.assertEqual(set(text.splitlines()), set(expected.splitlines()))
def test_tb_filter_match_prefix_and_suffix_only(self, tempdir): """ Issue #263 """ with mock.patch("vunit.test_bench_list.LOGGER", autospec=True) as logger: design_unit = Entity("mul_tbl_scale", file_name=join(tempdir, "file.vhd")) self.assertFalse(tb_filter(design_unit)) self.assertFalse(logger.warning.called)
def test_compile_source_files_continue_on_error(self): simif = create_simulator_interface() project = Project() project.add_library("lib", "lib_path") write_file("file1.vhd", "") file1 = project.add_source_file("file1.vhd", "lib", file_type="vhdl") write_file("file2.vhd", "") file2 = project.add_source_file("file2.vhd", "lib", file_type="vhdl") write_file("file3.vhd", "") file3 = project.add_source_file("file3.vhd", "lib", file_type="vhdl") project.add_manual_dependency(file2, depends_on=file1) def compile_source_file_command(source_file): """ Dummy compile command """ if source_file == file1: return ["command1"] if source_file == file2: return ["command2"] if source_file == file3: return ["command3"] raise AssertionError def check_output_side_effect(command, env=None): # pylint: disable=missing-docstring, unused-argument if command == ["command1"]: raise subprocess.CalledProcessError(returncode=-1, cmd=command, output="bad stuff") return "" simif.compile_source_file_command.side_effect = compile_source_file_command with mock.patch("vunit.simulator_interface.check_output", autospec=True) as check_output: check_output.side_effect = check_output_side_effect printer = MockPrinter() self.assertRaises(CompileError, simif.compile_source_files, project, printer=printer, continue_on_error=True) self.assertEqual(printer.output, """\ Compiling into lib: file3.vhd passed Compiling into lib: file1.vhd failed === Command used: === command1 === Command output: === bad stuff Compiling into lib: file2.vhd skipped Compile failed """) self.assertEqual(len(check_output.mock_calls), 2) check_output.assert_has_calls([mock.call(["command1"], env=simif.get_env()), mock.call(["command3"], env=simif.get_env())], any_order=True) self.assertEqual(project.get_files_in_compile_order(incremental=True), [file1, file2])
def test_create_output_path_on_windows(self): with mock.patch("sys.platform", new="win32"): with mock.patch("os.environ", new={}): output_path = "output_path" test_name = "_" * 400 test_output = create_output_path(output_path, test_name) self.assertEqual(len(test_output), 260 - 100 + 1) with mock.patch("os.environ", new={"VUNIT_TEST_OUTPUT_PATH_MARGIN": "-1000"}): output_path = "output_path" test_name = "_" * 400 test_output = create_output_path(output_path, test_name) self.assertEqual(test_output, join(abspath(output_path), test_name + "_" + hash_string(test_name))) with mock.patch("os.environ", new={"VUNIT_SHORT_TEST_OUTPUT_PATHS": ""}): output_path = "output_path" test_name = "_" * 400 test_output = create_output_path(output_path, test_name) self.assertEqual(test_output, join(abspath(output_path), hash_string(test_name)))
def _check_written_as(self, cds, contents): """ Check that the CDSFile object writes the 'contents to the file """ with mock.patch("vunit.cds_file.write_file", autospec=True) as write_file: cds.write("filename") self.assertEqual(len(write_file.mock_calls), 1) args = write_file.mock_calls[0][1] self.assertEqual(args[0], "filename") self.assertEqual(args[1], contents)
def test_tb_filter_warning_on_runner_cfg_but_not_matching_tb_pattern(self): design_unit = Entity('entity_ok_but_warning') design_unit.generic_names = ["runner_cfg"] with mock.patch("vunit.test_bench_list.LOGGER", autospec=True) as logger: self.assertTrue(tb_filter(design_unit)) logger.warning.assert_has_calls([ mock.call( '%s %s has runner_cfg %s but the file name and the %s name does not match regex %s\n' 'in file %s', 'Entity', 'entity_ok_but_warning', 'generic', 'entity', '^(tb_.*)|(.*_tb)$', design_unit.file_name) ])
def test_compile_source_files_run_command_error(self): simif = create_simulator_interface() simif.compile_source_file_command.return_value = ["command"] project = Project() project.add_library("lib", "lib_path") write_file("file.vhd", "") source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl") with mock.patch("vunit.simulator_interface.run_command", autospec=True) as run_command: run_command.return_value = False self.assertRaises(CompileError, simif.compile_source_files, project) run_command.assert_called_once_with(["command"]) self.assertEqual(project.get_files_in_compile_order(incremental=True), [source_file])
def test_find_implicit_test_vhdl(self): with mock.patch("vunit.test_bench.LOGGER") as logger: test, = _find_tests( """\ test_runner_setup( """, file_name="file_name.vhd", ) self.assertEqual(test.name, None) self.assertEqual(test.location.file_name, "file_name.vhd") self.assertEqual(test.location.lineno, 2) assert not logger.warning.called with mock.patch("vunit.test_bench.LOGGER") as logger: test, = _find_tests( """\ test_runner_setup """, file_name="file_name.vhd", ) self.assertEqual(test.name, None) self.assertEqual(test.location.file_name, "file_name.vhd") self.assertEqual(test.location.lineno, 1) assert logger.warning.called with mock.patch("vunit.test_bench.LOGGER") as logger: test, = _find_tests( """\ """, file_name="file_name.vhd", ) self.assertEqual(test.name, None) self.assertEqual(test.location.file_name, "file_name.vhd") self.assertEqual(test.location.lineno, 1) assert logger.warning.called
def preprocess(self, code, file_name="fn.v", include_paths=None): """ Tokenize & Preprocess """ tokenizer = VerilogTokenizer() preprocessor = VerilogPreprocessor(tokenizer) write_file(file_name, code) tokens = tokenizer.tokenize(code, file_name=file_name) defines = {} included_files = [] with mock.patch("vunit.parsing.verilog.preprocess.LOGGER", autospec=True) as logger: tokens = preprocessor.preprocess(tokens, defines, include_paths, included_files) return PreprocessResult(self, tokens, defines, [file_name for _, file_name in included_files if file_name is not None], logger)
def test_tb_filter_warning_on_missing_runner_cfg_when_matching_tb_pattern( self): design_unit = Module('tb_module_not_ok') design_unit.generic_names = [] with mock.patch("vunit.test_bench_list.LOGGER", autospec=True) as logger: self.assertFalse(tb_filter(design_unit)) logger.warning.assert_has_calls([ mock.call( '%s %s matches testbench name regex %s ' 'but has no %s runner_cfg and will therefore not be run.\n' 'in file %s', 'Module', 'tb_module_not_ok', '^(tb_.*)|(.*_tb)$', 'parameter', design_unit.file_name) ])
def _test_warning_on_duplicate(self, code, message, verilog=False): """ Utility function to test adding the same duplicate code under file.vhd and file_copy.vhd where the duplication should cause a warning message. """ suffix = "v" if verilog else "vhd" self.add_source_file("lib", "file." + suffix, code) with mock.patch("vunit.project.LOGGER") as mock_logger: self.add_source_file("lib", "file_copy." + suffix, code) warning_calls = mock_logger.warning.call_args_list log_msg = warning_calls[0][0][0] % warning_calls[0][0][1:] self.assertEqual(len(warning_calls), 1) self.assertEqual(log_msg, message)
def test_compile_source_files_create_command_error(self): simif = create_simulator_interface() project = Project() project.add_library("lib", "lib_path") write_file("file.vhd", "") source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl") with mock.patch("vunit.simulator_interface.check_output", autospec=True) as check_output: check_output.return_value = "" def raise_compile_error(source_file): # pylint: disable=unused-argument raise CompileError simif.compile_source_file_command.side_effect = raise_compile_error self.assertRaises(CompileError, simif.compile_source_files, project) self.assertEqual(project.get_files_in_compile_order(incremental=True), [source_file])
def test_tb_filter_warning_on_runner_cfg_but_not_matching_tb_pattern(self, tempdir): design_unit = Entity('entity_ok_but_warning', file_name=join(tempdir, "file.vhd")) design_unit.generic_names = ["runner_cfg"] with mock.patch("vunit.test_bench_list.LOGGER", autospec=True) as logger: self.assertTrue(tb_filter(design_unit)) logger.warning.assert_has_calls([ mock.call('%s %s has runner_cfg %s but the file name and the %s name does not match regex %s\n' 'in file %s', 'Entity', 'entity_ok_but_warning', 'generic', 'entity', '^(tb_.*)|(.*_tb)$', design_unit.file_name)])
def test_tb_filter_warning_on_missing_runner_cfg_when_matching_tb_pattern(self, tempdir): design_unit = Module('tb_module_not_ok', file_name=join(tempdir, "file.vhd")) design_unit.generic_names = [] with mock.patch("vunit.test_bench_list.LOGGER", autospec=True) as logger: self.assertFalse(tb_filter(design_unit)) logger.warning.assert_has_calls([ mock.call('%s %s matches testbench name regex %s ' 'but has no %s runner_cfg and will therefore not be run.\n' 'in file %s', 'Module', 'tb_module_not_ok', '^(tb_.*)|(.*_tb)$', 'parameter', design_unit.file_name)])
def test_compile_source_files_create_command_error(self): simif = create_simulator_interface() project = Project() project.add_library("lib", "lib_path") write_file("file.vhd", "") source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl") with mock.patch("vunit.simulator_interface.run_command", autospec=True) as run_command: run_command.return_value = True def raise_compile_error(*args, **kwargs): raise CompileError simif.compile_source_file_command.side_effect = raise_compile_error self.assertRaises(CompileError, simif.compile_source_files, project) self.assertEqual(project.get_files_in_compile_order(incremental=True), [source_file])
def test_list_files_flag(self): ui = self._create_ui("--files") lib1 = ui.add_library("lib1") lib2 = ui.add_library("lib2") file_name = self.create_entity_file() lib1.add_source_file(file_name) lib2.add_source_file(file_name) with mock.patch("sys.stdout", autospec=True) as stdout: self._run_main(ui) text = "".join([call[1][0] for call in stdout.write.mock_calls]) # @TODO not always in the same order in Python3 due to dependency graph self.assertEqual(set(text.splitlines()), set("""\ lib2, ent0.vhd lib1, ent0.vhd Listed 2 files""".splitlines()))
def test_warning_on_missing_runner_cfg_when_matching_tb_pattern(self): project = ProjectStub() lib = project.add_library("lib") module = lib.add_module("tb_module_not_ok") with mock.patch("vunit.test_scanner.LOGGER", autospec=True) as logger: tests = self.test_scanner.from_project(project, entity_filter=tb_filter) logger.warning.assert_has_calls([ mock.call('%s %s matches testbench name regex %s ' 'but has no %s runner_cfg and will therefore not be run.\n' 'in file %s', 'Module', 'tb_module_not_ok', '(tb_.*)|(.*_tb)', 'parameter', module.file_name)]) self.assert_has_tests(tests, [])
def test_warning_on_runner_cfg_but_not_matching_tb_pattern(self): project = ProjectStub() lib = project.add_library("lib") entity = lib.add_entity("entity_ok_but_warning", generic_names=["runner_cfg"]) with mock.patch("vunit.test_scanner.LOGGER", autospec=True) as logger: tests = self.test_scanner.from_project(project, entity_filter=tb_filter) logger.warning.assert_has_calls([ mock.call('%s %s has runner_cfg %s but the file name and the %s name does not match regex %s\n' 'in file %s', 'Entity', 'entity_ok_but_warning', 'generic', 'entity', '(tb_.*)|(.*_tb)', entity.file_name)]) self.assert_has_tests(tests, ["lib.entity_ok_but_warning.all"])
def test_compile_source_files(self): simif = create_simulator_interface() simif.compile_source_file_command.side_effect = iter([["command1"], ["command2"]]) project = Project() project.add_library("lib", "lib_path") write_file("file1.vhd", "") file1 = project.add_source_file("file1.vhd", "lib", file_type="vhdl") write_file("file2.vhd", "") file2 = project.add_source_file("file2.vhd", "lib", file_type="vhdl") project.add_manual_dependency(file2, depends_on=file1) with mock.patch("vunit.simulator_interface.run_command", autospec=True) as run_command: run_command.side_effect = iter([True, True]) simif.compile_source_files(project) run_command.assert_has_calls([mock.call(["command1"]), mock.call(["command2"])]) self.assertEqual(project.get_files_in_compile_order(incremental=True), [])
def test_compile_source_files_continue_on_error(self): simif = create_simulator_interface() project = Project() project.add_library("lib", "lib_path") write_file("file1.vhd", "") file1 = project.add_source_file("file1.vhd", "lib", file_type="vhdl") write_file("file2.vhd", "") file2 = project.add_source_file("file2.vhd", "lib", file_type="vhdl") write_file("file3.vhd", "") file3 = project.add_source_file("file3.vhd", "lib", file_type="vhdl") project.add_manual_dependency(file2, depends_on=file1) def compile_source_file_command(source_file): if source_file == file1: return ["command1"] elif source_file == file2: return ["command2"] elif source_file == file3: return ["command3"] def run_command_side_effect(command, **kwargs): if command == ["command1"]: return False else: return True simif.compile_source_file_command.side_effect = compile_source_file_command with mock.patch("vunit.simulator_interface.run_command", autospec=True) as run_command: run_command.side_effect = run_command_side_effect self.assertRaises(CompileError, simif.compile_source_files, project, continue_on_error=True) self.assertEqual(len(run_command.mock_calls), 2) run_command.assert_has_calls([ mock.call(["command1"], env=simif.get_env()), mock.call(["command3"], env=simif.get_env()) ], any_order=True) self.assertEqual(project.get_files_in_compile_order(incremental=True), [file1, file2])
def test_compile_source_files_minimal_subset(self): simif = create_simulator_interface() project = Project() project.add_library("lib", "lib_path") write_file("file1.vhd", "") file1 = project.add_source_file("file1.vhd", "lib", file_type="vhdl") with mock.patch( "vunit.project.Project.get_minimal_file_set_in_compile_order", autospec=True) as target_function: target_function.return_value = [] printer = MockPrinter() simif.compile_source_files(project, printer=printer, target_files=[file1]) simif.compile_source_files(project, printer=printer, target_files=[file1]) self.assertTrue(target_function.called)
def test_compile_source_files_check_output_error(self): simif = create_simulator_interface() simif.compile_source_file_command.return_value = ["command"] project = Project() project.add_library("lib", "lib_path") write_file("file.vhd", "") source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl") with mock.patch("vunit.simulator_interface.check_output", autospec=True) as check_output: def check_output_side_effect(command, env=None): # pylint: disable=missing-docstring, unused-argument raise subprocess.CalledProcessError(returncode=-1, cmd=command, output="bad stuff") check_output.side_effect = check_output_side_effect printer = MockPrinter() self.assertRaises(CompileError, simif.compile_source_files, project, printer=printer) self.assertEqual( printer.output, """\ Compiling into lib: file.vhd failed === Command used: === command === Command output: === bad stuff Compile failed """, ) check_output.assert_called_once_with(["command"], env=simif.get_env()) self.assertEqual(project.get_files_in_compile_order(incremental=True), [source_file])
def test_tb_filter_warning_on_runner_cfg_but_not_matching_tb_pattern(self, tempdir): design_unit = Entity( "entity_ok_but_warning", file_name=join(tempdir, "file.vhd") ) design_unit.generic_names = ["runner_cfg"] with mock.patch("vunit.test_bench_list.LOGGER", autospec=True) as logger: self.assertTrue(tb_filter(design_unit)) logger.warning.assert_has_calls( [ mock.call( "%s %s has runner_cfg %s but the file name and the %s name does not match regex %s\n" "in file %s", "Entity", "entity_ok_but_warning", "generic", "entity", "^(tb_.*)|(.*_tb)$", design_unit.file_name, ) ] )
def test_tb_filter_warning_on_missing_runner_cfg_when_matching_tb_pattern( self, tempdir ): design_unit = Module("tb_module_not_ok", file_name=join(tempdir, "file.vhd")) design_unit.generic_names = [] with mock.patch("vunit.test_bench_list.LOGGER", autospec=True) as logger: self.assertFalse(tb_filter(design_unit)) logger.warning.assert_has_calls( [ mock.call( "%s %s matches testbench name regex %s " "but has no %s runner_cfg and will therefore not be run.\n" "in file %s", "Module", "tb_module_not_ok", "^(tb_.*)|(.*_tb)$", "parameter", design_unit.file_name, ) ] )
def test_compile_source_files(self): simif = create_simulator_interface() simif.compile_source_file_command.side_effect = iter([["command1"], ["command2"]]) project = Project() project.add_library("lib", "lib_path") write_file("file1.vhd", "") file1 = project.add_source_file("file1.vhd", "lib", file_type="vhdl") write_file("file2.vhd", "") file2 = project.add_source_file("file2.vhd", "lib", file_type="vhdl") project.add_manual_dependency(file2, depends_on=file1) with mock.patch("vunit.simulator_interface.check_output", autospec=True) as check_output: check_output.side_effect = iter(["", ""]) printer = MockPrinter() simif.compile_source_files(project, printer=printer) check_output.assert_has_calls([mock.call(["command1"], env=simif.get_env()), mock.call(["command2"], env=simif.get_env())]) self.assertEqual(printer.output, """\ Compiling into lib: file1.vhd passed Compiling into lib: file2.vhd passed Compile passed """) self.assertEqual(project.get_files_in_compile_order(incremental=True), [])
def test_compile_source_files_continue_on_error(self): simif = create_simulator_interface() project = Project() project.add_library("lib", "lib_path") write_file("file1.vhd", "") file1 = project.add_source_file("file1.vhd", "lib", file_type="vhdl") write_file("file2.vhd", "") file2 = project.add_source_file("file2.vhd", "lib", file_type="vhdl") write_file("file3.vhd", "") file3 = project.add_source_file("file3.vhd", "lib", file_type="vhdl") project.add_manual_dependency(file2, depends_on=file1) def compile_source_file_command(source_file): if source_file == file1: return ["command1"] elif source_file == file2: return ["command2"] elif source_file == file3: return ["command3"] def run_command_side_effect(command): if command == ["command1"]: return False else: return True simif.compile_source_file_command.side_effect = compile_source_file_command with mock.patch("vunit.simulator_interface.run_command", autospec=True) as run_command: run_command.side_effect = run_command_side_effect self.assertRaises(CompileError, simif.compile_source_files, project, continue_on_error=True) self.assertEqual(len(run_command.mock_calls), 2) run_command.assert_has_calls([mock.call(["command1"]), mock.call(["command3"])], any_order=True) self.assertEqual(project.get_files_in_compile_order(incremental=True), [file1, file2])
def _create_ui(self, *args): """ Create an instance of the VUnit public interface class """ with mock.patch("vunit.ui.SIMULATOR_FACTORY.select_simulator", new=lambda: MockSimulator): return self._create_ui_real_sim(*args)
def test_simulate_gui(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None project = Project() project.add_library("lib", "lib_path") write_file("file.vhd", "") project.add_source_file("file.vhd", "lib", file_type="vhdl") simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, gui=True) with mock.patch("vunit.simulator_interface.check_output", autospec=True, return_value="") as dummy: simif.compile_project(project) config = make_config() self.assertTrue(simif.simulate("suite_output_path", "test_suite_name", config)) elaborate_args_file = join('suite_output_path', simif.name, 'irun_elaborate.args') simulate_args_file = join('suite_output_path', simif.name, 'irun_simulate.args') run_command.assert_has_calls([ mock.call([join('prefix', 'irun'), '-f', basename(elaborate_args_file)], cwd=dirname(elaborate_args_file), env=simif.get_env()), mock.call([join('prefix', 'irun'), '-f', basename(simulate_args_file)], cwd=dirname(simulate_args_file), env=simif.get_env()), ]) self.assertEqual( read_file(elaborate_args_file).splitlines(), ['-elaborate', '-nocopyright', '-licqueue', '-errormax 10', '-nowarn WRMNZD', '-nowarn DLCPTH', '-nowarn DLCVAR', '-ncerror EVBBOL', '-ncerror EVBSTR', '-ncerror EVBNAT', '-work work', '-nclibdirname "%s"' % join(self.output_path, "libraries"), '-cdslib "%s"' % join(self.output_path, "cds.lib"), '-log "%s"' % join("suite_output_path", simif.name, "irun_elaborate.log"), '-quiet', '-reflib "lib_path"', '-access +rwc', '-gui', '-top lib.ent:arch']) self.assertEqual( read_file(simulate_args_file).splitlines(), ['-nocopyright', '-licqueue', '-errormax 10', '-nowarn WRMNZD', '-nowarn DLCPTH', '-nowarn DLCVAR', '-ncerror EVBBOL', '-ncerror EVBSTR', '-ncerror EVBNAT', '-work work', '-nclibdirname "%s"' % join(self.output_path, "libraries"), '-cdslib "%s"' % join(self.output_path, "cds.lib"), '-log "%s"' % join("suite_output_path", simif.name, "irun_simulate.log"), '-quiet', '-reflib "lib_path"', '-access +rwc', '-gui', '-top lib.ent:arch'])
def _create_cds_file(contents): with mock.patch("vunit.cds_file.read_file", autospec=True) as read_file: read_file.return_value = contents return CDSFile.parse("file_name")
def test_simulate_gui(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None project = Project() project.add_library("lib", "lib_path") write_file("file.vhd", "") project.add_source_file("file.vhd", "lib", file_type="vhdl") simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, gui=True) with mock.patch("vunit.simulator_interface.run_command", autospec=True, return_value=True) as dummy: simif.compile_project(project) config = SimConfig() self.assertTrue(simif.simulate("sim_output_path", "lib", "ent", "arch", config)) elaborate_args_file = join("sim_output_path", "irun_elaborate.args") simulate_args_file = join("sim_output_path", "irun_simulate.args") run_command.assert_has_calls( [ mock.call( [join("prefix", "irun"), "-f", basename(elaborate_args_file)], cwd=dirname(elaborate_args_file) ), mock.call( [join("prefix", "irun"), "-f", basename(simulate_args_file)], cwd=dirname(simulate_args_file) ), ] ) self.assertEqual( read_file(elaborate_args_file).splitlines(), [ "-elaborate", "-nocopyright", "-licqueue", "-errormax 10", "-nowarn WRMNZD", "-nowarn DLCPTH", "-nowarn DLCVAR", "-ncerror EVBBOL", "-ncerror EVBSTR", "-ncerror EVBNAT", "-work work", '-nclibdirname "%s"' % join(self.output_path, "libraries"), '-cdslib "%s"' % join(self.output_path, "cds.lib"), '-log "sim_output_path/irun_elaborate.log"', "-quiet", '-reflib "lib_path"', "-access +rwc", "-gui", "-top lib.ent:arch", ], ) self.assertEqual( read_file(simulate_args_file).splitlines(), [ "-nocopyright", "-licqueue", "-errormax 10", "-nowarn WRMNZD", "-nowarn DLCPTH", "-nowarn DLCVAR", "-ncerror EVBBOL", "-ncerror EVBSTR", "-ncerror EVBNAT", "-work work", '-nclibdirname "%s"' % join(self.output_path, "libraries"), '-cdslib "%s"' % join(self.output_path, "cds.lib"), '-log "sim_output_path/irun_simulate.log"', "-quiet", '-reflib "lib_path"', "-access +rwc", "-gui", "-top lib.ent:arch", ], )
def test_simulate_verilog(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None simif = IncisiveInterface(prefix="prefix", output_path=self.output_path) project = Project() project.add_library("lib", "lib_path") write_file("file.vhd", "") project.add_source_file("file.vhd", "lib", file_type="vhdl") with mock.patch("vunit.simulator_interface.run_command", autospec=True, return_value=True) as dummy: simif.compile_project(project) config = SimConfig() self.assertTrue(simif.simulate("sim_output_path", "lib", "modulename", None, config)) elaborate_args_file = join('sim_output_path', 'irun_elaborate.args') simulate_args_file = join('sim_output_path', 'irun_simulate.args') run_command.assert_has_calls([ mock.call([join('prefix', 'irun'), '-f', basename(elaborate_args_file)], cwd=dirname(elaborate_args_file)), mock.call([join('prefix', 'irun'), '-f', basename(simulate_args_file)], cwd=dirname(simulate_args_file)), ]) self.assertEqual( read_file(elaborate_args_file).splitlines(), ['-elaborate', '-nocopyright', '-licqueue', '-errormax 10', '-nowarn WRMNZD', '-nowarn DLCPTH', '-nowarn DLCVAR', '-ncerror EVBBOL', '-ncerror EVBSTR', '-ncerror EVBNAT', '-work work', '-nclibdirname "%s"' % join(self.output_path, "libraries"), '-cdslib "%s"' % join(self.output_path, "cds.lib"), '-log "sim_output_path/irun_elaborate.log"', '-quiet', '-reflib "lib_path"', '-access +r', '-input "@run"', '-input "@catch {if {#vunit_pkg::__runner__.exit_without_errors == 1} {exit 0} else {exit 42}}"', '-input "@catch {if {#run_base_pkg.runner.exit_without_errors == \\"TRUE\\"} {exit 0} else {exit 42}}"', '-top lib.modulename:sv']) self.assertEqual( read_file(simulate_args_file).splitlines(), ['-nocopyright', '-licqueue', '-errormax 10', '-nowarn WRMNZD', '-nowarn DLCPTH', '-nowarn DLCVAR', '-ncerror EVBBOL', '-ncerror EVBSTR', '-ncerror EVBNAT', '-work work', '-nclibdirname "%s"' % join(self.output_path, "libraries"), '-cdslib "%s"' % join(self.output_path, "cds.lib"), '-log "sim_output_path/irun_simulate.log"', '-quiet', '-reflib "lib_path"', '-access +r', '-input "@run"', '-input "@catch {if {#vunit_pkg::__runner__.exit_without_errors == 1} {exit 0} else {exit 42}}"', '-input "@catch {if {#run_base_pkg.runner.exit_without_errors == \\"TRUE\\"} {exit 0} else {exit 42}}"', '-top lib.modulename:sv'])
def test_simulate_verilog(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None simif = IncisiveInterface(prefix="prefix", output_path=self.output_path) project = Project() project.add_library("lib", "lib_path") write_file("file.vhd", "") project.add_source_file("file.vhd", "lib", file_type="vhdl") with mock.patch("vunit.simulator_interface.check_output", autospec=True, return_value="") as dummy: simif.compile_project(project) config = make_config(verilog=True) self.assertTrue( simif.simulate("suite_output_path", "test_suite_name", config)) elaborate_args_file = join("suite_output_path", simif.name, "irun_elaborate.args") simulate_args_file = join("suite_output_path", simif.name, "irun_simulate.args") run_command.assert_has_calls([ mock.call( [join("prefix", "irun"), "-f", basename(elaborate_args_file)], cwd=dirname(elaborate_args_file), env=simif.get_env(), ), mock.call( [join("prefix", "irun"), "-f", basename(simulate_args_file)], cwd=dirname(simulate_args_file), env=simif.get_env(), ), ]) self.assertEqual( read_file(elaborate_args_file).splitlines(), [ "-elaborate", "-nocopyright", "-licqueue", "-errormax 10", "-nowarn WRMNZD", "-nowarn DLCPTH", "-nowarn DLCVAR", "-ncerror EVBBOL", "-ncerror EVBSTR", "-ncerror EVBNAT", "-work work", '-nclibdirname "%s"' % join(self.output_path, "libraries"), '-cdslib "%s"' % join(self.output_path, "cds.lib"), '-log "%s"' % join("suite_output_path", simif.name, "irun_elaborate.log"), "-quiet", '-reflib "lib_path"', "-access +r", '-input "@run"', "-top lib.modulename:sv", ], ) self.assertEqual( read_file(simulate_args_file).splitlines(), [ "-nocopyright", "-licqueue", "-errormax 10", "-nowarn WRMNZD", "-nowarn DLCPTH", "-nowarn DLCVAR", "-ncerror EVBBOL", "-ncerror EVBSTR", "-ncerror EVBNAT", "-work work", '-nclibdirname "%s"' % join(self.output_path, "libraries"), '-cdslib "%s"' % join(self.output_path, "cds.lib"), '-log "%s"' % join("suite_output_path", simif.name, "irun_simulate.log"), "-quiet", '-reflib "lib_path"', "-access +r", '-input "@run"', "-top lib.modulename:sv", ], )