def __init__(self): # config self.cli = VUnitCLI() self.args = self.cli.parse_args() self.args.num_threads = 4 self.ui = VUnit.from_args(self.args) self.lib = self.ui.add_library("lib")
def setup_vunit(argv=None): ''' Sets up vunit logging and returns the VUnit object. ''' args = VUnitCLI().parse_args(argv=argv) log_level = args.log_level vu = VUnit.from_args(args) vu.log_level = getattr(logging, log_level.upper()) return vu
def __init__(self): # config self.cli = VUnitCLI() self.args = self.cli.parse_args() self.args.gtkwave_fmt = 'vcd' self.args.num_threads = 4 #self.args.log_level = 'info' self.ui = VUnit.from_args(self.args) self.lib = self.ui.add_library("lib")
def run_with_compile_errors(ui, args, vhdl_standard): def match(name, patterns): return reduce( lambda found_match, pattern: found_match | fnmatch(name, pattern), patterns, False, ) # Run all tests in isolation to handle failure to compile args.minimal = True original_test_patterns = args.test_patterns test_report = TestReport() n_tests = 0 testbenches = (ui.library("vhdl_2008").get_test_benches() + ui.library("vhdl_2019").get_test_benches()) total_start_time = ostools.get_time() for tb in testbenches: tests = tb.get_tests() if not tests: test_names = ["all"] else: test_names = [test.name for test in tests] for test_name in test_names: full_test_name = "%s.%s.%s" % (tb.library.name, tb.name, test_name) if not match(full_test_name, original_test_patterns): continue test_start_time = ostools.get_time() n_tests += 1 args.test_patterns = [full_test_name] ui = VUnit.from_args(args, vhdl_standard=vhdl_standard) vhdl_2008 = ui.add_library("vhdl_2008") vhdl_2019 = ui.add_library("vhdl_2019") vhdl_2008.add_source_files(join(root, "vhdl_2008", "*.vhd")) vhdl_2019.add_source_files(join(root, "vhdl_2019", "*.vhd")) try: ui.main() except SystemExit as ex: tb_time = ostools.get_time() - test_start_time if ex.code == 0: test_report.add_result(full_test_name, PASSED, tb_time, None) else: test_report.add_result(full_test_name, FAILED, tb_time, None) print("\nCompliance test completed:\n") test_report.set_expected_num_tests(n_tests) test_report.set_real_total_time(ostools.get_time() - total_start_time) test_report.print_str()
def main(): "Main entry point for DVB FPGA test runner" _generateGnuRadioData() _createLdpcTables() cli = VUnitCLI() cli.parser.add_argument( "--individual-config-runs", "-i", action="store_true", help="Create individual test runs for each configuration. By default, " "all combinations of frame lengths, code rates and modulations are " "tested in the same simulation", ) args = cli.parse_args() vunit = VUnit.from_args(args=args) vunit.add_osvvm() vunit.add_com() vunit.enable_location_preprocessing() if vunit.get_simulator_name() == "ghdl": vunit.add_preprocessor(GhdlPragmaHandler()) library = vunit.add_library("lib") library.add_source_files(p.join(ROOT, "rtl", "*.vhd")) library.add_source_files(p.join(ROOT, "rtl", "ldpc", "*.vhd")) library.add_source_files(p.join(ROOT, "rtl", "bch_generated", "*.vhd")) library.add_source_files(p.join(ROOT, "testbench", "*.vhd")) vunit.add_library("str_format").add_source_files( p.join(ROOT, "third_party", "hdl_string_format", "src", "*.vhd")) vunit.add_library("fpga_cores").add_source_files( p.join(ROOT, "third_party", "fpga_cores", "src", "*.vhd")) vunit.add_library("fpga_cores_sim").add_source_files( p.join(ROOT, "third_party", "fpga_cores", "sim", "*.vhd")) if args.individual_config_runs: # BCH encoding doesn't depend on the constellation type, choose any for config in _getConfigs( constellations=(ConstellationType.MOD_8PSK, )): vunit.library("lib").entity("axi_bch_encoder_tb").add_config( name=config.name, generics=dict( test_cfg=config.getTestConfigString(), NUMBER_OF_TEST_FRAMES=8, ), ) vunit.library("lib").entity("dvbs2_tx_tb").add_config( name=config.name, generics=dict( test_cfg=config.getTestConfigString(), NUMBER_OF_TEST_FRAMES=2, ), ) # Only generate configs for 8 PSK since LDPC does not depend on this # parameter for config in _getConfigs( constellations=(ConstellationType.MOD_8PSK, ), ): vunit.library("lib").entity("axi_ldpc_encoder_tb").add_config( name=config.name, generics=dict( test_cfg=config.getTestConfigString(), NUMBER_OF_TEST_FRAMES=3, ), ) else: addAllConfigsTest( entity=vunit.library("lib").entity("axi_bch_encoder_tb"), configs=TEST_CONFIGS, ) addAllConfigsTest( entity=vunit.library("lib").entity("axi_ldpc_encoder_tb"), configs=_getConfigs( constellations=(ConstellationType.MOD_8PSK, ), ), ) addAllConfigsTest( entity=vunit.library("lib").entity("dvbs2_tx_tb"), configs=tuple(TEST_CONFIGS), ) addAllConfigsTest( entity=vunit.library("lib").entity("axi_baseband_scrambler_tb"), configs=TEST_CONFIGS, ) # Generate bit interleaver tests for data_width in (1, 8): all_configs = [] for config in _getConfigs(): all_configs += [config.getTestConfigString()] if args.individual_config_runs: vunit.library("lib").entity( "axi_bit_interleaver_tb").add_config( name=f"data_width={data_width},{config.name}", generics=dict( DATA_WIDTH=data_width, test_cfg=config.getTestConfigString(), NUMBER_OF_TEST_FRAMES=8, ), ) if not args.individual_config_runs: vunit.library("lib").entity("axi_bit_interleaver_tb").add_config( name=f"data_width={data_width},all_parameters", generics=dict( DATA_WIDTH=data_width, test_cfg="|".join(all_configs), NUMBER_OF_TEST_FRAMES=2, ), ) vunit.set_compile_option("modelsim.vcom_flags", ["-explicit"]) # Not all options are supported by all GHDL backends vunit.set_sim_option("ghdl.elab_flags", ["-frelaxed-rules"]) vunit.set_compile_option("ghdl.a_flags", ["-frelaxed-rules", "-O2", "-g"]) # Make components not bound (error 3473) an error vsim_flags = ["-error", "3473"] if args.gui: vsim_flags += ['-voptargs="+acc=n"'] vunit.set_sim_option("modelsim.vsim_flags", vsim_flags) vunit.set_sim_option("disable_ieee_warnings", True) vunit.set_sim_option("modelsim.init_file.gui", p.join(ROOT, "wave.do")) vunit.main()
# ------- from vunit import VUnit, VUnitCLI root = dirname(__file__) # These lines add the option to specify the Bitvis Utility Library root directory # from the command line (python run.py -b <path to my BVUL root>). They # can be replaced by a single line, ui = VUnit.from_argv(), if you assign the root # directory to the bvul_root variable directly cli = VUnitCLI() cli.parser.add_argument('-b', '--bvul-root', required=True, help='Bitvis Utility Library root directory') args = cli.parse_args() ui = VUnit.from_args(args) # ------ # Create VHDL libraries and add the related BVUL files to these bvul_root = args.bvul_root bvul_lib = ui.add_library('bitvis_util') bvul_lib.add_source_files(join(bvul_root, 'bitvis_util', 'src2008', '*.vhd')) bitvis_vip_spi_lib = ui.add_library('bitvis_vip_sbi') bitvis_vip_spi_lib.add_source_files(join(bvul_root, 'bitvis_vip_sbi', 'src', '*.vhd')) # Add all testbenches to lib lib = ui.add_library('lib') lib.add_source_files(join(root, 'test', '*.vhd'))
depth_b = int(depth_a * width_a / width_b) for reg in oreg: # due to memory model limitation if not (width_a == 32 and width_b == 32): test.add_config( name= "deptha=%d,depthb=%d,widtha=%d,widthb=%d,reg=%s" % (depth_a, depth_b, width_a, width_b, reg), generics=dict(g_width_a=width_a, g_width_b=width_b, g_depth_a=depth_a, g_depth_b=depth_b, g_register=reg)) if __name__ == "__main__": cli = VUnitCLI() cli.parser.add_argument('--cover', type=int, default=0, help='Enable ghdl coverage') args = cli.parse_args() VU = VUnit.from_args(args=args) VU.add_osvvm() create_test_suite(VU, args) if args.cover < 1: VU.main() else: VU.main(post_run=post_run)
from vunit import VUnit, VUnitCLI root = dirname(__file__) # These lines add the option to specify the UVVM Utility Library root directory # from the command line (python run.py -b <path to my UVVM root>). They # can be replaced by a single line, ui = VUnit.from_argv(), if you assign the root # directory to the uvvm_root variable directly cli = VUnitCLI() cli.parser.add_argument('-u', '--uvvm-root', required=True, help='UVVM Utility Library root directory') args = cli.parse_args() ui = VUnit.from_args(args) # ------ # Create VHDL libraries and add the related UVVM files to these uvvm_root = args.uvvm_root uvvm_lib = ui.add_library('uvvm_util') uvvm_lib.add_source_files(join(uvvm_root, 'uvvm_util', 'src', '*.vhd')) bitvis_vip_spi_lib = ui.add_library('bitvis_vip_sbi') bitvis_vip_spi_lib.add_source_files( join(uvvm_root, 'bitvis_vip_sbi', 'src', '*.vhd')) # Add all testbenches to lib lib = ui.add_library('lib') lib.add_source_files(join(root, 'test', 'tb_uvvm_integration.vhd'))
from os.path import join, dirname from vunit import VUnit, VUnitCLI from vunit.simulator_factory import SIMULATOR_FACTORY from run_support import run_with_compile_errors root = dirname(__file__) vhdl_standard = ("2019" if SIMULATOR_FACTORY.select_simulator().name == "rivierapro" else "2008") args = VUnitCLI().parse_args() # keep_going is a planned VUnit feature which adds support for dealing with testbenches # that don't compile if "keep_going" in args: args.keep_going = True ui = VUnit.from_args(args, vhdl_standard=vhdl_standard) vhdl_2008 = ui.add_library("vhdl_2008") vhdl_2019 = ui.add_library("vhdl_2019") vhdl_2008.add_source_files(join(root, "vhdl_2008", "*.vhd")) vhdl_2019.add_source_files(join(root, "vhdl_2019", "*.vhd")) if "keep_going" in args: ui.main() else: # Workaround while keep_going isn't supported run_with_compile_errors(ui, args, vhdl_standard)
def create_project(root, args): """ Create VUnit project """ prj = VUnit.from_args(args) if not args.vendor_verification: prj.add_preprocessor(IEEEPreprocessor()) prj.enable_check_preprocessing() new_ieee = prj.add_library("new_ieee") if not args.vendor_verification: new_ieee.add_source_files(str(root / "../ieee/*.vhdl")) new_ieee.add_source_files(str(root / "*.vhdl")) # Work around pending VUnit dependency scanning updates test_fixed = new_ieee.get_source_files("*test_fixed.vhdl") test_fixed2 = new_ieee.get_source_files("*test_fixed2.vhdl") test_fixed3 = new_ieee.get_source_files("*test_fixed3.vhdl") test_fixed_nr = new_ieee.get_source_files("*test_fixed_nr.vhdl") test_fphdl = new_ieee.get_source_files("*test_fphdl.vhdl") test_fphdl16 = new_ieee.get_source_files("*test_fphdl16.vhdl") test_fphdl64 = new_ieee.get_source_files("*test_fphdl64.vhdl") test_fphdl128 = new_ieee.get_source_files("*test_fphdl128.vhdl") test_fphdlbase = new_ieee.get_source_files("*test_fphdlbase.vhdl") test_fpfixed = new_ieee.get_source_files("*test_fpfixed.vhdl") test_fp32 = new_ieee.get_source_files("*test_fp32.vhdl") fixed_noround_pkg = new_ieee.get_source_files("*fixed_noround_pkg.vhdl") float_roundneg_pkg = new_ieee.get_source_files("*float_roundneg_pkg.vhdl") float_noround_pkg = new_ieee.get_source_files("*float_noround_pkg.vhdl") if not args.vendor_verification: fixed_pkg = new_ieee.get_source_files("*fixed_pkg.vhdl") float_pkg = new_ieee.get_source_files("*float_pkg.vhdl") fixed_generic_pkg_body = new_ieee.get_source_files( "*fixed_generic_pkg-body.vhdl") float_generic_pkg = new_ieee.get_source_files( "*float_generic_pkg.vhdl") float_generic_pkg_body = new_ieee.get_source_files( "*float_generic_pkg-body.vhdl") if not args.vendor_verification: float_pkg.add_dependency_on(fixed_pkg) float_pkg.add_dependency_on(float_generic_pkg_body) fixed_pkg.add_dependency_on(fixed_generic_pkg_body) float_generic_pkg.add_dependency_on(fixed_pkg) test_fixed.add_dependency_on(fixed_pkg) test_fixed2.add_dependency_on(fixed_pkg) test_fixed3.add_dependency_on(fixed_pkg) test_fphdlbase.add_dependency_on(fixed_pkg) test_fpfixed.add_dependency_on(fixed_pkg) test_fp32.add_dependency_on(fixed_pkg) test_fphdl64.add_dependency_on(float_pkg) test_fphdl128.add_dependency_on(float_pkg) test_fphdlbase.add_dependency_on(float_pkg) test_fpfixed.add_dependency_on(float_pkg) test_fp32.add_dependency_on(float_pkg) float_roundneg_pkg.add_dependency_on(float_generic_pkg_body) float_noround_pkg.add_dependency_on(float_generic_pkg_body) fixed_noround_pkg.add_dependency_on(fixed_generic_pkg_body) test_fphdl.add_dependency_on(float_roundneg_pkg) test_fphdl16.add_dependency_on(float_noround_pkg) test_fixed_nr.add_dependency_on(fixed_noround_pkg) prj.set_sim_option("vhdl_assert_stop_level", "warning") for testbench in new_ieee.get_test_benches(): for test_case in testbench.get_tests(): if test_case.name.startswith("Expected to warn"): levels = ["warning", "error"] elif test_case.name.startswith("Expected to fail"): levels = ["error", "failure"] else: levels = [] for level in levels: sim_options = dict(vhdl_assert_stop_level=level) test_case.add_config(name="stop@%s" % level, sim_options=sim_options) return prj
def setup_vunit(argv=None): args = VUnitCLI().parse_args(argv=argv) log_level = args.log_level vu = VUnit.from_args(args) vu.log_level = getattr(logging, log_level.upper()) return vu
for key, test in report.tests.items(): wave_file = f'{test.path}/ghdl/wave.vcd' system(f'{WAVE_VIEWER} {wave_file}') if __name__ == "__main__": cli = VUnitCLI() cli.parser.add_argument('--wave', action='store_true', default=False, help='Show wave file in the set viewer.') args = cli.parse_args() if args.wave: args.gtkwave_fmt = "vcd" project = VUnit.from_args(args=args) project.enable_check_preprocessing() project.enable_location_preprocessing() root = dirname(__file__) entity = project.add_library('{{cookiecutter.project_name}}') entity.add_source_files(join(root, 'src', '*.vhd')) entity.add_source_files(join(root, 'sim', '*.vhd')) if args.wave: project.main(post_run=show) else: project.main()
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. from collections import OrderedDict import os.path from fusesoc.config import Config from fusesoc.coremanager import CoreManager, DependencyError from vunit import VUnitCLI, VUnit cli = VUnitCLI() cli.parser.add_argument('--core', nargs=1, required=True, help='Top-level FuseSoC core') args = cli.parse_args() # Create VUnit instance by parsing command line arguments vu = VUnit.from_args(args=args) top_core = args.core[0] #Create singleton instances for core manager and configuration handler #Configuration manager is not needed in this example cm = CoreManager() #config = Config() #Add core libraries that were picked up from fusesoc.conf by the config handler #Not really necessary for this example as we can just add 'corelib' manually try: #cm.add_cores_root(config.cores_root) cm.add_cores_root('corelib') except (RuntimeError, IOError) as e: pr_warn("Failed to register cores root '{}'".format(str(e)))
def vunit_from_args(args, vhdl_standard): ui = VUnit.from_args(args, vhdl_standard=vhdl_standard) for std in ["2008", "2019"]: lib = f"vhdl_{std}" ui.add_library(lib).add_source_files(ROOT / lib / "*.vhd") return ui