def bench():
# Parameters
DATA_WIDTH = 32
ADDR_WIDTH = 32
SELECT_WIDTH = 4
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
wbm_adr_i = Signal(intbv(0)[ADDR_WIDTH:])
wbm_dat_i = Signal(intbv(0)[DATA_WIDTH:])
wbm_we_i = Signal(bool(0))
wbm_sel_i = Signal(intbv(0)[SELECT_WIDTH:])
wbm_stb_i = Signal(bool(0))
wbm_cyc_i = Signal(bool(0))
wbs0_dat_i = Signal(intbv(0)[DATA_WIDTH:])
wbs0_ack_i = Signal(bool(0))
wbs0_err_i = Signal(bool(0))
wbs0_rty_i = Signal(bool(0))
wbs0_addr = Signal(intbv(0)[ADDR_WIDTH:])
wbs0_addr_msk = Signal(intbv(0)[ADDR_WIDTH:])
wbs1_dat_i = Signal(intbv(0)[DATA_WIDTH:])
wbs1_ack_i = Signal(bool(0))
wbs1_err_i = Signal(bool(0))
wbs1_rty_i = Signal(bool(0))
wbs1_addr = Signal(intbv(0)[ADDR_WIDTH:])
wbs1_addr_msk = Signal(intbv(0)[ADDR_WIDTH:])
# Outputs
wbm_dat_o = Signal(intbv(0)[DATA_WIDTH:])
wbm_ack_o = Signal(bool(0))
wbm_err_o = Signal(bool(0))
wbm_rty_o = Signal(bool(0))
wbs0_adr_o = Signal(intbv(0)[ADDR_WIDTH:])
wbs0_dat_o = Signal(intbv(0)[DATA_WIDTH:])
wbs0_we_o = Signal(bool(0))
wbs0_sel_o = Signal(intbv(0)[SELECT_WIDTH:])
wbs0_stb_o = Signal(bool(0))
wbs0_cyc_o = Signal(bool(0))
wbs1_adr_o = Signal(intbv(0)[ADDR_WIDTH:])
wbs1_dat_o = Signal(intbv(0)[DATA_WIDTH:])
wbs1_we_o = Signal(bool(0))
wbs1_sel_o = Signal(intbv(0)[SELECT_WIDTH:])
wbs1_stb_o = Signal(bool(0))
wbs1_cyc_o = Signal(bool(0))
# WB master
wbm_inst = wb.WBMaster()
wbm_logic = wbm_inst.create_logic(clk,
adr_o=wbm_adr_i,
dat_i=wbm_dat_o,
dat_o=wbm_dat_i,
we_o=wbm_we_i,
sel_o=wbm_sel_i,
stb_o=wbm_stb_i,
ack_i=wbm_ack_o,
cyc_o=wbm_cyc_i,
name='master')
# WB RAM model
wb_ram0_inst = wb.WBRam(2**16)
wb_ram0_port0 = wb_ram0_inst.create_port(clk,
adr_i=wbs0_adr_o,
dat_i=wbs0_dat_o,
dat_o=wbs0_dat_i,
we_i=wbs0_we_o,
sel_i=wbs0_sel_o,
stb_i=wbs0_stb_o,
ack_o=wbs0_ack_i,
cyc_i=wbs0_cyc_o,
latency=1,
async=False,
name='slave0')
# WB RAM model
wb_ram1_inst = wb.WBRam(2**16)
wb_ram1_port0 = wb_ram1_inst.create_port(clk,
adr_i=wbs1_adr_o,
dat_i=wbs1_dat_o,
dat_o=wbs1_dat_i,
we_i=wbs1_we_o,
sel_i=wbs1_sel_o,
stb_i=wbs1_stb_o,
ack_o=wbs1_ack_i,
cyc_i=wbs1_cyc_o,
latency=1,
async=False,
name='slave1')
# DUT
dut = dut_wb_mux_2(clk, rst, current_test, wbm_adr_i, wbm_dat_i, wbm_dat_o,
wbm_we_i, wbm_sel_i, wbm_stb_i, wbm_ack_o, wbm_err_o,
wbm_rty_o, wbm_cyc_i, wbs0_adr_o, wbs0_dat_i,
wbs0_dat_o, wbs0_we_o, wbs0_sel_o, wbs0_stb_o,
wbs0_ack_i, wbs0_err_i, wbs0_rty_i, wbs0_cyc_o,
wbs0_addr, wbs0_addr_msk, wbs1_adr_o, wbs1_dat_i,
wbs1_dat_o, wbs1_we_o, wbs1_sel_o, wbs1_stb_o,
wbs1_ack_i, wbs1_err_i, wbs1_rty_i, wbs1_cyc_o,
wbs1_addr, wbs1_addr_msk)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
wbs0_addr.next = 0x00000000
wbs0_addr_msk.next = 0xFFFF0000
wbs1_addr.next = 0x00010000
wbs1_addr_msk.next = 0xFFFF0000
yield clk.posedge
print("test 1: write to slave 0")
current_test.next = 1
wbm_inst.init_write(0x00000004, b'\x11\x22\x33\x44')
yield wbm_inst.wait()
yield clk.posedge
data = wb_ram0_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram0_inst.read_mem(4, 4) == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 2: read from slave 0")
current_test.next = 2
wbm_inst.init_read(0x00000004, 4)
yield wbm_inst.wait()
yield clk.posedge
data = wbm_inst.get_read_data()
assert data[0] == 0x00000004
assert data[1] == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 3: write to slave 1")
current_test.next = 3
wbm_inst.init_write(0x00010004, b'\x11\x22\x33\x44')
yield wbm_inst.wait()
yield clk.posedge
data = wb_ram1_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram1_inst.read_mem(4, 4) == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 4: read from slave 1")
current_test.next = 4
wbm_inst.init_read(0x00010004, 4)
yield wbm_inst.wait()
yield clk.posedge
data = wbm_inst.get_read_data()
assert data[0] == 0x00010004
assert data[1] == b'\x11\x22\x33\x44'
yield delay(100)
raise StopSimulation
return dut, wbm_logic, wb_ram0_port0, wb_ram1_port0, clkgen, check
def bench():
# Parameters
IMPLICIT_FRAMING = 0
COUNT_SIZE = 16
AXIS_DATA_WIDTH = 8
AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH / 8)
WB_DATA_WIDTH = 32
WB_ADDR_WIDTH = 32
WB_SELECT_WIDTH = (WB_DATA_WIDTH / 8)
READ_REQ = 0xA1
WRITE_REQ = 0xA2
READ_RESP = 0xA3
WRITE_RESP = 0xA4
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(1)[AXIS_KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
output_axis_tready = Signal(bool(0))
wb_dat_i = Signal(intbv(0)[WB_DATA_WIDTH:])
wb_ack_i = Signal(bool(0))
wb_err_i = Signal(bool(0))
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(1)[AXIS_KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
wb_adr_o = Signal(intbv(0)[WB_ADDR_WIDTH:])
wb_dat_o = Signal(intbv(0)[WB_DATA_WIDTH:])
wb_we_o = Signal(bool(0))
wb_sel_o = Signal(intbv(0)[WB_SELECT_WIDTH:])
wb_stb_o = Signal(bool(0))
wb_cyc_o = Signal(bool(0))
busy = Signal(bool(0))
# sources and sinks
source_pause = Signal(bool(0))
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource()
source_logic = source.create_logic(clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source')
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink')
# WB RAM model
wb_ram_inst = wb.WBRam(2**16)
wb_ram_port0 = wb_ram_inst.create_port(clk,
adr_i=wb_adr_o,
dat_i=wb_dat_o,
dat_o=wb_dat_i,
we_i=wb_we_o,
sel_i=wb_sel_o,
stb_i=wb_stb_o,
ack_o=wb_ack_i,
cyc_i=wb_cyc_o,
latency=1,
asynchronous=False,
name='port0')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
wb_adr_o=wb_adr_o,
wb_dat_i=wb_dat_i,
wb_dat_o=wb_dat_o,
wb_we_o=wb_we_o,
wb_sel_o=wb_sel_o,
wb_stb_o=wb_stb_o,
wb_ack_i=wb_ack_i,
wb_err_i=wb_err_i,
wb_cyc_o=wb_cyc_o,
busy=busy)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: test write")
current_test.next = 1
source.send(
bytearray(b'\xA2' + struct.pack('>IH', 0, 4) +
b'\x11\x22\x33\x44'))
yield clk.posedge
yield input_axis_tvalid.negedge
yield delay(100)
yield clk.posedge
data = wb_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(0, 4) == b'\x11\x22\x33\x44'
rx_data = bytearray(sink.read())
print(repr(rx_data))
assert rx_data == b'\xA4' + struct.pack('>IH', 0, 4)
yield delay(100)
yield clk.posedge
print("test 2: test read")
current_test.next = 2
source.send(bytearray(b'\xA1' + struct.pack('>IH', 0, 4)))
yield clk.posedge
yield input_axis_tvalid.negedge
yield delay(100)
yield clk.posedge
rx_data = bytearray(sink.read())
print(repr(rx_data))
assert rx_data == b'\xA3' + struct.pack('>IH', 0,
4) + b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 3: various writes")
current_test.next = 3
for length in range(1, 9):
for offset in range(4, 8):
wb_ram_inst.write_mem(256 * (16 * offset + length),
b'\xAA' * 16)
source.send(
bytearray(
b'\xA2' +
struct.pack('>IH', 256 *
(16 * offset + length) + offset, length) +
b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]))
yield clk.posedge
yield input_axis_tvalid.negedge
yield delay(200)
yield clk.posedge
data = wb_ram_inst.read_mem(256 * (16 * offset + length), 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(
256 * (16 * offset + length) + offset,
length) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
assert wb_ram_inst.read_mem(
256 * (16 * offset + length) + offset - 1, 1) == b'\xAA'
assert wb_ram_inst.read_mem(
256 * (16 * offset + length) + offset + length,
1) == b'\xAA'
rx_data = bytearray(sink.read())
print(repr(rx_data))
assert rx_data == b'\xA4' + struct.pack(
'>IH', 256 * (16 * offset + length) + offset, length)
yield delay(100)
yield clk.posedge
print("test 4: various reads")
current_test.next = 4
for length in range(1, 9):
for offset in range(4, 8):
source.send(
bytearray(
b'\xA1' +
struct.pack('>IH', 256 *
(16 * offset + length) + offset, length)))
yield clk.posedge
yield input_axis_tvalid.negedge
yield delay(200)
yield clk.posedge
rx_data = bytearray(sink.read())
print(repr(rx_data))
assert rx_data == b'\xA3' + struct.pack(
'>IH', 256 * (16 * offset + length) + offset,
length) + b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
yield delay(100)
yield clk.posedge
print("test 5: test leading padding")
current_test.next = 5
source.send(bytearray(b'\xA2' + struct.pack('>IH', 4, 1) + b'\xAA'))
source.send(
bytearray(b'\x00' * 8 + b'\xA2' + struct.pack('>IH', 5, 1) +
b'\xBB'))
source.send(bytearray(b'\x00' * 8 + b'\xA1' +
struct.pack('>IH', 4, 1)))
source.send(bytearray(b'\xA2' + struct.pack('>IH', 6, 1) + b'\xCC'))
yield clk.posedge
yield input_axis_tvalid.negedge
yield delay(100)
yield clk.posedge
data = wb_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(4, 3) == b'\xAA\xBB\xCC'
rx_data = bytearray(sink.read())
print(repr(rx_data))
assert rx_data == b'\xA4' + struct.pack(
'>IH', 4,
1) + b'\xA4' + struct.pack('>IH', 5, 1) + b'\xA3' + struct.pack(
'>IH', 4, 1) + b'\xAA' + b'\xA4' + struct.pack('>IH', 6, 1)
yield delay(100)
yield clk.posedge
print("test 6: test trailing padding")
current_test.next = 6
source.send(bytearray(b'\xA2' + struct.pack('>IH', 7, 1) + b'\xAA'))
source.send(
bytearray(b'\xA2' + struct.pack('>IH', 8, 1) + b'\xBB' +
b'\x00' * 8))
source.send(bytearray(b'\xA1' + struct.pack('>IH', 7, 1) +
b'\x00' * 8))
source.send(bytearray(b'\xA2' + struct.pack('>IH', 9, 1) + b'\xCC'))
yield clk.posedge
yield input_axis_tvalid.negedge
yield delay(100)
yield clk.posedge
data = wb_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(7, 3) == b'\xAA\xBB\xCC'
rx_data = bytearray(sink.read())
print(repr(rx_data))
assert rx_data == b'\xA4' + struct.pack(
'>IH', 7,
1) + b'\xA4' + struct.pack('>IH', 8, 1) + b'\xA3' + struct.pack(
'>IH', 7, 1) + b'\xAA' + b'\xA4' + struct.pack('>IH', 9, 1)
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
ADDR_WIDTH = 32
WBM_DATA_WIDTH = 8
WBM_SELECT_WIDTH = 1
WBS_DATA_WIDTH = 32
WBS_SELECT_WIDTH = 4
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
wbm_adr_i = Signal(intbv(0)[ADDR_WIDTH:])
wbm_dat_i = Signal(intbv(0)[WBM_DATA_WIDTH:])
wbm_we_i = Signal(bool(0))
wbm_sel_i = Signal(intbv(0)[WBM_SELECT_WIDTH:])
wbm_stb_i = Signal(bool(0))
wbm_cyc_i = Signal(bool(0))
wbs_dat_i = Signal(intbv(0)[WBS_DATA_WIDTH:])
wbs_ack_i = Signal(bool(0))
wbs_err_i = Signal(bool(0))
wbs_rty_i = Signal(bool(0))
# Outputs
wbm_dat_o = Signal(intbv(0)[WBM_DATA_WIDTH:])
wbm_ack_o = Signal(bool(0))
wbm_err_o = Signal(bool(0))
wbm_rty_o = Signal(bool(0))
wbs_adr_o = Signal(intbv(0)[ADDR_WIDTH:])
wbs_dat_o = Signal(intbv(0)[WBS_DATA_WIDTH:])
wbs_we_o = Signal(bool(0))
wbs_sel_o = Signal(intbv(0)[WBS_SELECT_WIDTH:])
wbs_stb_o = Signal(bool(0))
wbs_cyc_o = Signal(bool(0))
# WB master
wbm_inst = wb.WBMaster()
wbm_logic = wbm_inst.create_logic(clk,
adr_o=wbm_adr_i,
dat_i=wbm_dat_o,
dat_o=wbm_dat_i,
we_o=wbm_we_i,
sel_o=wbm_sel_i,
stb_o=wbm_stb_i,
ack_i=wbm_ack_o,
cyc_o=wbm_cyc_i,
name='master')
# WB RAM model
wb_ram_inst = wb.WBRam(2**16)
wb_ram_port0 = wb_ram_inst.create_port(clk,
adr_i=wbs_adr_o,
dat_i=wbs_dat_o,
dat_o=wbs_dat_i,
we_i=wbs_we_o,
sel_i=wbs_sel_o,
stb_i=wbs_stb_o,
ack_o=wbs_ack_i,
cyc_i=wbs_cyc_o,
latency=1,
asynchronous=False,
name='slave')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
wbm_adr_i=wbm_adr_i,
wbm_dat_i=wbm_dat_i,
wbm_dat_o=wbm_dat_o,
wbm_we_i=wbm_we_i,
wbm_sel_i=wbm_sel_i,
wbm_stb_i=wbm_stb_i,
wbm_ack_o=wbm_ack_o,
wbm_err_o=wbm_err_o,
wbm_rty_o=wbm_rty_o,
wbm_cyc_i=wbm_cyc_i,
wbs_adr_o=wbs_adr_o,
wbs_dat_i=wbs_dat_i,
wbs_dat_o=wbs_dat_o,
wbs_we_o=wbs_we_o,
wbs_sel_o=wbs_sel_o,
wbs_stb_o=wbs_stb_o,
wbs_ack_i=wbs_ack_i,
wbs_err_i=wbs_err_i,
wbs_rty_i=wbs_rty_i,
wbs_cyc_o=wbs_cyc_o)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
print("test 1: write")
current_test.next = 1
wbm_inst.init_write(4, b'\x11\x22\x33\x44')
yield wbm_inst.wait()
yield clk.posedge
data = wb_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(4, 4) == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 2: read")
current_test.next = 2
wbm_inst.init_read(4, 4)
yield wbm_inst.wait()
yield clk.posedge
data = wbm_inst.get_read_data()
assert data[0] == 4
assert data[1] == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 3: various writes")
current_test.next = 3
for length in range(1, 8):
for offset in range(4, 8):
wb_ram_inst.write_mem(256 * (16 * offset + length),
b'\xAA' * 16)
wbm_inst.init_write(
256 * (16 * offset + length) + offset,
b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length])
yield wbm_inst.wait()
yield clk.posedge
data = wb_ram_inst.read_mem(256 * (16 * offset + length), 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(
256 * (16 * offset + length) + offset,
length) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
assert wb_ram_inst.read_mem(
256 * (16 * offset + length) + offset - 1, 1) == b'\xAA'
assert wb_ram_inst.read_mem(
256 * (16 * offset + length) + offset + length,
1) == b'\xAA'
yield delay(100)
yield clk.posedge
print("test 4: various reads")
current_test.next = 4
for length in range(1, 8):
for offset in range(4, 8):
wbm_inst.init_read(256 * (16 * offset + length) + offset,
length)
yield wbm_inst.wait()
yield clk.posedge
data = wbm_inst.get_read_data()
assert data[0] == 256 * (16 * offset + length) + offset
assert data[1] == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
port0_adr_i = Signal(intbv(0)[32:])
port0_dat_i = Signal(intbv(0)[32:])
port0_we_i = Signal(bool(0))
port0_sel_i = Signal(intbv(0)[4:])
port0_stb_i = Signal(bool(0))
port0_cyc_i = Signal(bool(0))
# Outputs
port0_dat_o = Signal(intbv(0)[32:])
port0_ack_o = Signal(bool(0))
# WB master
wb_master_inst = wb.WBMaster()
wb_master_logic = wb_master_inst.create_logic(clk,
adr_o=port0_adr_i,
dat_i=port0_dat_o,
dat_o=port0_dat_i,
we_o=port0_we_i,
sel_o=port0_sel_i,
stb_o=port0_stb_i,
ack_i=port0_ack_o,
cyc_o=port0_cyc_i,
name='master')
# WB RAM model
wb_ram_inst = wb.WBRam(2**16)
wb_ram_port0 = wb_ram_inst.create_port(clk,
adr_i=port0_adr_i,
dat_i=port0_dat_i,
dat_o=port0_dat_o,
we_i=port0_we_i,
sel_i=port0_sel_i,
stb_i=port0_stb_i,
ack_o=port0_ack_o,
cyc_i=port0_cyc_i,
latency=1,
asynchronous=False,
name='port0')
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
print("test 1: baseline")
current_test.next = 1
data = wb_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
yield delay(100)
yield clk.posedge
print("test 2: direct write")
current_test.next = 2
wb_ram_inst.write_mem(0, b'test')
data = wb_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(0, 4) == b'test'
yield clk.posedge
print("test 3: write via port0")
current_test.next = 3
wb_master_inst.init_write(4, b'\x11\x22\x33\x44')
yield wb_master_inst.wait()
yield clk.posedge
data = wb_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(4, 4) == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 4: read via port0")
current_test.next = 4
wb_master_inst.init_read(4, 4)
yield wb_master_inst.wait()
yield clk.posedge
data = wb_master_inst.get_read_data()
assert data[0] == 4
assert data[1] == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 5: various writes")
current_test.next = 5
for length in range(1, 8):
for offset in range(4, 8):
wb_ram_inst.write_mem(256 * (16 * offset + length),
b'\xAA' * 32)
wb_master_inst.init_write(
256 * (16 * offset + length) + offset,
b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length])
yield wb_master_inst.wait()
yield clk.posedge
data = wb_ram_inst.read_mem(256 * (16 * offset + length), 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(
256 * (16 * offset + length) + offset,
length) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
assert wb_ram_inst.read_mem(
256 * (16 * offset + length) + offset - 1, 1) == b'\xAA'
assert wb_ram_inst.read_mem(
256 * (16 * offset + length) + offset + length,
1) == b'\xAA'
yield delay(100)
yield clk.posedge
print("test 6: various reads")
current_test.next = 6
for length in range(1, 8):
for offset in range(4, 8):
wb_master_inst.init_read(256 * (16 * offset + length) + offset,
length)
yield wb_master_inst.wait()
yield clk.posedge
data = wb_master_inst.get_read_data()
assert data[0] == 256 * (16 * offset + length) + offset
assert data[1] == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
yield delay(100)
yield clk.posedge
print("test 7: write words")
current_test.next = 7
for offset in range(4):
wb_master_inst.init_write_words(
(0x4000 + offset * 64 + 0) / 2 + offset, [0x1234])
wb_master_inst.init_write_dwords(
(0x4000 + offset * 64 + 16) / 4 + offset, [0x12345678])
wb_master_inst.init_write_qwords(
(0x4000 + offset * 64 + 32) / 8 + offset, [0x1234567887654321])
yield wb_master_inst.wait()
yield clk.posedge
data = wb_ram_inst.read_mem(0x4000 + offset * 64, 64)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(
(0x4000 + offset * 64 + 0) + offset * 2, 2) == b'\x34\x12'
assert wb_ram_inst.read_mem(
(0x4000 + offset * 64 + 16) + offset * 4,
4) == b'\x78\x56\x34\x12'
assert wb_ram_inst.read_mem(
(0x4000 + offset * 64 + 32) + offset * 8,
8) == b'\x21\x43\x65\x87\x78\x56\x34\x12'
assert wb_ram_inst.read_words(
(0x4000 + offset * 64 + 0) / 2 + offset, 1)[0] == 0x1234
assert wb_ram_inst.read_dwords(
(0x4000 + offset * 64 + 16) / 4 + offset, 1)[0] == 0x12345678
assert wb_ram_inst.read_qwords(
(0x4000 + offset * 64 + 32) / 8 + offset,
1)[0] == 0x1234567887654321
yield delay(100)
yield clk.posedge
print("test 8: read words")
current_test.next = 8
for offset in range(4):
wb_master_inst.init_read_words(
(0x4000 + offset * 64 + 0) / 2 + offset, 1)
wb_master_inst.init_read_dwords(
(0x4000 + offset * 64 + 16) / 4 + offset, 1)
wb_master_inst.init_read_qwords(
(0x4000 + offset * 64 + 32) / 8 + offset, 1)
yield wb_master_inst.wait()
yield clk.posedge
data = wb_master_inst.get_read_data_words()
assert data[0] == (0x4000 + offset * 64 + 0) / 2 + offset
assert data[1][0] == 0x1234
data = wb_master_inst.get_read_data_dwords()
assert data[0] == (0x4000 + offset * 64 + 16) / 4 + offset
assert data[1][0] == 0x12345678
data = wb_master_inst.get_read_data_qwords()
assert data[0] == (0x4000 + offset * 64 + 32) / 8 + offset
assert data[1][0] == 0x1234567887654321
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[8:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
output_axis_tready = Signal(bool(0))
wb_dat_i = Signal(intbv(0)[8:])
wb_ack_i = Signal(bool(0))
wb_err_i = Signal(bool(0))
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[8:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
wb_adr_o = Signal(intbv(0)[36:])
wb_dat_o = Signal(intbv(0)[8:])
wb_we_o = Signal(bool(0))
wb_stb_o = Signal(bool(0))
wb_cyc_o = Signal(bool(0))
busy = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
fifo=source_queue,
pause=source_pause,
name='source')
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
fifo=sink_queue,
pause=sink_pause,
name='sink')
# WB RAM model
wb_ram_inst = wb.WBRam(2**16)
wb_ram_port0 = wb_ram_inst.create_port(clk,
adr_i=wb_adr_o,
dat_i=wb_dat_o,
dat_o=wb_dat_i,
we_i=wb_we_o,
stb_i=wb_stb_o,
ack_o=wb_ack_i,
cyc_i=wb_cyc_o,
latency=1,
async=False,
name='wb_ram')
# DUT
dut = dut_soc_interface_8(clk, rst, current_test, input_axis_tdata,
input_axis_tvalid, input_axis_tready,
input_axis_tlast, output_axis_tdata,
output_axis_tvalid, output_axis_tready,
output_axis_tlast, wb_adr_o, wb_dat_i, wb_dat_o,
wb_we_o, wb_stb_o, wb_ack_i, wb_err_i, wb_cyc_o,
busy)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
yield clk.posedge
print("test 1: Write to bank 0")
current_test.next = 1
test_frame = bytearray('\xB0\x00\x00\x00\x00\xAA')
source_queue.put(test_frame)
yield clk.posedge
yield busy.negedge
yield clk.posedge
yield clk.posedge
data = wb_ram_inst.read_mem(0, 1)
assert data == '\xAA'
yield delay(100)
yield clk.posedge
print("test 2: Longer write to bank 0")
current_test.next = 2
test_frame = bytearray(
'\xB0\x00\x00\x00\x20\x11\x22\x33\x44\x55\x66\x77')
source_queue.put(test_frame)
yield clk.posedge
yield busy.negedge
yield clk.posedge
yield clk.posedge
data = wb_ram_inst.read_mem(32, 7)
assert data == '\x11\x22\x33\x44\x55\x66\x77'
yield delay(100)
yield clk.posedge
print("test 3: Read from bank 0")
current_test.next = 3
test_frame = bytearray('\xA0\x00\x00\x00\x00' + '\x00' * 8)
source_queue.put(test_frame)
yield clk.posedge
yield busy.negedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = bytearray(sink_queue.get())
assert rx_frame.find('\x01\xAA') >= 0
yield delay(100)
yield clk.posedge
print("test 4: Longer read from bank 0")
current_test.next = 4
test_frame = bytearray('\xA0\x00\x00\x00\x20' + '\x00' * 30)
source_queue.put(test_frame)
yield clk.posedge
yield busy.negedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = bytearray(sink_queue.get())
print(repr(rx_frame))
assert rx_frame.find('\x01\x11\x22\x33\x44\x55\x66\x77') >= 0
yield delay(100)
yield clk.posedge
print("test 5: Write to bank 0, source pause")
current_test.next = 5
test_frame = bytearray(
'\xB0\x00\x00\x00\x20\x11\x22\x33\x44\x55\x66\x77')
source_queue.put(test_frame)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
data = wb_ram_inst.read_mem(32, 7)
assert data == '\x11\x22\x33\x44\x55\x66\x77'
yield delay(100)
yield clk.posedge
print("test 6: Read from bank 0, source pause")
current_test.next = 6
test_frame = bytearray('\xA0\x00\x00\x00\x20' + '\x00' * 10)
source_queue.put(test_frame)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = bytearray(sink_queue.get())
assert rx_frame.find('\x01\x11\x22\x33\x44\x55\x66\x77') >= 0
yield delay(100)
yield clk.posedge
print("test 7: Read from bank 0, sink pause")
current_test.next = 7
test_frame = bytearray('\xA0\x00\x00\x00\x20' + '\x00' * 40)
source_queue.put(test_frame)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = bytearray(sink_queue.get())
print(repr(rx_frame))
assert rx_frame.find('\x01\x11\x22\x33\x44\x55\x66\x77') >= 0
yield delay(100)
yield clk.posedge
print("test 8: Write to bank 1")
current_test.next = 8
test_frame = bytearray('\xB1\x00\x00\x01\x00\x11')
source_queue.put(test_frame)
yield clk.posedge
yield busy.negedge
yield clk.posedge
yield clk.posedge
data = wb_ram_inst.read_mem(256, 1)
assert data == '\x11'
yield delay(100)
yield clk.posedge
print("test 9: Longer write to bank 1")
current_test.next = 9
test_frame = bytearray(
'\xB1\x00\x00\x01\x20\xAA\xBB\xCC\xDD\xEE\xFF\x77')
source_queue.put(test_frame)
yield clk.posedge
yield busy.negedge
yield clk.posedge
yield clk.posedge
data = wb_ram_inst.read_mem(288, 7)
assert data == '\xAA\xBB\xCC\xDD\xEE\xFF\x77'
yield delay(100)
yield clk.posedge
print("test 10: Read from bank 1")
current_test.next = 10
test_frame = bytearray('\xA1\x00\x00\x01\x00' + '\x00' * 8)
source_queue.put(test_frame)
yield clk.posedge
yield busy.negedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = bytearray(sink_queue.get())
assert rx_frame.find('\x01\x11') >= 0
yield delay(100)
yield clk.posedge
print("test 11: Longer read from bank 1")
current_test.next = 11
test_frame = bytearray('\xA1\x00\x00\x01\x20' + '\x00' * 30)
source_queue.put(test_frame)
yield clk.posedge
yield busy.negedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = bytearray(sink_queue.get())
assert rx_frame.find('\x01\xAA\xBB\xCC\xDD\xEE\xFF\x77') >= 0
yield delay(100)
raise StopSimulation
return dut, source, sink, wb_ram_port0, clkgen, check
def bench():
# Parameters
IMPLICIT_FRAMING = 0
COUNT_SIZE = 16
AXIS_DATA_WIDTH = 8
AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH / 8)
WB_DATA_WIDTH = 32
WB_ADDR_WIDTH = 31
WB_SELECT_WIDTH = 2
READ_REQ = 0xA1
WRITE_REQ = 0xA2
READ_RESP = 0xA3
WRITE_RESP = 0xA4
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(1)[AXIS_KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
output_axis_tready = Signal(bool(0))
wb_dat_i = Signal(intbv(0)[WB_DATA_WIDTH:])
wb_ack_i = Signal(bool(0))
wb_err_i = Signal(bool(0))
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(1)[AXIS_KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
wb_adr_o = Signal(intbv(0)[WB_ADDR_WIDTH:])
wb_dat_o = Signal(intbv(0)[WB_DATA_WIDTH:])
wb_we_o = Signal(bool(0))
wb_sel_o = Signal(intbv(0)[WB_SELECT_WIDTH:])
wb_stb_o = Signal(bool(0))
wb_cyc_o = Signal(bool(0))
busy = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
# WB RAM model
wb_ram_inst = wb.WBRam(2**16)
wb_ram_port0 = wb_ram_inst.create_port(clk,
adr_i=wb_adr_o,
dat_i=wb_dat_o,
dat_o=wb_dat_i,
we_i=wb_we_o,
sel_i=wb_sel_o,
stb_i=wb_stb_o,
ack_o=wb_ack_i,
cyc_i=wb_cyc_o,
latency=1,
async=False,
name='port0')
# DUT
dut = dut_axis_wb_master(
clk, rst, current_test, input_axis_tdata, input_axis_tkeep,
input_axis_tvalid, input_axis_tready, input_axis_tlast,
input_axis_tuser, output_axis_tdata, output_axis_tkeep,
output_axis_tvalid, output_axis_tready, output_axis_tlast,
output_axis_tuser, wb_adr_o, wb_dat_i, wb_dat_o, wb_we_o, wb_sel_o,
wb_stb_o, wb_ack_i, wb_err_i, wb_cyc_o, busy)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: test write")
current_test.next = 1
source_queue.put(
bytearray(b'\xA2' + struct.pack('>IH', 0, 4) +
b'\x11\x22\x33\x44'))
yield clk.posedge
yield input_axis_tvalid.negedge
yield delay(100)
yield clk.posedge
data = wb_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(0, 4) == b'\x11\x22\x33\x44'
rx_data = b''
while not sink_queue.empty():
rx_data += bytearray(sink_queue.get())
print(repr(rx_data))
assert rx_data == b'\xA4' + struct.pack('>IH', 0, 4)
yield delay(100)
yield clk.posedge
print("test 2: test read")
current_test.next = 2
source_queue.put(bytearray(b'\xA1' + struct.pack('>IH', 0, 4)))
yield clk.posedge
yield input_axis_tvalid.negedge
yield delay(100)
yield clk.posedge
rx_data = b''
while not sink_queue.empty():
rx_data += bytearray(sink_queue.get())
print(repr(rx_data))
assert rx_data == b'\xA3' + struct.pack('>IH', 0,
4) + b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 3: various writes")
current_test.next = 3
for length in range(1, 8):
for offset in range(4):
source_queue.put(
bytearray(
b'\xA2' +
struct.pack('>IH', 256 *
(16 * offset + length) + offset, length) +
b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]))
yield clk.posedge
yield input_axis_tvalid.negedge
yield delay(200)
yield clk.posedge
data = wb_ram_inst.read_mem(256 * (16 * offset + length), 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(
256 * (16 * offset + length) + offset,
length) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
rx_data = b''
while not sink_queue.empty():
rx_data += bytearray(sink_queue.get())
print(repr(rx_data))
assert rx_data == b'\xA4' + struct.pack(
'>IH', 256 * (16 * offset + length) + offset, length)
yield delay(100)
yield clk.posedge
print("test 4: various reads")
current_test.next = 4
for length in range(1, 8):
for offset in range(4):
source_queue.put(
bytearray(
b'\xA1' +
struct.pack('>IH', 256 *
(16 * offset + length) + offset, length)))
yield clk.posedge
yield input_axis_tvalid.negedge
yield delay(200)
yield clk.posedge
rx_data = b''
while not sink_queue.empty():
rx_data += bytearray(sink_queue.get())
print(repr(rx_data))
assert rx_data == b'\xA3' + struct.pack(
'>IH', 256 * (16 * offset + length) + offset,
length) + b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
yield delay(100)
yield clk.posedge
print("test 5: test leading padding")
current_test.next = 5
source_queue.put(
bytearray(b'\xA2' + struct.pack('>IH', 4, 2) + b'\xAA\xBB'))
source_queue.put(
bytearray(b'\x00' * 8 + b'\xA2' + struct.pack('>IH', 6, 2) +
b'\xCC\xDD'))
source_queue.put(
bytearray(b'\x00' * 8 + b'\xA1' + struct.pack('>IH', 4, 2)))
source_queue.put(
bytearray(b'\xA2' + struct.pack('>IH', 8, 2) + b'\xEE\xFF'))
yield clk.posedge
yield input_axis_tvalid.negedge
yield delay(100)
yield clk.posedge
data = wb_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(4, 6) == b'\xAA\xBB\x00\x00\xEE\xFF'
rx_data = b''
while not sink_queue.empty():
rx_data += bytearray(sink_queue.get())
print(repr(rx_data))
assert rx_data == b'\xA4' + struct.pack(
'>IH', 4, 2) + b'\xA4' + struct.pack('>IH', 8, 2)
yield delay(100)
yield clk.posedge
print("test 6: test trailing padding")
current_test.next = 6
source_queue.put(
bytearray(b'\xA2' + struct.pack('>IH', 10, 2) + b'\xAA\xBB'))
source_queue.put(
bytearray(b'\xA2' + struct.pack('>IH', 12, 2) + b'\xCC\xDD' +
b'\x00' * 8))
source_queue.put(
bytearray(b'\xA1' + struct.pack('>IH', 10, 2) + b'\x00' * 8))
source_queue.put(
bytearray(b'\xA1' + struct.pack('>IH', 10, 2) + b'\x00' * 1))
source_queue.put(
bytearray(b'\xA2' + struct.pack('>IH', 14, 2) + b'\xEE\xFF'))
yield clk.posedge
yield input_axis_tvalid.negedge
yield delay(100)
yield clk.posedge
data = wb_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(10, 6) == b'\xAA\xBB\xCC\xDD\xEE\xFF'
rx_data = b''
while not sink_queue.empty():
rx_data += bytearray(sink_queue.get())
print(repr(rx_data))
assert rx_data == b'\xA4'+struct.pack('>IH', 10, 2)+\
b'\xA4'+struct.pack('>IH', 12, 2)+\
b'\xA3'+struct.pack('>IH', 10, 2)+b'\xAA\xBB'+\
b'\xA3'+struct.pack('>IH', 10, 2)+b'\xAA\xBB'+\
b'\xA4'+struct.pack('>IH', 14, 2)
yield delay(100)
raise StopSimulation
return dut, clkgen, source, sink, wb_ram_port0, check
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
port0_adr_i = Signal(intbv(0)[32:])
port0_dat_i = Signal(intbv(0)[32:])
port0_we_i = Signal(bool(0))
port0_sel_i = Signal(intbv(0)[4:])
port0_stb_i = Signal(bool(0))
port0_cyc_i = Signal(bool(0))
# Outputs
port0_dat_o = Signal(intbv(0)[32:])
port0_ack_o = Signal(bool(0))
# WB RAM model
wb_ram_inst = wb.WBRam(2**16)
wb_ram_port0 = wb_ram_inst.create_port(clk,
adr_i=port0_adr_i,
dat_i=port0_dat_i,
dat_o=port0_dat_o,
we_i=port0_we_i,
sel_i=port0_sel_i,
stb_i=port0_stb_i,
ack_o=port0_ack_o,
cyc_i=port0_cyc_i,
latency=1,
async=False,
name='port0')
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
print("test 1: baseline")
current_test.next = 1
data = wb_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
yield delay(100)
yield clk.posedge
print("test 2: direct write")
current_test.next = 2
wb_ram_inst.write_mem(0, b'test')
data = wb_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(0, 4) == b'test'
yield delay(100)
yield clk.posedge
print("test 2: write via port0")
current_test.next = 2
yield clk.posedge
port0_adr_i.next = 4
port0_dat_i.next = 0x44332211
port0_sel_i.next = 0xF
port0_we_i.next = 1
port0_cyc_i.next = 1
port0_stb_i.next = 1
yield port0_ack_o.posedge
yield clk.posedge
port0_we_i.next = 0
port0_cyc_i.next = 0
port0_stb_i.next = 0
yield clk.posedge
yield clk.posedge
data = wb_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(4, 4) == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 3: read via port0")
current_test.next = 3
yield clk.posedge
port0_adr_i.next = 4
port0_we_i.next = 0
port0_cyc_i.next = 1
port0_stb_i.next = 1
yield port0_ack_o.posedge
yield clk.posedge
port0_we_i.next = 0
port0_cyc_i.next = 0
port0_stb_i.next = 0
assert port0_dat_o == 0x44332211
yield delay(100)
yield clk.posedge
print("test 4: various writes")
current_test.next = 4
for length in range(1, 8):
for offset in range(4):
yield clk.posedge
sel_start = ((2**(4) - 1) << offset % 4) & (2**(4) - 1)
sel_end = ((2**(4) - 1) >>
(4 - (((offset + int(length / 1) - 1) % 4) + 1)))
cycles = int((length + 4 - 1 + (offset % 4)) / 4)
i = 1
port0_cyc_i.next = 1
port0_stb_i.next = 1
port0_we_i.next = 1
port0_adr_i.next = 256 * (16 * offset + length)
val = 0
for j in range(4):
if j >= offset % 4 and (cycles > 1 or j < ((
(offset + int(length / 1) - 1) % 4) + 1)):
val |= (0x11 * i) << j * 8
i += 1
port0_dat_i.next = val
if cycles == 1:
port0_sel_i.next = sel_start & sel_end
else:
port0_sel_i.next = sel_start
yield clk.posedge
while not port0_ack_o:
yield clk.posedge
port0_we_i.next = 0
port0_stb_i.next = 0
for k in range(1, cycles - 1):
yield clk.posedge
port0_stb_i.next = 1
port0_we_i.next = 1
port0_adr_i.next = 256 * (16 * offset + length) + 4 * k
val = 0
for j in range(4):
val |= (0x11 * i) << j * 8
i += 1
port0_dat_i.next = val
port0_sel_i.next = 2**(4) - 1
yield clk.posedge
while not port0_ack_o:
yield clk.posedge
port0_we_i.next = 0
port0_stb_i.next = 0
if cycles > 1:
yield clk.posedge
port0_stb_i.next = 1
port0_we_i.next = 1
port0_adr_i.next = 256 * (16 * offset +
length) + 4 * (cycles - 1)
val = 0
for j in range(4):
if j < (((offset + int(length / 1) - 1) % 4) + 1):
val |= (0x11 * i) << j * 8
i += 1
port0_dat_i.next = val
port0_sel_i.next = sel_end
yield clk.posedge
while not port0_ack_o:
yield clk.posedge
port0_we_i.next = 0
port0_stb_i.next = 0
port0_we_i.next = 0
port0_stb_i.next = 0
port0_cyc_i.next = 0
yield clk.posedge
yield clk.posedge
data = wb_ram_inst.read_mem(256 * (16 * offset + length), 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(
256 * (16 * offset + length) + offset,
length) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
yield delay(100)
raise StopSimulation
return wb_ram_port0, clkgen, check
def bench():
# Parameters
DATA_WIDTH = 32
ADDR_WIDTH = 32
SELECT_WIDTH = (DATA_WIDTH / 8)
ARB_TYPE = "PRIORITY"
LSB_PRIORITY = "HIGH"
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
wbm0_adr_i = Signal(intbv(0)[ADDR_WIDTH:])
wbm0_dat_i = Signal(intbv(0)[DATA_WIDTH:])
wbm0_we_i = Signal(bool(0))
wbm0_sel_i = Signal(intbv(0)[SELECT_WIDTH:])
wbm0_stb_i = Signal(bool(0))
wbm0_cyc_i = Signal(bool(0))
wbm1_adr_i = Signal(intbv(0)[ADDR_WIDTH:])
wbm1_dat_i = Signal(intbv(0)[DATA_WIDTH:])
wbm1_we_i = Signal(bool(0))
wbm1_sel_i = Signal(intbv(0)[SELECT_WIDTH:])
wbm1_stb_i = Signal(bool(0))
wbm1_cyc_i = Signal(bool(0))
wbs_dat_i = Signal(intbv(0)[DATA_WIDTH:])
wbs_ack_i = Signal(bool(0))
wbs_err_i = Signal(bool(0))
wbs_rty_i = Signal(bool(0))
# Outputs
wbm0_dat_o = Signal(intbv(0)[DATA_WIDTH:])
wbm0_ack_o = Signal(bool(0))
wbm0_err_o = Signal(bool(0))
wbm0_rty_o = Signal(bool(0))
wbm1_dat_o = Signal(intbv(0)[DATA_WIDTH:])
wbm1_ack_o = Signal(bool(0))
wbm1_err_o = Signal(bool(0))
wbm1_rty_o = Signal(bool(0))
wbs_adr_o = Signal(intbv(0)[ADDR_WIDTH:])
wbs_dat_o = Signal(intbv(0)[DATA_WIDTH:])
wbs_we_o = Signal(bool(0))
wbs_sel_o = Signal(intbv(0)[SELECT_WIDTH:])
wbs_stb_o = Signal(bool(0))
wbs_cyc_o = Signal(bool(0))
# WB master
wbm0_inst = wb.WBMaster()
wbm0_logic = wbm0_inst.create_logic(clk,
adr_o=wbm0_adr_i,
dat_i=wbm0_dat_o,
dat_o=wbm0_dat_i,
we_o=wbm0_we_i,
sel_o=wbm0_sel_i,
stb_o=wbm0_stb_i,
ack_i=wbm0_ack_o,
cyc_o=wbm0_cyc_i,
name='master0')
# WB master
wbm1_inst = wb.WBMaster()
wbm1_logic = wbm1_inst.create_logic(clk,
adr_o=wbm1_adr_i,
dat_i=wbm1_dat_o,
dat_o=wbm1_dat_i,
we_o=wbm1_we_i,
sel_o=wbm1_sel_i,
stb_o=wbm1_stb_i,
ack_i=wbm1_ack_o,
cyc_o=wbm1_cyc_i,
name='master1')
# WB RAM model
wb_ram_inst = wb.WBRam(2**16)
wb_ram_port0 = wb_ram_inst.create_port(clk,
adr_i=wbs_adr_o,
dat_i=wbs_dat_o,
dat_o=wbs_dat_i,
we_i=wbs_we_o,
sel_i=wbs_sel_o,
stb_i=wbs_stb_o,
ack_o=wbs_ack_i,
cyc_i=wbs_cyc_o,
latency=1,
asynchronous=False,
name='slave')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
wbm0_adr_i=wbm0_adr_i,
wbm0_dat_i=wbm0_dat_i,
wbm0_dat_o=wbm0_dat_o,
wbm0_we_i=wbm0_we_i,
wbm0_sel_i=wbm0_sel_i,
wbm0_stb_i=wbm0_stb_i,
wbm0_ack_o=wbm0_ack_o,
wbm0_err_o=wbm0_err_o,
wbm0_rty_o=wbm0_rty_o,
wbm0_cyc_i=wbm0_cyc_i,
wbm1_adr_i=wbm1_adr_i,
wbm1_dat_i=wbm1_dat_i,
wbm1_dat_o=wbm1_dat_o,
wbm1_we_i=wbm1_we_i,
wbm1_sel_i=wbm1_sel_i,
wbm1_stb_i=wbm1_stb_i,
wbm1_ack_o=wbm1_ack_o,
wbm1_err_o=wbm1_err_o,
wbm1_rty_o=wbm1_rty_o,
wbm1_cyc_i=wbm1_cyc_i,
wbs_adr_o=wbs_adr_o,
wbs_dat_i=wbs_dat_i,
wbs_dat_o=wbs_dat_o,
wbs_we_o=wbs_we_o,
wbs_sel_o=wbs_sel_o,
wbs_stb_o=wbs_stb_o,
wbs_ack_i=wbs_ack_i,
wbs_err_i=wbs_err_i,
wbs_rty_i=wbs_rty_i,
wbs_cyc_o=wbs_cyc_o)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: master 0")
current_test.next = 1
wbm0_inst.init_write(0x00000000, b'\x11\x22\x33\x44')
yield wbm0_inst.wait()
yield clk.posedge
data = wb_ram_inst.read_mem(0x00000000, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(0, 4) == b'\x11\x22\x33\x44'
wbm0_inst.init_read(0x00000000, 4)
yield wbm0_inst.wait()
yield clk.posedge
data = wbm0_inst.get_read_data()
assert data[0] == 0x00000000
assert data[1] == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 2: master 1")
current_test.next = 2
wbm1_inst.init_write(0x00001000, b'\x11\x22\x33\x44')
yield wbm1_inst.wait()
yield clk.posedge
data = wb_ram_inst.read_mem(0x00001000, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(0, 4) == b'\x11\x22\x33\x44'
wbm1_inst.init_read(0x00001000, 4)
yield wbm0_inst.wait()
yield wbm1_inst.wait()
yield clk.posedge
data = wbm1_inst.get_read_data()
assert data[0] == 0x00001000
assert data[1] == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 3: arbitration")
current_test.next = 3
wbm0_inst.init_write(0x00000010, bytearray(range(16)))
wbm0_inst.init_write(0x00000020, bytearray(range(16)))
wbm1_inst.init_write(0x00001010, bytearray(range(16)))
wbm1_inst.init_write(0x00001020, bytearray(range(16)))
yield wbm1_inst.wait()
yield clk.posedge
data = wb_ram_inst.read_mem(0x00000010, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
data = wb_ram_inst.read_mem(0x00001010, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(0, 4) == b'\x11\x22\x33\x44'
wbm0_inst.init_read(0x00000010, 16)
wbm0_inst.init_read(0x00000020, 16)
wbm1_inst.init_read(0x00001010, 16)
wbm1_inst.init_read(0x00001020, 16)
yield wbm0_inst.wait()
yield wbm1_inst.wait()
yield clk.posedge
data = wbm0_inst.get_read_data()
assert data[0] == 0x00000010
assert data[1] == bytearray(range(16))
data = wbm0_inst.get_read_data()
assert data[0] == 0x00000020
assert data[1] == bytearray(range(16))
data = wbm1_inst.get_read_data()
assert data[0] == 0x00001010
assert data[1] == bytearray(range(16))
data = wbm1_inst.get_read_data()
assert data[0] == 0x00001020
assert data[1] == bytearray(range(16))
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
port0_adr_i = Signal(intbv(0)[32:])
port0_dat_i = Signal(intbv(0)[32:])
port0_we_i = Signal(bool(0))
port0_sel_i = Signal(intbv(0)[4:])
port0_stb_i = Signal(bool(0))
port0_cyc_i = Signal(bool(0))
# Outputs
port0_dat_o = Signal(intbv(0)[32:])
port0_ack_o = Signal(bool(0))
# WB master
wb_master_inst = wb.WBMaster()
wb_master_logic = wb_master_inst.create_logic(clk,
adr_o=port0_adr_i,
dat_i=port0_dat_o,
dat_o=port0_dat_i,
we_o=port0_we_i,
sel_o=port0_sel_i,
stb_o=port0_stb_i,
ack_i=port0_ack_o,
cyc_o=port0_cyc_i,
name='master')
# WB RAM model
wb_ram_inst = wb.WBRam(2**16)
wb_ram_port0 = wb_ram_inst.create_port(clk,
adr_i=port0_adr_i,
dat_i=port0_dat_i,
dat_o=port0_dat_o,
we_i=port0_we_i,
sel_i=port0_sel_i,
stb_i=port0_stb_i,
ack_o=port0_ack_o,
cyc_i=port0_cyc_i,
latency=1,
async=False,
name='port0')
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
print("test 1: baseline")
current_test.next = 1
data = wb_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
yield delay(100)
yield clk.posedge
print("test 2: direct write")
current_test.next = 2
wb_ram_inst.write_mem(0, b'test')
data = wb_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(0, 4) == b'test'
yield clk.posedge
print("test 3: write via port0")
current_test.next = 3
wb_master_inst.init_write(4, b'\x11\x22\x33\x44')
yield wb_master_inst.wait()
yield clk.posedge
data = wb_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(4, 4) == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 4: read via port0")
current_test.next = 4
wb_master_inst.init_read(4, 4)
yield wb_master_inst.wait()
yield clk.posedge
data = wb_master_inst.get_read_data()
assert data[0] == 4
assert data[1] == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 5: various writes")
current_test.next = 5
for length in range(1, 8):
for offset in range(4):
wb_master_inst.init_write(
256 * (16 * offset + length) + offset,
b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length])
yield wb_master_inst.wait()
yield clk.posedge
data = wb_ram_inst.read_mem(256 * (16 * offset + length), 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(
256 * (16 * offset + length) + offset,
length) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
yield delay(100)
yield clk.posedge
print("test 6: various reads")
current_test.next = 6
for length in range(1, 8):
for offset in range(4):
wb_master_inst.init_read(256 * (16 * offset + length) + offset,
length)
yield wb_master_inst.wait()
yield clk.posedge
data = wb_master_inst.get_read_data()
assert data[0] == 256 * (16 * offset + length) + offset
assert data[1] == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
yield delay(100)
raise StopSimulation
return wb_master_logic, wb_ram_port0, clkgen, check
def bench():
# Parameters
DATA_WIDTH = 32
ADDR_WIDTH = 32
SELECT_WIDTH = 4
# Inputs
wbm_clk = Signal(bool(0))
wbm_rst = Signal(bool(0))
wbs_clk = Signal(bool(0))
wbs_rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
wbm_adr_i = Signal(intbv(0)[ADDR_WIDTH:])
wbm_dat_i = Signal(intbv(0)[DATA_WIDTH:])
wbm_we_i = Signal(bool(0))
wbm_sel_i = Signal(intbv(0)[SELECT_WIDTH:])
wbm_stb_i = Signal(bool(0))
wbm_cyc_i = Signal(bool(0))
wbs_dat_i = Signal(intbv(0)[DATA_WIDTH:])
wbs_ack_i = Signal(bool(0))
wbs_err_i = Signal(bool(0))
wbs_rty_i = Signal(bool(0))
# Outputs
wbm_dat_o = Signal(intbv(0)[DATA_WIDTH:])
wbm_ack_o = Signal(bool(0))
wbm_err_o = Signal(bool(0))
wbm_rty_o = Signal(bool(0))
wbs_adr_o = Signal(intbv(0)[ADDR_WIDTH:])
wbs_dat_o = Signal(intbv(0)[DATA_WIDTH:])
wbs_we_o = Signal(bool(0))
wbs_sel_o = Signal(intbv(0)[SELECT_WIDTH:])
wbs_stb_o = Signal(bool(0))
wbs_cyc_o = Signal(bool(0))
# WB master
wbm_inst = wb.WBMaster()
wbm_logic = wbm_inst.create_logic(wbm_clk,
adr_o=wbm_adr_i,
dat_i=wbm_dat_o,
dat_o=wbm_dat_i,
we_o=wbm_we_i,
sel_o=wbm_sel_i,
stb_o=wbm_stb_i,
ack_i=wbm_ack_o,
cyc_o=wbm_cyc_i,
name='master')
# WB RAM model
wb_ram_inst = wb.WBRam(2**16)
wb_ram_port0 = wb_ram_inst.create_port(wbs_clk,
adr_i=wbs_adr_o,
dat_i=wbs_dat_o,
dat_o=wbs_dat_i,
we_i=wbs_we_o,
sel_i=wbs_sel_o,
stb_i=wbs_stb_o,
ack_o=wbs_ack_i,
cyc_i=wbs_cyc_o,
latency=1,
async=False,
name='slave')
# DUT
dut = dut_wb_async_reg(wbm_clk, wbm_rst, wbs_clk, wbs_rst, current_test,
wbm_adr_i, wbm_dat_i, wbm_dat_o, wbm_we_i,
wbm_sel_i, wbm_stb_i, wbm_ack_o, wbm_err_o,
wbm_rty_o, wbm_cyc_i, wbs_adr_o, wbs_dat_i,
wbs_dat_o, wbs_we_o, wbs_sel_o, wbs_stb_o,
wbs_ack_i, wbs_err_i, wbs_rty_i, wbs_cyc_o)
@always(delay(4))
def wbm_clkgen():
wbm_clk.next = not wbm_clk
@always(delay(5))
def wbs_clkgen():
wbs_clk.next = not wbs_clk
@instance
def check():
yield delay(100)
yield wbm_clk.posedge
wbm_rst.next = 1
wbs_rst.next = 1
yield wbm_clk.posedge
yield wbm_clk.posedge
yield wbm_clk.posedge
wbm_rst.next = 0
wbs_rst.next = 0
yield wbm_clk.posedge
yield delay(100)
yield wbm_clk.posedge
yield wbm_clk.posedge
print("test 1: write")
current_test.next = 1
wbm_inst.init_write(4, b'\x11\x22\x33\x44')
yield wbm_inst.wait()
yield wbm_clk.posedge
data = wb_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(4, 4) == b'\x11\x22\x33\x44'
yield delay(100)
yield wbm_clk.posedge
print("test 2: read")
current_test.next = 2
wbm_inst.init_read(4, 4)
yield wbm_inst.wait()
yield wbm_clk.posedge
data = wbm_inst.get_read_data()
assert data[0] == 4
assert data[1] == b'\x11\x22\x33\x44'
yield delay(100)
yield wbm_clk.posedge
print("test 3: various writes")
current_test.next = 3
for length in range(1, 8):
for offset in range(4):
wbm_inst.init_write(
256 * (16 * offset + length) + offset,
b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length])
yield wbm_inst.wait()
yield wbm_clk.posedge
data = wb_ram_inst.read_mem(256 * (16 * offset + length), 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(
256 * (16 * offset + length) + offset,
length) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
yield delay(100)
yield wbm_clk.posedge
print("test 4: various reads")
current_test.next = 4
for length in range(1, 8):
for offset in range(4):
wbm_inst.init_read(256 * (16 * offset + length) + offset,
length)
yield wbm_inst.wait()
yield wbm_clk.posedge
data = wbm_inst.get_read_data()
assert data[0] == 256 * (16 * offset + length) + offset
assert data[1] == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
yield delay(100)
raise StopSimulation
return dut, wbm_logic, wb_ram_port0, wbm_clkgen, wbs_clkgen, check
def bench():
# Parameters
FILTER_LEN = 4
WB_DATA_WIDTH = 32
WB_ADDR_WIDTH = 16
WB_SELECT_WIDTH = WB_DATA_WIDTH / 8
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
i2c_scl_i = Signal(bool(1))
i2c_sda_i = Signal(bool(1))
wb_dat_i = Signal(intbv(0)[WB_DATA_WIDTH:])
wb_ack_i = Signal(bool(0))
wb_err_i = Signal(bool(0))
enable = Signal(bool(0))
device_address = Signal(intbv(0)[7:])
m_scl_i = Signal(bool(1))
m_sda_i = Signal(bool(1))
s2_scl_i = Signal(bool(1))
s2_sda_i = Signal(bool(1))
# Outputs
i2c_scl_o = Signal(bool(1))
i2c_scl_t = Signal(bool(1))
i2c_sda_o = Signal(bool(1))
i2c_sda_t = Signal(bool(1))
wb_adr_o = Signal(intbv(0)[WB_ADDR_WIDTH:])
wb_dat_o = Signal(intbv(0)[WB_DATA_WIDTH:])
wb_we_o = Signal(bool(0))
wb_sel_o = Signal(intbv(0)[WB_SELECT_WIDTH:])
wb_stb_o = Signal(bool(0))
wb_cyc_o = Signal(bool(0))
busy = Signal(bool(0))
bus_addressed = Signal(bool(0))
bus_active = Signal(bool(0))
m_scl_o = Signal(bool(1))
m_scl_t = Signal(bool(1))
m_sda_o = Signal(bool(1))
m_sda_t = Signal(bool(1))
s2_scl_o = Signal(bool(1))
s2_scl_t = Signal(bool(1))
s2_sda_o = Signal(bool(1))
s2_sda_t = Signal(bool(1))
# I2C master
i2c_master_inst = i2c.I2CMaster()
i2c_master_logic = i2c_master_inst.create_logic(clk,
rst,
scl_i=m_scl_i,
scl_o=m_scl_o,
scl_t=m_scl_t,
sda_i=m_sda_i,
sda_o=m_sda_o,
sda_t=m_sda_t,
prescale=4,
name='master')
# I2C memory model 2
i2c_mem_inst2 = i2c.I2CMem(1024)
i2c_mem_logic2 = i2c_mem_inst2.create_logic(scl_i=s2_scl_i,
scl_o=s2_scl_o,
scl_t=s2_scl_t,
sda_i=s2_sda_i,
sda_o=s2_sda_o,
sda_t=s2_sda_t,
abw=2,
address=0x51,
latency=0,
name='slave2')
# WB RAM model
wb_ram_inst = wb.WBRam(2**16)
wb_ram_port0 = wb_ram_inst.create_port(clk,
adr_i=wb_adr_o,
dat_i=wb_dat_o,
dat_o=wb_dat_i,
we_i=wb_we_o,
sel_i=wb_sel_o,
stb_i=wb_stb_o,
ack_o=wb_ack_i,
cyc_i=wb_cyc_o,
latency=1,
asynchronous=False,
name='port0')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
i2c_scl_i=i2c_scl_i,
i2c_scl_o=i2c_scl_o,
i2c_scl_t=i2c_scl_t,
i2c_sda_i=i2c_sda_i,
i2c_sda_o=i2c_sda_o,
i2c_sda_t=i2c_sda_t,
wb_adr_o=wb_adr_o,
wb_dat_i=wb_dat_i,
wb_dat_o=wb_dat_o,
wb_we_o=wb_we_o,
wb_sel_o=wb_sel_o,
wb_stb_o=wb_stb_o,
wb_ack_i=wb_ack_i,
wb_err_i=wb_err_i,
wb_cyc_o=wb_cyc_o,
busy=busy,
bus_addressed=bus_addressed,
bus_active=bus_active,
enable=enable,
device_address=device_address)
@always_comb
def bus():
# emulate I2C wired AND
scl = m_scl_o & i2c_scl_o & s2_scl_o
sda = m_sda_o & i2c_sda_o & s2_sda_o
m_scl_i.next = scl
m_sda_i.next = sda
i2c_scl_i.next = scl
i2c_sda_i.next = sda
s2_scl_i.next = scl
s2_sda_i.next = sda
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
enable.next = 1
device_address.next = 0x50
yield clk.posedge
print("test 1: write")
current_test.next = 1
i2c_master_inst.init_write(0x50, b'\x00\x04' + b'\x11\x22\x33\x44')
yield i2c_master_inst.wait()
yield clk.posedge
while busy:
yield clk.posedge
data = wb_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(4, 4) == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 2: read")
current_test.next = 2
i2c_master_inst.init_write(0x50, b'\x00\x04')
i2c_master_inst.init_read(0x50, 4)
yield i2c_master_inst.wait()
yield clk.posedge
data = i2c_master_inst.get_read_data()
assert data[0] == 0x50
assert data[1] == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 3: various writes")
current_test.next = 3
for length in range(1, 9):
for offset in range(4):
i2c_master_inst.init_write(
0x50,
bytearray(
struct.pack('>H', 256 *
(16 * offset + length) + offset) +
b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]))
yield i2c_master_inst.wait()
yield clk.posedge
while busy:
yield clk.posedge
data = wb_ram_inst.read_mem(256 * (16 * offset + length), 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(
256 * (16 * offset + length) + offset,
length) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
yield delay(100)
yield clk.posedge
print("test 4: various reads")
current_test.next = 4
for length in range(1, 9):
for offset in range(4):
i2c_master_inst.init_write(
0x50,
bytearray(
struct.pack('>H',
256 * (16 * offset + length) + offset)))
i2c_master_inst.init_read(0x50, length)
yield i2c_master_inst.wait()
yield clk.posedge
data = i2c_master_inst.get_read_data()
assert data[0] == 0x50
assert data[1] == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
yield delay(100)
# TODO various reads and writes
# yield clk.posedge
# print("test 3: read with delays")
# current_test.next = 3
# i2c_master_inst.init_write(0x50, b'\x00\x04')
# i2c_master_inst.init_read(0x50, 4)
# data_source.send(b'\x11\x22\x33\x44')
# data_source_pause.next = True
# data_sink_pause.next = True
# yield delay(5000)
# data_sink_pause.next = False
# yield delay(2000)
# data_source_pause.next = False
# yield i2c_master_inst.wait()
# yield clk.posedge
# data = None
# while not data:
# yield clk.posedge
# data = data_sink.recv()
# assert data.data == b'\x00\x04'
# data = i2c_master_inst.get_read_data()
# assert data[0] == 0x50
# assert data[1] == b'\x11\x22\x33\x44'
# yield delay(100)
yield clk.posedge
print("test 4: access slave 2")
current_test.next = 4
i2c_master_inst.init_write(0x51, b'\x00\x04' + b'\x11\x22\x33\x44')
yield i2c_master_inst.wait()
yield clk.posedge
data = i2c_mem_inst2.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert i2c_mem_inst2.read_mem(4, 4) == b'\x11\x22\x33\x44'
i2c_master_inst.init_write(0x51, b'\x00\x04')
i2c_master_inst.init_read(0x51, 4)
yield i2c_master_inst.wait()
yield clk.posedge
data = i2c_master_inst.get_read_data()
assert data[0] == 0x51
assert data[1] == b'\x11\x22\x33\x44'
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
XFCP_ID_TYPE = 0x0001
XFCP_ID_STR = "WB Master"
XFCP_EXT_ID = b''
XFCP_EXT_ID_STR = ""
COUNT_SIZE = 16
WB_DATA_WIDTH = 32
WB_ADDR_WIDTH = 32
WB_SELECT_WIDTH = (WB_DATA_WIDTH) / 8
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
up_xfcp_in_tdata = Signal(intbv(0)[8:])
up_xfcp_in_tvalid = Signal(bool(0))
up_xfcp_in_tlast = Signal(bool(0))
up_xfcp_in_tuser = Signal(bool(0))
up_xfcp_out_tready = Signal(bool(0))
wb_dat_i = Signal(intbv(0)[WB_DATA_WIDTH:])
wb_ack_i = Signal(bool(0))
wb_err_i = Signal(bool(0))
# Outputs
up_xfcp_in_tready = Signal(bool(0))
up_xfcp_out_tdata = Signal(intbv(0)[8:])
up_xfcp_out_tvalid = Signal(bool(0))
up_xfcp_out_tlast = Signal(bool(0))
up_xfcp_out_tuser = Signal(bool(0))
wb_adr_o = Signal(intbv(0)[WB_ADDR_WIDTH:])
wb_dat_o = Signal(intbv(0)[WB_DATA_WIDTH:])
wb_we_o = Signal(bool(0))
wb_sel_o = Signal(intbv(0)[WB_SELECT_WIDTH:])
wb_stb_o = Signal(bool(0))
wb_cyc_o = Signal(bool(0))
# XFCP ports
up_xfcp_port_out_pause = Signal(bool(0))
up_xfcp_port_in_pause = Signal(bool(0))
up_xfcp_port = xfcp.XFCPPort()
up_xfcp_port_logic = up_xfcp_port.create_logic(
clk=clk,
rst=rst,
xfcp_in_tdata=up_xfcp_out_tdata,
xfcp_in_tvalid=up_xfcp_out_tvalid,
xfcp_in_tready=up_xfcp_out_tready,
xfcp_in_tlast=up_xfcp_out_tlast,
xfcp_in_tuser=up_xfcp_out_tuser,
xfcp_out_tdata=up_xfcp_in_tdata,
xfcp_out_tvalid=up_xfcp_in_tvalid,
xfcp_out_tready=up_xfcp_in_tready,
xfcp_out_tlast=up_xfcp_in_tlast,
xfcp_out_tuser=up_xfcp_in_tuser,
pause_source=up_xfcp_port_in_pause,
pause_sink=up_xfcp_port_out_pause,
name='up_xfcp_port')
# WB RAM model
wb_ram = wb.WBRam(2**16)
wb_ram_port0 = wb_ram.create_port(clk,
adr_i=wb_adr_o,
dat_i=wb_dat_o,
dat_o=wb_dat_i,
we_i=wb_we_o,
sel_i=wb_sel_o,
stb_i=wb_stb_o,
ack_o=wb_ack_i,
cyc_i=wb_cyc_o,
latency=1,
asynchronous=False,
name='port0')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
up_xfcp_in_tdata=up_xfcp_in_tdata,
up_xfcp_in_tvalid=up_xfcp_in_tvalid,
up_xfcp_in_tready=up_xfcp_in_tready,
up_xfcp_in_tlast=up_xfcp_in_tlast,
up_xfcp_in_tuser=up_xfcp_in_tuser,
up_xfcp_out_tdata=up_xfcp_out_tdata,
up_xfcp_out_tvalid=up_xfcp_out_tvalid,
up_xfcp_out_tready=up_xfcp_out_tready,
up_xfcp_out_tlast=up_xfcp_out_tlast,
up_xfcp_out_tuser=up_xfcp_out_tuser,
wb_adr_o=wb_adr_o,
wb_dat_i=wb_dat_i,
wb_dat_o=wb_dat_o,
wb_we_o=wb_we_o,
wb_sel_o=wb_sel_o,
wb_stb_o=wb_stb_o,
wb_ack_i=wb_ack_i,
wb_err_i=wb_err_i,
wb_cyc_o=wb_cyc_o)
@always(delay(4))
def clkgen():
clk.next = not clk
def wait_normal():
i = 4
while i > 0:
i = max(0, i - 1)
if not up_xfcp_port.idle() or wb_cyc_o:
i = 4
yield clk.posedge
def wait_pause_source():
i = 2
while i > 0:
i = max(0, i - 1)
if not up_xfcp_port.idle() or wb_cyc_o:
i = 2
up_xfcp_port_in_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
up_xfcp_port_in_pause.next = False
yield clk.posedge
def wait_pause_sink():
i = 2
while i > 0:
i = max(0, i - 1)
if not up_xfcp_port.idle() or wb_cyc_o:
i = 2
up_xfcp_port_out_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
up_xfcp_port_out_pause.next = False
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: test write")
current_test.next = 1
pkt = xfcp.XFCPFrame()
pkt.ptype = 0x12
pkt.payload = bytearray(struct.pack('<IH', 0, 4) + b'\x11\x22\x33\x44')
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt)
yield clk.posedge
yield wait()
yield clk.posedge
data = wb_ram.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram.read_mem(0, 4) == b'\x11\x22\x33\x44'
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x13
assert rx_pkt.payload.data == struct.pack('<IH', 0, 4)
yield delay(100)
yield clk.posedge
print("test 2: test read")
current_test.next = 2
pkt = xfcp.XFCPFrame()
pkt.ptype = 0x10
pkt.payload = bytearray(struct.pack('<IH', 0, 4))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x11
assert rx_pkt.payload.data == struct.pack('<IH', 0,
4) + b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 3: various writes")
current_test.next = 3
for length in range(1, 8):
for offset in range(4):
pkt = xfcp.XFCPFrame()
pkt.ptype = 0x12
pkt.payload = bytearray(
struct.pack('<IH', 256 *
(16 * offset + length) + offset, length) +
b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length])
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt)
yield clk.posedge
yield wait()
yield clk.posedge
data = wb_ram.read_mem(256 * (16 * offset + length), 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
assert wb_ram.read_mem(
256 * (16 * offset + length) + offset, length
) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x13
assert rx_pkt.payload.data == struct.pack(
'<IH', 256 * (16 * offset + length) + offset, length)
yield delay(100)
yield clk.posedge
print("test 4: various reads")
current_test.next = 4
for length in range(1, 8):
for offset in range(4):
pkt = xfcp.XFCPFrame()
pkt.ptype = 0x10
pkt.payload = bytearray(
struct.pack('<IH', 256 * (16 * offset + length) + offset,
length))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x11
assert rx_pkt.payload.data == struct.pack(
'<IH', 256 * (16 * offset + length) + offset,
length) + b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
yield delay(100)
yield clk.posedge
print("test 5: test trailing padding")
current_test.next = 5
pkt1 = xfcp.XFCPFrame()
pkt1.ptype = 0x12
pkt1.payload = bytearray(struct.pack('<IH', 7, 1) + b'\xAA')
pkt2 = xfcp.XFCPFrame()
pkt2.ptype = 0x12
pkt2.payload = bytearray(
struct.pack('<IH', 8, 1) + b'\xBB' + b'\x00' * 8)
pkt3 = xfcp.XFCPFrame()
pkt3.ptype = 0x10
pkt3.payload = bytearray(struct.pack('<IH', 7, 1) + b'\x00' * 8)
pkt4 = xfcp.XFCPFrame()
pkt4.ptype = 0x10
pkt4.payload = bytearray(struct.pack('<IH', 7, 1) + b'\x00' * 1)
pkt5 = xfcp.XFCPFrame()
pkt5.ptype = 0x12
pkt5.payload = bytearray(struct.pack('<IH', 9, 1) + b'\xCC')
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt1)
up_xfcp_port.send(pkt2)
up_xfcp_port.send(pkt3)
up_xfcp_port.send(pkt4)
up_xfcp_port.send(pkt5)
yield clk.posedge
yield wait()
yield clk.posedge
data = wb_ram.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram.read_mem(7, 3) == b'\xAA\xBB\xCC'
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x13
assert rx_pkt.payload.data == struct.pack('<IH', 7, 1)
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x13
assert rx_pkt.payload.data == struct.pack('<IH', 8, 1)
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x11
assert rx_pkt.payload.data == struct.pack('<IH', 7, 1) + b'\xAA'
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x11
assert rx_pkt.payload.data == struct.pack('<IH', 7, 1) + b'\xAA'
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x13
assert rx_pkt.payload.data == struct.pack('<IH', 9, 1)
yield delay(100)
yield clk.posedge
print("test 6: test id")
current_test.next = 6
pkt = xfcp.XFCPFrame()
pkt.ptype = 0xFE
pkt.payload = b''
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0xff
assert len(rx_pkt.payload.data) == 32
yield delay(100)
yield clk.posedge
print("test 7: test id with trailing bytes")
current_test.next = 7
pkt1 = xfcp.XFCPFrame()
pkt1.ptype = 0xFE
pkt1.payload = b'\0' * 256
pkt2 = xfcp.XFCPFrame()
pkt2.ptype = 0xFE
pkt2.payload = b'\0' * 8
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt1)
up_xfcp_port.send(pkt2)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0xff
assert len(rx_pkt.payload.data) == 32
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0xff
assert len(rx_pkt.payload.data) == 32
yield delay(100)
yield clk.posedge
print("test 8: test with rpath")
current_test.next = 8
pkt1 = xfcp.XFCPFrame()
pkt1.rpath = [1, 2, 3]
pkt1.ptype = 0xFE
pkt1.payload = b'\0' * 8
pkt2 = xfcp.XFCPFrame()
pkt2.rpath = [4, 5, 6]
pkt2.ptype = 0x10
pkt2.payload = bytearray(struct.pack('<IH', 0, 4))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt1)
up_xfcp_port.send(pkt2)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.rpath == [1, 2, 3]
assert rx_pkt.ptype == 0xff
assert len(rx_pkt.payload.data) == 32
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.rpath == [4, 5, 6]
assert rx_pkt.ptype == 0x11
assert rx_pkt.payload.data == struct.pack('<IH', 0,
4) + b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 9: test invalid packets")
current_test.next = 9
pkt1 = xfcp.XFCPFrame()
pkt1.ptype = 0x99
pkt1.payload = b'\x00' * 8
pkt2 = xfcp.XFCPFrame()
pkt2.path = [0]
pkt2.ptype = 0xFE
pkt2.payload = b''
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt1)
up_xfcp_port.send(pkt2)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
assert rx_pkt is None
yield delay(100)
raise StopSimulation
return instances()
