예제 #1
0
def main(flib, fnet, targetdir="current/"):

    import ply_liberty
    print "\nParsing Library"
    start = time()
    lsi_lib = PLYPair()
    lsi_lib.set_lexer(ply_liberty.create_lexer())
    lsi_lib.set_parser(ply_liberty.create_parser())
    lsi_lib.parse_file(flib)
    total = time() - start
    print "Total Time:", total, "s"
    # import pdb; pdb.set_trace()

    import ply_boolean_expressions
    print "\nParsing Boolean Expressions"
    start = time()
    be = PLYPair()
    be.set_lexer(ply_boolean_expressions.create_lexer())
    be.set_parser(ply_boolean_expressions.create_parser())
    for g in lsi_lib.result:
        g = lsi_lib.result[g]
        ply_boolean_expressions.update(g.getPinMap())
        for p in g.pins:
            if 'function' in g.pins[p]:
                g.pins[p]['o_function'] = g.pins[p]['function']
                g.pins[p]['function'] = be.parse(g.pins[p]['function'])
        for s in g.specials:
            s = g.specials[s]
            for k in s.getBEatts():
                s.atts['o_' + k] = s.atts[k]
                s.atts[k] = be.parse(s.atts[k])
    total = time() - start
    print "Total Time:", total, "s"
    # import pdb; pdb.set_trace()

    import ply_verilog_netlist
    print "\nParsing CCX"
    start = time()
    cd = {key: "CELL" for key in lsi_lib.result.keys()}
    ccx = PLYPair()
    ccx.set_lexer(ply_verilog_netlist.create_lexer(cd))
    ccx.set_parser(ply_verilog_netlist.create_parser(lsi_lib.result))
    ccx.parse_file(fnet)
    total = time() - start
    print "Total Time:", total, "s"
    # import pdb; pdb.set_trace()

    import wire_remover
    print "\nRemoving Wires from database"
    start = time()
    wire_remover.main(ccx.result['wires'], ccx.result['gates'], lsi_lib.result)
    total = time() - start
    print "Total Time:", total, "s"
    # import pdb; pdb.set_trace()

    import file_writer
    print "\nWriting Files"
    start = time()
    flib = flib.split('/')[-1].split('.')[0]
    fnet = fnet.split('/')[-1].split('.')[0]
    file_writer.generateC(targetdir + flib, lsi_lib.result)
    file_writer.generateRoss(targetdir + fnet, lsi_lib.result,
                             ccx.result['gates'])
    total = time() - start
    print "Total Time:", total, "s"

    import pdb
    pdb.set_trace()
예제 #2
0
def main(flib, fnet, targetdir="current/"):

	import ply_liberty
	print "\nParsing Library"
	start = time()
	lsi_lib = PLYPair()
	lsi_lib.set_lexer(ply_liberty.create_lexer())
	lsi_lib.set_parser(ply_liberty.create_parser())
	lsi_lib.parse_file(flib)
	total = time() - start
	print "Total Time:", total, "s"
	# import pdb; pdb.set_trace()

	import ply_boolean_expressions
	print "\nParsing Boolean Expressions"
	start = time()
	be = PLYPair()
	be.set_lexer(ply_boolean_expressions.create_lexer())
	be.set_parser(ply_boolean_expressions.create_parser())
	for g in lsi_lib.result:
		g = lsi_lib.result[g]
		ply_boolean_expressions.update(g.getPinMap())
		for p in g.pins:
			if 'function' in g.pins[p]:
				g.pins[p]['o_function'] = g.pins[p]['function']
				g.pins[p]['function'] = be.parse(g.pins[p]['function'])
		for s in g.specials:
			s = g.specials[s]
			for k in s.getBEatts():
				s.atts['o_'+k] = s.atts[k]
				s.atts[k] = be.parse(s.atts[k])
	total = time() - start
	print "Total Time:", total, "s"
	# import pdb; pdb.set_trace()

	import ply_verilog_netlist
	print "\nParsing CCX"
	start = time()
	cd = {key : "CELL" for key in lsi_lib.result.keys()}
	ccx = PLYPair()
	ccx.set_lexer(ply_verilog_netlist.create_lexer(cd))
	ccx.set_parser(ply_verilog_netlist.create_parser(lsi_lib.result))
	ccx.parse_file(fnet)
	total = time() - start
	print "Total Time:", total, "s"
	# import pdb; pdb.set_trace()

	import wire_remover
	print "\nRemoving Wires from database"
	start = time()
	wire_remover.main(ccx.result['wires'], ccx.result['gates'], lsi_lib.result)
	total = time() - start
	print "Total Time:", total, "s"
	# import pdb; pdb.set_trace()

	import file_writer
	print "\nWriting Files"
	start = time()
	flib = flib.split('/')[-1].split('.')[0]
	fnet = fnet.split('/')[-1].split('.')[0]
	file_writer.generateC(targetdir+flib, lsi_lib.result)
	file_writer.generateRoss(targetdir+fnet, lsi_lib.result, ccx.result['gates'])
	total = time() - start
	print "Total Time:", total, "s"

	import pdb; pdb.set_trace()
예제 #3
0
	print "Parsing CCX"
	start = time()
	cd = {key : "CELL" for key in lsi_lib.result.keys()}
	ccx = PLYPair()
	ccx.set_lexer(ply_verilog_netlist.create_lexer(cd))
	ccx.set_parser(ply_verilog_netlist.create_parser(lsi_lib.result))
	ccx.parse_file('Examples/ccx_lsi.vSyn')
	total = time() - start
	print "Total Time:", total, "s"
	# print ccx.result
	# import pdb; pdb.set_trace()

	print "Removing Wires from database"
	start = time()
	import wire_remover
	wire_remover.main(ccx.result['wires'], ccx.result['gates'], lsi_lib.result)
	total = time() - start
	print "Total Time:", total, "s"
	
	print "Writing Files"
	start = time()
	import file_writer
	file_writer.out_files(ccx.result['gates'], lsi_lib.result, "test_ccx_ross")
	total = time() - start
	print "Total Time:", total, "s"

	import pdb; pdb.set_trace()

	ccx.result.stats()
	ccx.result.net_stats()
	ccx.result.wire_stats(lsi_lib.result)