def test_version(verbose=False): """ @brief Test Version """ # TODO - get version from VHDL source file... response = read_address(0x0001) # Version - 0x----
def test_loopback_register(register=0, verbose=True): print print 'Loopback Register {:}'.format(register) print address = { 0 : 0x0003, 1 : 0x000B }[register] read_address(address, verbose=verbose) # Loopback Register write_address(address, 0x0000) # Write Loopback Register read_address(address, verbose=verbose) # Loopback Register write_address(address, 0x0001) # Write Loopback Register read_address(address, verbose=verbose) # Loopback Register write_address(address, 0x0002) # Write Loopback Register read_address(address, verbose=verbose) # Loopback Register write_address(address, 0x0004) # Write Loopback Register read_address(address, verbose=verbose) # Loopback Register write_address(address, 0x0008) # Write Loopback Register read_address(address, verbose=verbose) # Loopback Register write_address(address, 0x0010) # Write Loopback Register read_address(address, verbose=verbose) # Loopback Register write_address(address, 0x0020) # Write Loopback Register read_address(address, verbose=verbose) # Loopback Register write_address(address, 0x0040) # Write Loopback Register read_address(address, verbose=verbose) # Loopback Register write_address(address, 0x0080) # Write Loopback Register read_address(address, verbose=verbose) # Loopback Register write_address(address, 0x0100) # Write Loopback Register read_address(address, verbose=verbose) # Loopback Register write_address(address, 0x0200) # Write Loopback Register read_address(address, verbose=verbose) # Loopback Register write_address(address, 0x0400) # Write Loopback Register read_address(address, verbose=verbose) # Loopback Register write_address(address, 0x0800) # Write Loopback Register read_address(address, verbose=verbose) # Loopback Register write_address(address, 0x1000) # Write Loopback Register read_address(address, verbose=verbose) # Loopback Register write_address(address, 0x2000) # Write Loopback Register read_address(address, verbose=verbose) # Loopback Register write_address(address, 0x4000) # Write Loopback Register read_address(address, verbose=verbose) # Loopback Register write_address(address, 0x8000) # Write Loopback Register read_address(address, verbose=verbose) # Loopback Register write_address(address, 0x0000) # Write Loopback Register read_address(address, verbose=verbose) # Loopback Register write_address(address, 0x5555) # Write Loopback Register read_address(address, verbose=verbose) # Loopback Register write_address(address, 0xAAAA) # Write Loopback Register read_address(address, verbose=verbose) # Loopback Register write_address(address, 0xFFFF) # Write Loopback Register read_address(address, verbose=verbose) # Loopback Register write_address(address, 0x0000) # Write Loopback Register read_address(address, verbose=verbose) # Loopback Register
def test_sanity(verbose=False): """ @brief Test Sanity """ response = read_address(0x0000) # Sanity Check - 0xDEAD
def test_gpio(verbose=True): """ Wishbone Register Offset = 0xE000 @param verbose @returns None @brief Test GPIO """ # 0xE000 # 0x0001 direction # 0x0000 data # //gpio(15 downto 6) => open, # //gpio(5) => FPGA_DCM_RST, # //gpio(4) => BUFFER_OE_N, # //gpio(3) => LD_TAP4_N, # //gpio(2) => LD_TAP3_N, # //gpio(1) => LD_TAP2_N, # //gpio(0) => LD_TAP1_N # gpio(15 downto 12) => open, # gpio(11) => open, # gpio(10) => FPGA_DCM_RST, # gpio(9) => LD_DATA_N, # gpio(8) => BUFFER_OE_N, # gpio(7) => LD_TAP4_N, # gpio(6) => LD_TAP3_N, # gpio(5) => LD_TAP2_N, # gpio(4) => LD_TAP1_N, # gpio(3) => CS_TAP4_N, # gpio(2) => CS_TAP3_N, # gpio(1) => CS_TAP2_N, # gpio(0) => CS_TAP1_N #verbose = True print print '@' * 50 print print 'Test GPIO' print read_address(0xE000, verbose=verbose) write_address(0xE001, 0xF000) # Direction #logiWrite(0xE000, (0x00, 0x55)) # Data write_address(0xE000, 0x5000) # Data read_address(0xE000, verbose=verbose) #logiWrite(0xE000, (0x00, 0xAA)) # Data write_address(0xE000, 0xA000) # Data read_address(0xE000, verbose=verbose) # Drive BUFFER_OE_N Low #logiWrite(0xE001, (0x01, 0x00)) # Direction = Output # LSB, MSB write_address(0xE001, 0x0100) # Direction #logiWrite(0xE000, (0x00, 0x00)) # Data write_address(0xE000, 0x0000) # Data read_address(0xE000, verbose=verbose)
def test_spi1(verbose=False): """ Wishbone Register Offset = 0xB000 @param verbose @returns None @brief Test SPI """ # Register Address Width WISHBONE Access Description # REG_RXDATA 0x00 81 Read only Data from SPI port # REG_TXDATA 0x04 81 Read/write Data to SPI port, SSMASK or control register # REG_STATUS 0x08 8 Read only Status register # REG_CONTROL 0x0C 8 Read/write Control register # REG_SSMASK 0x10 81 Read/write Slave select register print print '@' * 50 print print 'Test SPI 1' print print 'REG_RXDATA = 0x{:04X}'.format(read_address(0xB000, verbose=verbose)) print 'REG_TXDATA = 0x{:04X}'.format(read_address(0xB004, verbose=verbose)) reg_status = read_address(0xB008, verbose=verbose) print 'REG_STATUS = 0x{:04X}'.format(reg_status) err = (reg_status >> 7) & 0x0001 rrdy = (reg_status >> 6) & 0x0001 trdy = (reg_status >> 5) & 0x0001 tmt = (reg_status >> 4) & 0x0001 toe = (reg_status >> 3) & 0x0001 roe = (reg_status >> 2) & 0x0001 # 1 - reserved # 0 - reserved print ' E (REG_STATUS bit 7 - Error Bit) =', err print ' RRDY (REG_STATUS bit 6 - Receive Ready Status) =', rrdy print ' TRDY (REG_STATUS bit 5 - Transmit Ready Status) =', trdy print ' TMT (REG_STATUS bit 4 - Transmit Shift Register is Empty) =', tmt print ' TOE (REG_STATUS bit 3 - Transmit Overrun Error) =', toe print ' ROE (REG_STATUS bit 2 - Receive Overrun Error) =', roe # 1 - reserved # 0 - reserved reg_control = read_address(0xB00C, verbose=verbose) print 'REG_CONTROL = 0x{:04X}'.format(reg_control) sso = (reg_control >> 7) & 0x0001 # 6- reserved ie = (reg_control >> 5) & 0x0001 irrdy = (reg_control >> 4) & 0x0001 itrdy = (reg_control >> 3) & 0x0001 # 2 - reserved itoe = (reg_control >> 1) & 0x0001 iroe = (reg_control >> 0) & 0x0001 print ' SSO (REG_CONTROL bit 7 - Error Bit) =', sso # 6- reserved print ' IE (REG_CONTROL bit 5 - Transmit Ready Status) =', ie print ' IRRDY (REG_CONTROL bit 4 - Transmit Shift Register is Empty) =', irrdy print ' ITRDY (REG_CONTROL bit 3 - Transmit Overrun Error) =', itrdy # 2- reserved print ' ITOE (REG_CONTROL bit 1 - Receive Overrun Error) =', itoe print ' IROE (REG_CONTROL bit 0 - Receive Overrun Error) =', iroe print 'REG_SSMASK = 0x{:04X}'.format(read_address(0xB010, verbose=verbose))
def test_registers(verbose=True): """ Wishbone Register Offset = 0x0000 @param verbose @returns None @brief Test Registers """ # reg_in(0) => X"DEAD", -- sudo ./read_wishbone 0x0000 # reg_in(1) => VERSION, # reg_in(2) => external_register, # reg_in(3) => LOOPBACK_REGISTER, # reg_in(4) => TAP1_INPUT, # reg_in(5) => TAP2_INPUT, # reg_in(6) => TAP3_INPUT, # reg_in(7) => TAP4_INPUT, # reg_in(8) => TAP1_REGISTER, # reg_in(9) => TAP2_REGISTER, # reg_in(10) => TAP3_REGISTER, # reg_in(11) => TAP4_REGISTER #0x0000 (173,) #0x0001 (6,) #0x0002 (0,) #0x0002 (52,) #0x0000 (173, 222) AD DE #0x0001 (6, 0) 06 00 #0x0002 (52, 18) 34 12 #0x0002 (52, 18) #0x0003 (3, 4) 3 #0x0003 (11, 4) # Switch B 1011 print print 'FPGA Registers' print read_address(0x0000, verbose=verbose) # Sanity Check - 0xDEAD read_address(0x0001, verbose=verbose) # Version read_address(0x0002, verbose=verbose) # External Register read_address(0x0003, verbose=verbose) # Loopback Register read_address(0x0004, verbose=verbose) # TAP1_INPUT read_address(0x0005, verbose=verbose) # TAP2_INPUT read_address(0x0006, verbose=verbose) # TAP3_INPUT read_address(0x0007, verbose=verbose) # TAP4_INPUT read_address(0x0008, verbose=verbose) # TAP1_REGISTER read_address(0x0009, verbose=verbose) # TAP2_REGISTER read_address(0x000A, verbose=verbose) # TAP3_REGISTER read_address(0x000B, verbose=verbose) # TAP4_REGISTER read_address(0x000C, verbose=verbose) read_address(0x000D, verbose=verbose) read_address(0x000E, verbose=verbose) read_address(0x000F, verbose=verbose)