def test_fixed_clock_period(self, clock_period_ps): verilog_path = test_base.create_named_output_text_file( f'sha256.clock_{clock_period_ps}_ps.v') subprocess.check_call([ CODEGEN_MAIN_PATH, '--generator=pipeline', '--delay_model=unit', '--clock_period_ps=' + str(clock_period_ps), '--alsologtostderr', '--output_verilog_path=' + verilog_path, SHA256_IR_PATH ])
def test_pipeline_no_system_verilog(self): verilog_path = test_base.create_named_output_text_file('sha256.v') subprocess.check_call([ CODEGEN_MAIN_PATH, '--nouse_system_verilog', '--generator=pipeline', '--delay_model=unit', '--pipeline_stages=10', '--alsologtostderr', '--output_verilog_path=' + verilog_path, SHA256_IR_PATH ]) with open(verilog_path, 'r') as f: verilog = f.read() self.assertNotIn('always_ff', verilog) self.assertIn('always @ (posedge clk)', verilog)
def test_combinational(self): ir_file = self.create_tempfile(content=NOT_ADD_IR) signature_path = test_base.create_named_output_text_file( 'combinational_sig.textproto') verilog_path = test_base.create_named_output_text_file('combinational.v') subprocess.check_call([ CODEGEN_MAIN_PATH, '--generator=combinational', '--alsologtostderr', '--entry=not_add', '--output_signature_path=' + signature_path, '--output_verilog_path=' + verilog_path, ir_file.full_path ]) with open(verilog_path, 'r') as f: self.assertIn('module not_add(', f.read()) with open(signature_path, 'r') as f: sig_proto = text_format.Parse(f.read(), module_signature_pb2.ModuleSignatureProto()) self.assertEqual(sig_proto.module_name, 'not_add') self.assertTrue(sig_proto.HasField('combinational'))
def test_clock_period_and_pipeline_stages(self): pipeline_stages = 5 clock_period_ps = 5000 verilog_path = test_base.create_named_output_text_file( f'sha256.clock_{clock_period_ps}_ps_pipeline_stages_{pipeline_stages}.v' ) subprocess.check_call([ CODEGEN_MAIN_PATH, '--generator=pipeline', '--delay_model=unit', '--pipeline_stages=' + str(pipeline_stages), '--clock_period_ps=' + str(clock_period_ps), '--alsologtostderr', '--output_verilog_path=' + verilog_path, SHA256_IR_PATH ])
def test_fixed_pipeline_length(self, pipeline_stages): signature_path = test_base.create_named_output_text_file( f'sha256.{pipeline_stages}_stage.sig.textproto') verilog_path = test_base.create_named_output_text_file( f'sha256.{pipeline_stages}_stage.v') subprocess.check_call([ CODEGEN_MAIN_PATH, '--generator=pipeline', '--delay_model=unit', '--pipeline_stages=' + str(pipeline_stages), '--alsologtostderr', '--output_signature_path=' + signature_path, '--output_verilog_path=' + verilog_path, SHA256_IR_PATH ]) with open(verilog_path, 'r') as f: verilog = f.read() self.assertIn(f'// ===== Pipe stage {pipeline_stages}', verilog) self.assertNotIn(f'// ===== Pipe stage {pipeline_stages + 1}', verilog) with open(signature_path, 'r') as f: sig_proto = text_format.Parse(f.read(), module_signature_pb2.ModuleSignatureProto()) self.assertTrue(sig_proto.HasField('pipeline')) self.assertEqual(sig_proto.pipeline.latency, pipeline_stages + 1)