def create_common_output(options, outfile): output = odin.output() target = odin.target() target.set_arch_file(abspath(options.arch)) output.set_output_type("blif") output.set_output_path_and_name(outfile + output.get_output_type()) output.set_target(target) return output
def create_odin_projects(options, file_list, base, path): soft = base + ".soft." if options.soft else None hard_mem = base + ".hard_mem." if options.mem or options.both else None hard_mult = base + ".hard_mult." if options.mult or options.both else None hard = base + ".hard." if options.both else None output = abspath(options.output) + "/" config = odin.config(verilog_files=create_common_verilog(file_list), debug_outputs=create_common_debug(options)) if soft: config.set_output(create_common_output(options, output + soft)) config.export(open(path + soft + "xml", "w"), 0) if hard_mem or hard_mult or hard: if hard: config.set_output(create_common_output(options, output + hard)) config.set_optimizations(create_common_optimizations(options)) config.export(open(path + hard + "xml", "w"), 0) if hard_mem: config.set_output(create_common_output(options, output + hard_mem)) config.set_optimizations(create_common_optimizations(options)) config.optimizations.set_multiply(None) config.export(open(path + hard_mem + "xml", "w"), 0) if hard_mult: config.set_output(create_common_output(options, output + hard_mult)) config.set_optimizations(create_common_optimizations(options)) config.optimizations.set_memory(None) config.export(open(path + hard_mult + "xml", "w"), 0)
def create_odin_projects(options, file_list, base, path): soft = base + ".soft." if options.soft else None hard_mem = base + ".hard_mem." if options.mem or options.both else None hard_mult = base + ".hard_mult." if options.mult or options.both else None hard = base + ".hard." if options.both else None output = abspath(options.output) + "/" config = odin.config(verilog_files=create_common_verilog(file_list), debug_outputs= create_common_debug(options)) if soft: config.set_output(create_common_output(options, output + soft)) config.export(open(path + soft + "xml", "w"), 0) if hard_mem or hard_mult or hard: if hard: config.set_output(create_common_output(options, output + hard)) config.set_optimizations(create_common_optimizations(options)) config.export(open(path + hard + "xml", "w"), 0) if hard_mem: config.set_output(create_common_output(options, output + hard_mem)) config.set_optimizations(create_common_optimizations(options)) config.optimizations.set_multiply(None) config.export(open(path + hard_mem + "xml", "w"), 0) if hard_mult: config.set_output(create_common_output(options, output + hard_mult)) config.set_optimizations(create_common_optimizations(options)) config.optimizations.set_memory(None) config.export(open(path + hard_mult + "xml", "w"), 0)
def create_common_optimizations(options): optimizations = odin.optimizations() if options.mem or options.both: mem = odin.memory() if options.split_width or options.split_depth: mem.set_split_memory_width(1 if options.split_width or options.split_depth else 0) mem.set_split_memory_depth(1 if options.split_depth else 0) else: mem = None optimizations.set_memory(mem) if options.mult or options.both: mult = odin.multiply() if options.size: mult.set_size(int(options.size)) mult.set_fracture(1 if options.fracture else 0) mult.set_fixed(1 if options.fixed else 0) else: mult = None optimizations.set_multiply(mult) return optimizations
def create_common_debug(options): debug = odin.debug_outputs() debug.set_debug_output_path(abspath(options.debug_path)) debug.set_output_ast_graphs(1 if options.ast_graph else 0) debug.set_output_netlist_graphs(1 if options.netlist_graph else 0) return debug
def create_common_verilog(file_list): verilog_files = odin.verilog_files() verilog_files.set_verilog_file(file_list) return verilog_files