def top(clk100MHz, sdram_clk, sdram_return_clk,sd_intf_inst): #def top(clk100MHz, sdram_clk, sdram_return_clk, pb, sd_intf_inst,host_int_inst): pb = Signal(bool(1)) clk100MHz = Signal(bool(0)) clk50MHz = Signal(bool(0)) reset = Signal(bool(False)) divclkby2_0 = divclkby2(clk100MHz,clk50MHz) test_status = Signal(intbv(0)[8:]) host_intf_inst = host_intf() i_wb_cyc, i_wb_stb, i_wb_we,o_wb_ack, o_wb_stall = [Signal(bool(0)) for _ in range(5)] i_wb_data = Signal(intbv(0)[16:]) o_wb_data = Signal(intbv(0)[16:]) i_wb_addr = Signal(intbv(0)[32:]) i_wb_sel = Signal(intbv(0)[4:]) sdramdev_inst = sdramdev(clk50MHz, sdram_clk, sdram_return_clk, pb, \ sd_intf_inst, host_intf_inst) """ sdramdev_inst = sdramdev(clk50MHz, sdram_clk, sdram_return_clk, pb, \ sd_intf_inst, host_intf_inst, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, \ o_wb_ack, o_wb_stall, o_wb_data, i_wb_sel) """ """ Only one sdramdev_inst.convert(name = 'sdramdev') or SdCntl_inst.convert(name = 'Sdcntl') can be uncommented at the same time not both or the following error will occur Signal has multiple drivers: host_intf_rst_i """ #sdramdev_inst.convert(name = 'sdramdev') sdramdev_inst.convert(name = 'sdcnt') return instances()
def top(clk100MHz, sdram_clk, sdram_return_clk, led_status, pb, sd_intf_inst):
clk50MHz = Signal(bool(0))
reset = Signal(bool(False))
divclkby2_0 = divclkby2(clk100MHz, clk50MHz)
test_status = Signal(intbv(0)[8:])
host_intf_inst = host_intf()
memdev_inst = memdev(clk50MHz, sdram_clk, sdram_return_clk, led_status, pb,
sd_intf_inst)
#memdev_inst.convert()
return instances()
def echo(master_clk_i, i_uart_rx, o_uart_tx, CLKS_PER_BIT=None):
divclkby2_0 = divclkby2(master_clk_i, clk50MHz)
uart_rx_0 = uart_rx(clk50MHz,
i_uart_rx,
w_RX_DV,
w_RX_Byte,
state_rx,
CLKS_PER_BIT=CLKS_PER_BIT)
uart_tx_0 = uart_tx(clk50MHz,
w_RX_DV,
w_RX_Byte,
w_TX_Active,
w_TX_Serial,
o_TX_Done,
state_tx,
CLKS_PER_BIT=CLKS_PER_BIT)
forceHi_0 = forceHi(w_TX_Serial, w_TX_Active, o_uart_tx)
return uart_tx_0, uart_rx_0, forceHi_0, divclkby2_0
def top(clk100MHz, sdram_clk, sdram_return_clk, led_status, pb, sd_intf_inst,
host_int_inst):
clk50MHz = Signal(bool(0))
reset = Signal(bool(False))
divclkby2_0 = divclkby2(clk100MHz, clk50MHz)
test_status = Signal(intbv(0)[8:])
#host_intf_inst = host_intf()
i_wb_cyc, i_wb_stb, i_wb_we, o_wb_ack, o_wb_stall = [
Signal(bool(0)) for _ in range(5)
]
i_wb_data = Signal(intbv(0)[16:])
o_wb_data = Signal(intbv(0)[16:])
i_wb_addr = Signal(intbv(0)[32:])
i_wb_sel = Signal(intbv(0)[4:])
sdramdev_inst = sdramdev(clk50MHz, sdram_clk, sdram_return_clk, led_status, pb, \
sd_intf_inst, host_intf_inst, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, \
o_wb_ack, o_wb_stall, o_wb_data, i_wb_sel)
sdramdev_inst.convert()
return instances()
def testbench():
i_TX_DV = Signal(bool(0))
o_TX_Done = Signal(bool(0))
"""
o_TX_Serial = Signal(bool(0))
w_TX_Serial = Signal(bool(0))
o_TX_Active = Signal(bool(0))
w_TX_Active = Signal(bool(0))
i_Clk = Signal(bool(0))
i_Clock = Signal(bool(0))
"""
"""
w_TX_Serial = Signal(bool(0))
w_TX_Active = Signal(bool(0))
"""
w_TX_Active = Signal(bool(0))
w_TX_Serial = Signal(intbv(0)[1:])
i_uart_rx = Signal(bool(0))
o_uart_tx = Signal(bool(0))
#o_TX_Serial = Signal(bool(0))
w_TX_Serial = Signal(bool(0))
o_TX_Active = Signal(bool(0))
master_clk_i = Signal(bool(0))
clk50MHz = Signal(bool(0))
w_RX_Byte = Signal(intbv(0)[8:])
w_TX_Byte = Signal(intbv(0)[8:])
i_TX_Byte = Signal(intbv(0)[8:])
w_RX_DV = Signal(bool(0))
w_TX_DV = Signal(bool(0))
#i_RX_Serial = Signal(bool(0))
#i_uart_rx = Signal(bool(0))
o_RX_Byte = Signal(intbv(0)[8:])
w_RX_Byte = Signal(intbv(0)[8:])
state_tx = Signal(t_state_tx.TX_IDLE)
state_rx = Signal(t_state_rx.RX_IDLE)
divclkby2_0 = divclkby2(master_clk_i, clk50MHz)
uart_rx_0 = uart_rx(clk50MHz,
i_uart_rx,
w_RX_DV,
w_RX_Byte,
state_rx,
CLKS_PER_BIT=25)
uart_tx_0 = uart_tx(clk50MHz,
w_TX_DV,
w_TX_Byte,
w_TX_Active,
w_TX_Serial,
o_TX_Done,
state_tx,
CLKS_PER_BIT=25)
forceHi_0 = forceHi(w_TX_Serial, w_TX_Active, o_uart_tx)
msg = ['h', 'e', 'l', 'l', 'o', 'w', 'o', 'l', 'd']
#msg = ['5','6','7','8','5','5','a','a','10','13']
"""
master_clk_i is 50 MHz 20 nsec is the output of the clkgen
This is further reduced to 25 MHz 40 nsec is what drives the
uart_rx_0 & uart_tx_0 with CLKS_PER_BIT=25 a baud rate of 1M Baud is obtained
"""
@always(delay(10))
def clkgen():
master_clk_i.next = not master_clk_i
@instance
def stimulus():
i_uart_rx.next = 1
for j in range(100):
yield clk50MHz.posedge
for j in range(8):
w_TX_Byte.next = ord(msg[j])
w_TX_DV.next = 1
for i in range(1):
yield clk50MHz.posedge
w_TX_DV.next = 0
for i in range(1):
yield clk50MHz.posedge
for i in range(250):
yield clk50MHz.posedge
for i in range(10):
yield clk50MHz.posedge
for j in range(8):
"""
srart bit
"""
i_uart_rx.next = 0
for i in range(25):
yield clk50MHz.posedge
for i in range(1):
yield clk50MHz.posedge
x = ord(msg[j])
#print x
"""
8 data bits
"""
y = 1
for i in range(8):
z = x & y
#print z
if (z > 0):
i_uart_rx.next = 1
else:
i_uart_rx.next = 0
y = y << 1
for l in range(25):
yield clk50MHz.posedge
"""
stop nit
"""
i_uart_rx.next = 1
for i in range(25):
yield clk50MHz.posedge
raise StopSimulation()
return uart_tx_0, uart_rx_0, clkgen, stimulus, forceHi_0, divclkby2_0
def sdram_test(master_clk_i, sdram_clk_o, sdram_clk_i,led_status, o_uart_tx, pb_i, sd_intf): clk50MHz = Signal(bool(0)) w_TX_Serial = Signal(bool(0)) w_TX_Active = Signal(bool(0)) w_TX_DV = Signal(bool(0)) w_TX_Byte = Signal(intbv(0)[8:]) w_TX_Done = Signal(bool(0)) state_tx = Signal(t_state_tx.TX_IDLE) #state_rx = Signal(t_state_rx.RX_IDLE) clk = Signal(bool(0)) """ @always(master_clk_i.posedge) def div2(): clk50MHz.next = not clk50MHz """ divclkby2_0 = divclkby2(master_clk_i,clk50MHz) @always_comb def clock_routing(): sdram_clk_o.next = clk50MHz clk.next = sdram_clk_i initialized = Signal(bool(False)) @always_seq(clk.posedge, reset=None) def internal_reset(): if initialized == False: initialized.next = not initialized # Get an internal version of the pushbutton signal and debounce it. pb, pb_prev, pb_debounced = [Signal(bool(0)) for _ in range(3)] #pb_inst = input_pin(pb_i, pb, pullup=True) #pb_debouncer = debouncer(clk, pb, pb_debounced, dbnc_window_g=0.01) DEBOUNCE_INTERVAL = int(49) debounce_cntr = Signal(intbv(DEBOUNCE_INTERVAL - 1, 0, DEBOUNCE_INTERVAL)) @always_seq(clk.posedge, reset=None) def debounce_pb(): if pb_i != pb_prev: debounce_cntr.next = DEBOUNCE_INTERVAL - 1 else: if debounce_cntr == 0: pb_debounced.next = pb_i debounce_cntr.next = 1 else: debounce_cntr.next = debounce_cntr - 1 pb_prev.next = pb_i reset = Signal(bool(False)) @always_comb def reset_logic(): # Reset if not initialized upon startup or if pushbutton is pressed (low). reset.next = not initialized or not pb_debounced test_status = Signal(intbv(0)[8:]) host_intf_inst = host_intf() memory_test_inst = memory_test(clk, reset, test_status, led_status, host_intf_inst, w_TX_Byte, w_TX_DV, w_TX_Active, w_TX_Serial,w_TX_Done) sdramCntl_inst = SdramCntl(clk, host_intf_inst, sd_intf) """ during a read 5 clks to read 6 clks in between address chg during a write 4 clks in between address chg 4 clks in between data chg 50MHz 1M 1e-06 per bit 10 e-6 per char """ #uart_rx_inst = uart_rx(sdram_clk_o,i_uart_rx,w_RX_DV,w_RX_Byte,state_rx,CLKS_PER_BIT=434) uart_tx_inst = uart_tx(sdram_clk_o,w_TX_DV,w_TX_Byte,w_TX_Active,w_TX_Serial,w_TX_Done,state_tx,CLKS_PER_BIT=50) forceHi_inst = forceHi(w_TX_Serial,w_TX_Active,o_uart_tx) return instances()