class Malta(Platform): type = 'Malta' system = Param.System(Parent.any, "system") cchip = MaltaCChip(pio_addr=0x801a0000000) io = MaltaIO(pio_addr=0x801fc000000) uart = Uart8250(pio_addr=0xBFD003F8) # Attach I/O devices to specified bus object. Can't do this # earlier, since the bus object itself is typically defined at the # System level. def attachIO(self, bus): self.cchip.pio = bus.master self.io.pio = bus.master self.uart.pio = bus.master
class Pc(Platform): type = 'Pc' cxx_header = "dev/x86/pc.hh" system = Param.System(Parent.any, "system") south_bridge = SouthBridge() pci_host = PcPciHost() # "Non-existant" ports used for timing purposes by the linux kernel i_dont_exist1 = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1) i_dont_exist2 = IsaFake(pio_addr=x86IOAddress(0xed), pio_size=1) # Ports behind the pci config and data regsiters. These don't do anything, # but the linux kernel fiddles with them anway. behind_pci = IsaFake(pio_addr=x86IOAddress(0xcf8), pio_size=8) # Serial port and terminal com_1 = Uart8250() com_1.pio_addr = x86IOAddress(0x3f8) com_1.device = Terminal() # Devices to catch access to non-existant serial ports. fake_com_2 = IsaFake(pio_addr=x86IOAddress(0x2f8), pio_size=8) fake_com_3 = IsaFake(pio_addr=x86IOAddress(0x3e8), pio_size=8) fake_com_4 = IsaFake(pio_addr=x86IOAddress(0x2e8), pio_size=8) # A device to catch accesses to the non-existant floppy controller. fake_floppy = IsaFake(pio_addr=x86IOAddress(0x3f2), pio_size=2) # NVMe Interface nvme = NVMeInterface(pci_func=0, pci_dev=5, pci_bus=0) def attachIO(self, bus, dma_ports=[]): self.south_bridge.attachIO(bus, dma_ports) self.i_dont_exist1.pio = bus.master self.i_dont_exist2.pio = bus.master self.behind_pci.pio = bus.master self.com_1.pio = bus.master self.fake_com_2.pio = bus.master self.fake_com_3.pio = bus.master self.fake_com_4.pio = bus.master self.fake_floppy.pio = bus.master self.pci_host.pio = bus.default self.nvme.pio = bus.master if dma_ports.count(self.nvme.dma) == 0: self.nvme.dma = bus.slave
class Pc(Platform): type = 'Pc' system = Param.System(Parent.any, "system") pciconfig = PciConfigAll() south_bridge = SouthBridge() # "Non-existant" port used for timing purposes by the linux kernel i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1) # Ports behind the pci config and data regsiters. These don't do anything, # but the linux kernel fiddles with them anway. behind_pci = IsaFake(pio_addr=x86IOAddress(0xcf8), pio_size=8) # Serial port and terminal terminal = Terminal() com_1 = Uart8250() com_1.pio_addr = x86IOAddress(0x3f8) com_1.terminal = terminal # Devices to catch access to non-existant serial ports. fake_com_2 = IsaFake(pio_addr=x86IOAddress(0x2f8), pio_size=8) fake_com_3 = IsaFake(pio_addr=x86IOAddress(0x3e8), pio_size=8) fake_com_4 = IsaFake(pio_addr=x86IOAddress(0x2e8), pio_size=8) # A device to catch accesses to the non-existant floppy controller. fake_floppy = IsaFake(pio_addr=x86IOAddress(0x3f2), pio_size=2) def attachIO(self, bus): self.south_bridge.attachIO(bus) self.i_dont_exist.pio = bus.port self.behind_pci.pio = bus.port self.com_1.pio = bus.port self.fake_com_2.pio = bus.port self.fake_com_3.pio = bus.port self.fake_com_4.pio = bus.port self.fake_floppy.pio = bus.port self.pciconfig.pio = bus.default bus.responder_set = True bus.responder = self.pciconfig
class SimpleBoard(Platform): type = 'SimpleBoard' cxx_header = 'dev/riscv/simpleboard.hh' system = Param.System(Parent.any, 'system') timer_cpu = TimerCpu(pio_addr=0x02000000) term = Terminal() uart = Uart8250(pio_addr=0x10013000) cust_regs = CustomRegs(pio_addr=0x90000000, regs=[0x90000000, 0x90000004, 0x90000008, 0x9000000c]) # attach I/O devices to bus # call this method after bus is defined at system level def attachIO(self, bus): self.cust_regs.pio = bus.master self.timer_cpu.pio = bus.master self.uart.device = self.term self.uart.pio = bus.master
class Tsunami(Platform): type = 'Tsunami' cxx_header = "dev/alpha/tsunami.hh" system = Param.System(Parent.any, "system") cchip = TsunamiCChip(pio_addr=0x801a0000000) pchip = TsunamiPChip(pio_addr=0x80180000000) fake_sm_chip = IsaFake(pio_addr=0x801fc000370) fake_uart1 = IsaFake(pio_addr=0x801fc0002f8) fake_uart2 = IsaFake(pio_addr=0x801fc0003e8) fake_uart3 = IsaFake(pio_addr=0x801fc0002e8) fake_uart4 = IsaFake(pio_addr=0x801fc0003f0) fake_ppc = IsaFake(pio_addr=0x801fc0003bb) fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000) fake_pnp_addr = IsaFake(pio_addr=0x801fc000279) fake_pnp_write = IsaFake(pio_addr=0x801fc000a79) fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203) fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243) fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283) fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3) fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303) fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343) fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383) fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3) fake_ata0 = IsaFake(pio_addr=0x801fc0001f0) fake_ata1 = IsaFake(pio_addr=0x801fc000170) fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer') io = TsunamiIO(pio_addr=0x801fc000000) uart = Uart8250(pio_addr=0x801fc0003f8) backdoor = AlphaBackdoor(pio_addr=0x80200000000, disk=Parent.simple_disk) # Attach I/O devices to specified bus object. Can't do this # earlier, since the bus object itself is typically defined at the # System level. def attachIO(self, bus): self.cchip.pio = bus.master self.pchip.pio = bus.master self.fake_sm_chip.pio = bus.master self.fake_uart1.pio = bus.master self.fake_uart2.pio = bus.master self.fake_uart3.pio = bus.master self.fake_uart4.pio = bus.master self.fake_ppc.pio = bus.master self.fake_OROM.pio = bus.master self.fake_pnp_addr.pio = bus.master self.fake_pnp_write.pio = bus.master self.fake_pnp_read0.pio = bus.master self.fake_pnp_read1.pio = bus.master self.fake_pnp_read2.pio = bus.master self.fake_pnp_read3.pio = bus.master self.fake_pnp_read4.pio = bus.master self.fake_pnp_read5.pio = bus.master self.fake_pnp_read6.pio = bus.master self.fake_pnp_read7.pio = bus.master self.fake_ata0.pio = bus.master self.fake_ata1.pio = bus.master self.fb.pio = bus.master self.io.pio = bus.master self.uart.pio = bus.master self.backdoor.pio = bus.master
class T1000(Platform): type = 'T1000' system = Param.System(Parent.any, "system") fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000) #warn_access="Accessing Clock Unit -- Unimplemented!") fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384, ret_data64=0x0000000000000000, update_data=False) #warn_access="Accessing Memory Banks -- Unimplemented!") fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000) #warn_access="Accessing JBI -- Unimplemented!") fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8, ret_data64=0x0000000000000001, update_data=True) #warn_access="Accessing L2 Cache Banks -- Unimplemented!") fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8, ret_data64=0x0000000000000001, update_data=True) #warn_access="Accessing L2 Cache Banks -- Unimplemented!") fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8, ret_data64=0x0000000000000001, update_data=True) #warn_access="Accessing L2 Cache Banks -- Unimplemented!") fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8, ret_data64=0x0000000000000001, update_data=True) #warn_access="Accessing L2 Cache Banks -- Unimplemented!") fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8, ret_data64=0x0000000000000000, update_data=True) #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8, ret_data64=0x0000000000000000, update_data=True) #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8, ret_data64=0x0000000000000000, update_data=True) #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8, ret_data64=0x0000000000000000, update_data=True) #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000) #warn_access="Accessing SSI -- Unimplemented!") hterm = Terminal() hvuart = Uart8250(pio_addr=0xfff0c2c000) htod = DumbTOD() pterm = Terminal() puart0 = Uart8250(pio_addr=0x1f10000000) iob = Iob() # Attach I/O devices that are on chip def attachOnChipIO(self, bus): self.iob.pio = bus.port self.htod.pio = bus.port # Attach I/O devices to specified bus object. Can't do this # earlier, since the bus object itself is typically defined at the # System level. def attachIO(self, bus): self.hvuart.terminal = self.hterm self.puart0.terminal = self.pterm self.fake_clk.pio = bus.port self.fake_membnks.pio = bus.port self.fake_l2_1.pio = bus.port self.fake_l2_2.pio = bus.port self.fake_l2_3.pio = bus.port self.fake_l2_4.pio = bus.port self.fake_l2esr_1.pio = bus.port self.fake_l2esr_2.pio = bus.port self.fake_l2esr_3.pio = bus.port self.fake_l2esr_4.pio = bus.port self.fake_ssi.pio = bus.port self.fake_jbi.pio = bus.port self.puart0.pio = bus.port self.hvuart.pio = bus.port