def pnp_uart(path, uid, ddn, port, irq):
resources = []
cls = rdt.SmallResourceItemIOPort
length = ctypes.sizeof(cls)
data = bytearray(length)
res = cls.from_buffer(data)
res.type = 0
res.name = rdt.SMALL_RESOURCE_ITEM_IO_PORT
res.length = 7
res._DEC = 1
res._MIN = port
res._MAX = port
res._ALN = 1
res._LEN = 8
resources.append(data)
cls = rdt.SmallResourceItemIRQ_factory(2)
length = ctypes.sizeof(cls)
data = bytearray(length)
res = cls.from_buffer(data)
res.type = 0
res.name = rdt.SMALL_RESOURCE_ITEM_IRQ_FORMAT
res.length = 2
res._INT = 1 << irq
resources.append(data)
resources.append(bytes([0x79, 0]))
resource_buf = bytearray().join(resources)
checksum = (256 - (sum(resource_buf) % 256)) % 256
resource_buf[-1] = checksum
uart = builder.DefDevice(
builder.PkgLength(), path,
builder.TermList(
builder.DefName("_HID",
builder.DWordConst(encode_eisa_id("PNP0501"))),
builder.DefName("_UID", builder.build_value(uid)),
builder.DefName("_DDN", builder.String(ddn)),
builder.DefName(
"_CRS",
builder.DefBuffer(builder.PkgLength(),
builder.WordConst(len(resource_buf)),
builder.ByteList(resource_buf)))))
return uart
def gen_root_pci_bus(path, prt_packages):
resources = []
# Bus number
cls = rdt.LargeResourceItemWordAddressSpace_factory()
length = ctypes.sizeof(cls)
data = bytearray(length)
res = cls.from_buffer(data)
res.type = 1 # Large type
res.name = rdt.LARGE_RESOURCE_ITEM_WORD_ADDRESS_SPACE
res.length = length - 3
res._TYP = 2 # Bus number range
res._DEC = 0 # Positive decoding
res._MIF = 1 # Minimum address fixed
res._MAF = 1 # Maximum address fixed
res.flags = 0
res._MAX = 0xff
res._LEN = 0x100
resources.append(data)
# The PCI hole below 4G
cls = rdt.LargeResourceItemDWordAddressSpace_factory()
length = ctypes.sizeof(cls)
data = bytearray(length)
res = cls.from_buffer(data)
res.type = 1 # Large type
res.name = rdt.LARGE_RESOURCE_ITEM_ADDRESS_SPACE_RESOURCE
res.length = length - 3
res._TYP = 0 # Memory range
res._DEC = 0 # Positive decoding
res._MIF = 1 # Minimum address fixed
res._MAF = 1 # Maximum address fixed
res.flags = 1 # read-write, non-cachable, TypeStatic
res._MIN = 0x80000000
res._MAX = 0xdfffffff
res._LEN = 0x60000000
resources.append(data)
# The PCI hole above 4G
cls = rdt.LargeResourceItemQWordAddressSpace_factory()
length = ctypes.sizeof(cls)
data = bytearray(length)
res = cls.from_buffer(data)
res.type = 1 # Large type
res.name = rdt.LARGE_RESOURCE_ITEM_QWORD_ADDRESS_SPACE
res.length = length - 3
res._TYP = 0 # Memory range
res._DEC = 0 # Positive decoding
res._MIF = 1 # Minimum address fixed
res._MAF = 1 # Maximum address fixed
res.flags = 1 # read-write, non-cachable, TypeStatic
res._MIN = 0x4000000000
res._MAX = 0x7fffffffff
res._LEN = 0x4000000000
resources.append(data)
cls = rdt.LargeResourceItemDWordAddressSpace_factory()
length = ctypes.sizeof(cls)
data = bytearray(length)
res = cls.from_buffer(data)
res.type = 1 # Large type
res.name = rdt.LARGE_RESOURCE_ITEM_ADDRESS_SPACE_RESOURCE
res.length = length - 3
res._TYP = 1 # Memory range
res._DEC = 0 # Positive decoding
res._MIF = 1 # Minimum address fixed
res._MAF = 1 # Maximum address fixed
res.flags = 3 # Entire range, TypeStatic
res._MIN = 0x0
res._MAX = 0xffff
res._LEN = 0x10000
resources.append(data)
# End tag
resources.append(bytes([0x79, 0]))
resource_buf = bytearray().join(resources)
checksum = (256 - (sum(resource_buf) % 256)) % 256
resource_buf[-1] = checksum
# Device object for the root PCI bus
tree = builder.DefDevice(
builder.PkgLength(), path,
builder.TermList(
builder.DefName("_HID",
builder.DWordConst(encode_eisa_id("PNP0A08"))),
builder.DefName("_CID",
builder.DWordConst(encode_eisa_id("PNP0A03"))),
builder.DefName("_BBN", builder.ZeroOp()),
builder.DefName("_UID", builder.ZeroOp()),
builder.DefName(
"_CRS",
builder.DefBuffer(builder.PkgLength(),
builder.WordConst(len(resource_buf)),
builder.ByteList(resource_buf))),
builder.DefName(
"_PRT",
builder.DefPackage(
builder.PkgLength(), builder.ByteData(len(prt_packages)),
builder.PackageElementList(*prt_packages)))))
return tree