def definition(cls):
# each valid clock, going to get a magma_repr in
# read or write each one of those to a location
rams = [DefineRAMAnyType(t.magma_repr(), t.valid_clocks(), read_latency=read_latency)() for _ in range(n)]
read_time_position_counter = DefineNestedCounters(t, has_cur_valid=True, has_ce=True, has_reset=has_reset)()
read_valid_term = TermAnyType(Bit)
read_last_term = TermAnyType(Bit)
write_time_position_counter = DefineNestedCounters(t, has_cur_valid=True, has_ce=True, has_reset=has_reset)()
write_valid_term = TermAnyType(Bit)
write_last_term = TermAnyType(Bit)
read_selector = DefineMuxAnyType(t.magma_repr(), n)()
for i in range(n):
wire(cls.WDATA, rams[i].WDATA)
wire(write_time_position_counter.cur_valid, rams[i].WADDR)
wire(read_selector.data[i], rams[i].RDATA)
wire(read_time_position_counter.cur_valid, rams[i].RADDR)
write_cur_ram = Decode(i, cls.WADDR.N)(cls.WADDR)
wire(write_cur_ram & write_time_position_counter.valid, rams[i].WE)
wire(cls.RADDR, read_selector.sel)
wire(cls.RDATA, read_selector.out)
wire(cls.WE, write_time_position_counter.CE)
wire(cls.RE, read_time_position_counter.CE)
wire(read_time_position_counter.valid, read_valid_term.I)
wire(read_time_position_counter.last, read_last_term.I)
wire(write_time_position_counter.valid, write_valid_term.I)
wire(write_time_position_counter.last, write_last_term.I)
if has_reset:
wire(cls.RESET, write_time_position_counter.RESET)
wire(cls.RESET, read_time_position_counter.RESET)
def definition(Sort2Elements):
sel = DefineMuxAnyType(Array[2, T], 2)()
cmp0 = cmp_component(Sort2Elements.I0)
cmp1 = cmp_component(Sort2Elements.I1)
cmp0_bits = Dehydrate(type(cmp0))
cmp1_bits = Dehydrate(type(cmp1))
wire(cmp0_bits.I, cmp0)
wire(cmp1_bits.I, cmp1)
lt = DefineCoreirUlt(cmp0_bits.out.N)()
wire(lt.I0, cmp0_bits.out)
wire(lt.I1, cmp1_bits.out)
# lt will emit 1 if I0 is less than
wire(Sort2Elements.I0, sel.data[1][0])
wire(Sort2Elements.I1, sel.data[1][1])
wire(Sort2Elements.I0, sel.data[0][1])
wire(Sort2Elements.I1, sel.data[0][0])
wire(lt.O, sel.sel[0])
wire(sel.out[0], Sort2Elements.O0)
wire(sel.out[1], Sort2Elements.O1)
def definition(cls):
op = DefineMuxAnyType(t.magma_repr(), 2)()
wire(cls.I[0], op.sel)
wire(cls.I[1][0], op.data[1])
wire(cls.I[1][1], op.data[0])
wire(op.out, cls.O)
if has_valid:
wire(cls.valid_up, cls.valid_down)
def test_mux_int_5():
n = 5
T = ST_Int().magma_repr()
testcircuit = DefineMuxAnyType(T, n)
tester = fault.Tester(testcircuit)
for i in range(n):
tester.circuit.data[i] = i
tester.circuit.sel = 2
tester.eval()
tester.circuit.out.expect(2)
compile_and_run(tester)
def definition(cls):
neg = DefineNegate(t.length())()
cmp = DefineCoreirUgt(t.length())()
mux = DefineMuxAnyType(t.magma_repr(), 2)()
wire(cls.I, mux.data[0])
wire(cls.I, neg.I)
wire(neg.O, mux.data[1])
wire(cls.I, cmp.I0)
wire(neg.O, cmp.I1)
wire(cmp.O, mux.sel[0])
abs_reg = DefineRegister(cls.st_out_t.magma_repr().N)()
wire(mux.out, abs_reg.I)
wire(abs_reg.O, cls.O)
if has_valid:
valid_reg = DefineRegister(1)()
wire(cls.valid_up, valid_reg.I[0])
wire(valid_reg.O[0], cls.valid_down)
def definition(cls):
enabled = DefineCoreirConst(1, 1)().O[0]
if has_valid:
enabled = cls.valid_up & enabled
wire(cls.valid_up, cls.valid_down)
if has_ce:
enabled = bit(cls.CE) & enabled
value_store = DefineRAM_ST(elem_t, 1, has_reset=has_reset)()
# write to value_store for first element, read for next
element_time_counter = DefineNestedCounters(elem_t, has_ce=True, has_reset=has_reset)()
element_idx_counter = AESizedCounterModM(n + i, has_ce=True, has_reset=has_reset)
is_first_element = Decode(0, element_idx_counter.O.N)(element_idx_counter.O)
zero_addr = DefineCoreirConst(1, 0)().O
wire(zero_addr, value_store.WADDR)
wire(zero_addr, value_store.RADDR)
wire(enabled & is_first_element, value_store.WE)
wire(enabled, value_store.RE)
wire(enabled, element_time_counter.CE)
wire(enabled & element_time_counter.last, element_idx_counter.CE)
element_time_counter_term = TermAnyType(Bit)
wire(element_time_counter.valid, element_time_counter_term.I)
wire(cls.I, value_store.WDATA)
output_selector = DefineMuxAnyType(elem_t.magma_repr(), 2)()
# on first element, send the input directly out. otherwise, use the register
wire(is_first_element, output_selector.sel[0])
wire(value_store.RDATA, output_selector.data[0])
wire(cls.I, output_selector.data[1])
wire(output_selector.out, cls.O)
if has_reset:
wire(value_store.RESET, cls.RESET)
wire(element_time_counter.RESET, cls.RESET)
wire(element_idx_counter.RESET, cls.RESET)
def definition(cls):
length_counter = AESizedCounterModM(numInputs, has_ce=has_ce, cout=True)
reg_input_mux = DefineMuxAnyType(cls.token_type, 2)()
op_instance = opDef()
accumulatorRegister = DefineRegisterAnyType(cls.token_type, has_ce=has_ce)()
if has_ce:
wire(cls.CE, accumulatorRegister.CE)
wire(cls.CE, length_counter.CE)
wire(cls.I, get_in0(op_instance))
wire(accumulatorRegister.O, get_in1(op_instance))
# use reduce input for register on first clock,
# otherwise use op output
wire(get_out(op_instance),reg_input_mux.data[0])
wire(cls.I,reg_input_mux.data[1])
wire(0 == length_counter.O, reg_input_mux.sel[0])
wire(reg_input_mux.out, accumulatorRegister.I)
wire(get_out(op_instance), cls.out)
wire(1, cls.ready)
# valid when COUT == 1 as register contains sum of all inputs
wire(length_counter.COUT == 1, cls.valid)
def definition(upsampleSequential):
# the counter of the current element of output sequence, when hits 0, load the next input to upsample
element_idx_counter = SizedCounterModM(n,
has_ce=True,
has_reset=has_reset)
is_first_element = Decode(0, element_idx_counter.O.N)(
element_idx_counter.O)
if has_reset:
wire(upsampleSequential.RESET, element_idx_counter.RESET)
# enabled means run the circuit
# do this when downstream is ready, so have something to communicate with,
# and when in first element and upstream is valid or have data to repeat
enabled = upsampleSequential.ready_down & \
((is_first_element & upsampleSequential.valid_up) | (~is_first_element))
# ready means can accept input when get valid from upstream
# do this when in first element and downstream ready to accept
ready = is_first_element & upsampleSequential.ready_down
# valid means can emit downstream
# valid when in first element and upstream valid or repeating old data
valid = (is_first_element
& upsampleSequential.valid_up) | (~is_first_element)
# only assert these signals when CE is high or no CE
if has_ce:
enabled = enabled & bit(upsampleSequential.CE)
ready = ready & bit(upsampleSequential.CE)
valid = valid & bit(upsampleSequential.CE)
if time_per_element > 1:
value_store = DefineRAMAnyType(T, time_per_element)()
value_store_input = value_store.WDATA
value_store_output = value_store.RDATA
time_per_element_counter = SizedCounterModM(
time_per_element, has_ce=True, has_reset=has_reset)
go_to_next_element = Decode(time_per_element - 1,
time_per_element_counter.O.N)(
time_per_element_counter.O)
wire(time_per_element_counter.CE, enabled)
wire(element_idx_counter.CE, enabled & go_to_next_element)
wire(value_store.WE, is_first_element & enabled)
# location in current element is where to read and write.
# will write on first iteration through element, read on later iterations
wire(time_per_element_counter.O, value_store.WADDR)
wire(time_per_element_counter.O, value_store.RADDR)
if has_reset:
wire(time_per_element_counter.RESET,
upsampleSequential.RESET)
else:
value_store = DefineRegisterAnyType(T, has_ce=True)()
value_store_input = value_store.I
value_store_output = value_store.O
wire(element_idx_counter.CE, enabled)
wire(value_store.CE, is_first_element & enabled)
output_selector = DefineMuxAnyType(T, 2)()
wire(upsampleSequential.I, value_store_input)
# on first element, send the input directly out. otherwise, use the register
wire(is_first_element, output_selector.sel[0])
wire(value_store_output, output_selector.data[0])
wire(upsampleSequential.I, output_selector.data[1])
wire(output_selector.out, upsampleSequential.O)
wire(valid, upsampleSequential.valid_down)
wire(ready, upsampleSequential.ready_up)