def primitives(cn):
mydir = pathlib.Path(__file__).resolve()
pdk_path = mydir.parent.parent.parent / 'pdks' / 'FinFET14nm_Mock_PDK'
test_path = mydir.parent / 'test_circuits' / (cn + '.sp')
updated_ckt, library = compiler(test_path, cn, pdk_path)
assert cn in updated_ckt
return compiler_output(test_path, library, updated_ckt, 'sizing',
pathlib.Path(__file__).parent / 'Results', pdk_path)
def test_sizing1():
mydir = pathlib.Path(__file__).resolve()
test_path = mydir.parent / 'test_circuits' / 'intel_circuit1.sp'
updated_ckt,library = compiler(test_path, "intel_circuit1",0 )
all_subckt_list = [ele["name"] for ele in updated_ckt]
assert 'intel_circuit1' in all_subckt_list
pdk_path = mydir.parent.parent.parent / 'pdks' / 'FinFET14nm_Mock_PDK'
primitives = compiler_output(test_path, library, updated_ckt, 'sizing', pathlib.Path(__file__).parent / 'Results', pdk_path )
assert primitives['DCL_PMOS_nfin6_m4_n12_X2_Y1_ST6_HVT']['stack']==6
assert primitives['DCL_PMOS_nfin6_m4_n12_X2_Y1_ST6_HVT']['vt_type']=='HVT'
def test_sizing4(path):
test_path, pdk_path = path
updated_ckt, library = compiler(test_path, 'intel_circuit4', pdk_path)
assert 'SCM_PMOS' in updated_ckt
assert 'CMB_PMOS_2' in updated_ckt
assert 'INV_B' in updated_ckt
assert 'intel_circuit4' in updated_ckt
primitives = compiler_output(test_path, library, updated_ckt, 'sizing',
pathlib.Path(__file__).parent / 'Results',
pdk_path)
assert len(primitives) == 7
def test_sizing4():
mydir = pathlib.Path(__file__).resolve()
test_path = mydir.parent / 'test_circuits' / 'intel_circuit4.sp'
updated_ckt,library = compiler(test_path, "intel_circuit4",0 )
all_subckt_list = [ele["name"] for ele in updated_ckt]
assert 'SCM_PMOS' in all_subckt_list
assert 'CMB_PMOS_2' in all_subckt_list
assert 'INV_B' in all_subckt_list
assert 'intel_circuit4' in all_subckt_list
pdk_path = mydir.parent.parent.parent / 'pdks' / 'FinFET14nm_Mock_PDK'
primitives = compiler_output(test_path, library, updated_ckt, 'sizing', pathlib.Path(__file__).parent / 'Results', pdk_path )
assert len(primitives) ==9
def test_compiler():
test_path = pathlib.Path(__file__).resolve().parent / 'ota.sp'
updated_ckt, library = compiler(test_path, "ota", 0)
all_subckt_list = [ele["name"] for ele in updated_ckt]
assert 'CMC_PMOS_S' in all_subckt_list
assert 'CMC_PMOS' in all_subckt_list
assert 'SCM_NMOS' in all_subckt_list
assert 'CMC_NMOS' in all_subckt_list
assert 'DP_NMOS' in all_subckt_list
assert 'ota' in all_subckt_list
return (updated_ckt, library)
def test_sizing3():
mydir = pathlib.Path(__file__).resolve()
test_path = mydir.parent / 'test_circuits' / 'intel_circuit3.sp'
updated_ckt,library = compiler(test_path, "intel_circuit3",0 )
all_subckt_list = [ele["name"] for ele in updated_ckt]
assert 'DP_NMOS_B' in all_subckt_list
assert 'intel_circuit3' in all_subckt_list
pdk_path = mydir.parent.parent.parent / 'pdks' / 'FinFET14nm_Mock_PDK'
primitives = compiler_output(test_path, library, updated_ckt, 'sizing', pathlib.Path(__file__).parent / 'Results', pdk_path )
assert len(primitives) ==6
assert 'Switch_PMOS_nfin4_nf1_m4_n12_X2_Y1_ST3' in primitives.keys()
assert primitives['Switch_PMOS_nfin4_nf1_m4_n12_X2_Y1_ST3']['stack']==3
assert primitives['Switch_PMOS_nfin6_nf4_m3_n12_X3_Y2_LVT']['vt_type']=='LVT'
def test_compiler():
test_path = pathlib.Path(
__file__).resolve().parent / 'test_circuits' / 'ota' / 'ota.sp'
pdk_dir = pathlib.Path(__file__).resolve(
).parent.parent.parent / 'pdks' / 'FinFET14nm_Mock_PDK'
updated_ckt, library = compiler(test_path, "ota", pdk_dir)
assert 'CMC_PMOS' in updated_ckt
assert 'SCM_NMOS' in updated_ckt
assert 'CMC_S_NMOS_B' in updated_ckt
assert 'DP_NMOS_B' in updated_ckt
assert 'ota' in updated_ckt
return (updated_ckt, library)
def test_compiler_hsc(dir_name):
circuit_name = 'high_speed_comparator'
test_path = pathlib.Path(__file__).resolve(
).parent / 'test_circuits' / dir_name / (circuit_name + '.sp')
pdk_dir = pathlib.Path(__file__).resolve(
).parent.parent.parent / 'pdks' / 'FinFET14nm_Mock_PDK'
updated_ckt, library = compiler(test_path, circuit_name, pdk_dir)
assert 'DP_NMOS_B' in updated_ckt.keys()
assert 'CCP_S_NMOS_B' in updated_ckt.keys()
assert 'CCP_PMOS' in updated_ckt.keys()
assert 'DP_NMOS_B' in updated_ckt.keys()
assert 'INV' in updated_ckt.keys()
assert 'dp' in updated_ckt.keys()
assert 'ccn' in updated_ckt.keys()
assert 'ccp' in updated_ckt.keys()
assert 'inv_p' in updated_ckt.keys()
assert 'inv_n' in updated_ckt.keys()
return (updated_ckt, library, dir_name)
def test_cap():
mydir = pathlib.Path(__file__).resolve()
pdk_path = mydir.parent.parent.parent / 'pdks' / 'FinFET14nm_Mock_PDK'
test_path = mydir.parent / 'test_circuits' / 'test_cap.sp'
gen_const_path = mydir.parent / 'Results' / 'test_cap.const.json'
gold_const_path = mydir.parent / 'test_results' / 'test_cap.const.json'
updated_ckt, library = compiler(test_path, "test_cap", pdk_path)
assert 'test_cap' in updated_ckt
primitives = compiler_output(test_path, library, updated_ckt, 'test_cap',
pathlib.Path(__file__).parent / 'Results',
pdk_path)
assert 'Cap_12f' in primitives.keys()
with open(gen_const_path, "r") as const_fp:
gen_const = json.load(const_fp)
with open(gold_const_path, "r") as const_fp:
gold_const = json.load(const_fp)
assert gold_const == gen_const
