def test_one():
tx = Transistor(device_type='parallel', nf=4, nfin=4, model_name='n')
tx_array = TransistorArray(unit_transistor=tx,
m={1: 1},
ports={1: {k: k for k in ['D', 'G', 'S']}},
n_rows=1
)
def test_two():
tx = Transistor(device_type='parallel',
nf=4,
nfin=4,
model_name='p')
data = mos(tx)
data['globalRoutes'] = []
data['globalRouteGrid'] = []
print(data)
with open(pathlib.Path(os.getenv('ALIGN_HOME'))/'Viewer'/'INPUT'/'test_mos_two.json', "wt") as fp:
fp.write(json.dumps(data, indent=2) + '\n')
def mos_array_temporary_wrapper(self, x_cells, y_cells, pattern, vt_type,
ports, **parameters):
#################################################################################################
# TODO: All of below goes away when TransistorArray is passed to mos_array as shown below
for key in ['m', 'real_inst_type']:
assert key in parameters, f'Missing transistor parameter {key}'
assert 'nf' or 'stack' in parameters, f'Missing transistor parameter nf or stack'
if 'nf' in parameters:
nf = 'nf'
device_type = 'parallel'
elif 'stack' in parameters:
nf = 'stack'
device_type = 'stack'
else:
nf = device_type = None
unit_transistor = Transistor(device_type=device_type,
nf=parameters[nf],
nfin=4,
model_name=parameters['real_inst_type'])
def find_ports(p, i):
d = {}
for (k, v) in p.items():
for t in v:
if t[0] == i:
d[t[1]] = k
return d
p1 = find_ports(ports, 'M1')
p = {1: p1}
m = {1: parameters['m']}
p2 = find_ports(ports, 'M2')
if len(p2) > 1:
m[2] = parameters['m']
p[2] = p2
transistor_array = TransistorArray(unit_transistor=unit_transistor,
m=m,
ports=p,
n_rows=x_cells)
# TODO: All of above goes away when TransistorArray is passed to mos_array as shown below
#################################################################################################
self.mos_array(transistor_array, **parameters)
def test_zero():
cv = CanvasPDK()
ox = oy = 0
track_pattern = {'G': [6], 'S': [4], 'D': [2]}
for nfin in range(1, 9):
ox = 0
for model_name in ['n', 'p']:
for device_type in ["stack", "parallel"]:
for nf in [2, 4, 6]:
mg = MOS()
tx = Transistor(model_name=model_name,
nf=nf,
nfin=nfin,
device_type=device_type)
data = mg.mos(tx, track_pattern=track_pattern)
place(cv, data, ox, oy)
ox += data['bbox'][2]
oy += data['bbox'][3]
compare_with_golden("test_transistor_0", cv)
def mos_array_temporary_wrapper(self, x_cells, y_cells, pattern, vt_type, ports, **parameters):
logger_func(f'x_cells={x_cells}, y_cells={y_cells}, pattern={pattern}, ports={ports}, parameters={parameters}')
#################################################################################################
# TODO: All of below goes away when TransistorArray is passed to mos_array as shown below
for key in ['M', 'real_inst_type']:
assert key in parameters, f'Missing transistor parameter {key}'
assert 'NF' or 'STACK' in parameters, f'Missing transistor parameter nf or stack'
if 'STACK' in parameters and int(parameters['STACK']) > 1:
nf = 'STACK'
device_type = 'stack'
elif 'NF' in parameters and int(parameters['NF']) > 1:
nf = 'NF'
device_type = 'parallel'
else:
nf = device_type = None
assert False, f'Either nf>1 or stack>1 parameter should be defined {parameters}'
if 'W' in parameters:
nfin = int(float(parameters['W']) * 1e10) // self.pdk['Fin']['Pitch']
# w in the netlist is the effective total width for a single transistor
nfin = nfin // int(parameters[nf])
elif 'NFIN' in parameters:
nfin = int(parameters['NFIN'])
else:
assert False, f'Either nfin or w parameter should be defined {parameters}'
unit_transistor = Transistor(device_type=device_type,
nf=int(parameters[nf]),
nfin=nfin,
model_name=parameters['real_inst_type'].lower())
def find_ports(p, i):
d = {}
for (k, v) in p.items():
for t in v:
if t[0] == i:
d[t[1]] = k
return d
p1 = find_ports(ports, 'M1')
p = {1: p1}
m = {1: int(parameters['M'])}
p2 = find_ports(ports, 'M2')
if len(p2) > 1:
m[2] = int(parameters['M'])
p[2] = p2
self.transistor_array = TransistorArray(
unit_transistor=unit_transistor,
m=m,
ports=p,
n_rows=y_cells
)
# TODO: All of above goes away when TransistorArray is passed to mos_array as shown below
#################################################################################################
m = 2*int(parameters['M']) if pattern > 0 else int(parameters['M'])
self.n_row, self.n_col = self.validate_array(m, y_cells, x_cells)
logger_func(f'x_cells={self.n_col}, y_cells={self.n_row} after legalization')
if self.n_row * self.n_col != m:
assert False, f'x_cells {self.n_row} by y_cells {self.n_col} not equal to m {m}'
self.ports = ports
self.mos_array()
def test_one():
tx = Transistor(model_name='n', nf=2, nfin=4, device_type='stack')
data = mos(CanvasPDK, tx, track_pattern={'G': [6], 'D': [4], 'S': [2]})
fn = "test_transistor_1"
compare_with_golden(fn, data)
def test_six():
tx = Transistor(model_name='n', nf=4, nfin=4, device_type='stack')
data = tap(CanvasPDK, tx)
fn = "test_transistor_6"
compare_with_golden(fn, data)