def BLDCResource(*args,
uL,
uH,
vL,
vH,
wL,
wH,
sensor,
number=None,
conn=None,
attrs=None):
""" BLDC driver resource
I/O signals:
I: *L *H -- low or high impedance input of BLDC motor
I: -- enable pin
"""
io = []
io.append(Subsignal("uL", Pins(uL, dir="o", conn=conn, assert_width=1)))
io.append(Subsignal("uH", Pins(uH, dir="o", conn=conn, assert_width=1)))
io.append(Subsignal("vL", Pins(vL, dir="o", conn=conn, assert_width=1)))
io.append(Subsignal("vH", Pins(vH, dir="o", conn=conn, assert_width=1)))
io.append(Subsignal("wL", Pins(wL, dir="o", conn=conn, assert_width=1)))
io.append(Subsignal("wH", Pins(wH, dir="o", conn=conn, assert_width=1)))
io.append(
Subsignal("sensor", Pins(sensor, dir="i", conn=conn, assert_width=1)))
if attrs is not None:
io.append(attrs)
return Resource.family(*args, number, default_name="bldc", ios=io)
def StepperResource(*args, step, direction, limit, number=None,
conn=None, attrs=None):
""" The enable pin is currently activated via the Linux host
I/O signals:
O: step -- pin for step pulse
O: dir -- rotating direction of motor
I: limit -- limit switch to detect end movement
"""
io = []
io.append(Subsignal("step", Pins(step, dir="o",
conn=conn, assert_width=1)))
io.append(Subsignal("dir", Pins(direction, dir="o",
conn=conn, assert_width=1)))
io.append(Subsignal("limit", Pins(limit, dir="i",
conn=conn, assert_width=1)))
if attrs is not None:
io.append(attrs)
return Resource.family(*args, number, default_name="stepper", ios=io)
def LaserscannerResource(*args, laser0, laser1,
photodiode,
number=None,
conn=None, attrs=None):
""" Resource for laser scanner
The enable pin is currently activated via the Linux host
I/O signals:
O: laser0 -- laser channel 0
O: laser1 -- laser channel 1
I: photodiode -- photodiode used to measure position of laser
"""
io = []
io.append(Subsignal("laser0", Pins(laser0, dir="o",
conn=conn, assert_width=1)))
io.append(Subsignal("laser1", Pins(laser1, dir="o",
conn=conn, assert_width=1)))
io.append(Subsignal("photodiode",
Pins(photodiode, dir="i", conn=conn, assert_width=1)))
if attrs is not None:
io.append(attrs)
return Resource.family(*args, number, default_name="laserscanner", ios=io)
def ULPIResource(name, data_sites, clk_site, dir_site, nxt_site, stp_site, reset_site, extras=(), attrs=None):
""" Generates a set of resources for a ULPI-connected USB PHY. """
attrs = Attrs() if attrs is None else attrs
return Resource(name, 0,
Subsignal("data", Pins(data_sites, dir="io")),
Subsignal("clk", Pins(clk_site, dir="i" ), Clock(60e6)),
Subsignal("dir", Pins(dir_site, dir="i" )),
Subsignal("nxt", Pins(nxt_site, dir="i" )),
Subsignal("stp", Pins(stp_site, dir="o" )),
Subsignal("rst", Pins(reset_site, dir="o" )),
attrs
)
class USB2SnifferPlatform(Xilinx7SeriesPlatform, LUNAPlatform):
""" Board description for OpenVizsla USB analyzer. """
name = "LambdaConcept USB2Sniffer"
device = "xc7a35t"
package = "fgg484"
speed = "1"
default_clk = "clk100"
# Provide the type that'll be used to create our clock domains.
clock_domain_generator = StubClockDomainGenerator
# We only have a single PHY; so use it directly.
default_usb_connection = "target_phy"
#
# I/O resources.
#
resources = [
Resource("clk100", 0, Pins("J19"), Attrs(IOStandard="LVCMOS33")),
Resource("led", 0, PinsN("W1"), Attrs(IOStandard="LVCMOS33")),
Resource("led", 1, PinsN("Y2"), Attrs(IOStandard="LVCMOS33")),
Resource("rgb_led", 0,
Subsignal("r", PinsN("W2")),
Subsignal("g", PinsN("Y1")),
Subsignal("b", PinsN("W1")),
Attrs(IOStandard="LVCMOS33"),
),
Resource("rgb_led", 1,
Subsignal("r", PinsN("AA1")),
Subsignal("g", PinsN("AB1")),
Subsignal("b", PinsN("Y2")),
Attrs(IOStandard="LVCMOS33"),
),
Resource("serial", 0,
Subsignal("tx", Pins("U21")), # FPGA_GPIO0
Subsignal("rx", Pins("T21")), # FPGA_GPIO1
Attrs(IOStandard="LVCMOS33"),
),
Resource("ddram", 0,
Subsignal("a", Pins(
"M2 M5 M3 M1 L6 P1 N3 N2"
"M6 R1 L5 N5 N4 P2 P6"),
Attrs(IOStandard="SSTL15")),
Subsignal("ba", Pins("L3 K6 L4"), Attrs(IOStandard="SSTL15")),
Subsignal("ras_n", Pins("J4"), Attrs(IOStandard="SSTL15")),
Subsignal("cas_n", Pins("K3"), Attrs(IOStandard="SSTL15")),
Subsignal("we_n", Pins("L1"), Attrs(IOStandard="SSTL15")),
Subsignal("dm", Pins("G3 F1"), Attrs(IOStandard="SSTL15")),
Subsignal("dq", Pins(
"G2 H4 H5 J1 K1 H3 H2 J5"
"E3 B2 F3 D2 C2 A1 E2 B1"),
Attrs(IOStandard="SSTL15", IN_TERM="UNTUNED_SPLIT_50")),
Subsignal("dqs_p", Pins("K2 E1"), Attrs(IOStandard="DIFF_SSTL15")),
Subsignal("dqs_n", Pins("J2 D1"), Attrs(IOStandard="DIFF_SSTL15")),
Subsignal("clk_p", Pins("P5"), Attrs(IOStandard="DIFF_SSTL15")),
Subsignal("clk_n", Pins("P4"), Attrs(IOStandard="DIFF_SSTL15")),
Subsignal("cke", Pins("J6"), Attrs(IOStandard="SSTL15")),
Subsignal("odt", Pins("K4"), Attrs(IOStandard="SSTL15")),
Subsignal("reset_n", Pins("G1"), Attrs(IOStandard="SSTL15")),
Attrs(SLEW="FAST"),
),
Resource("flash", 0,
Subsignal("cs_n", Pins("T19")),
Subsignal("mosi", Pins("P22")),
Subsignal("miso", Pins("R22")),
Subsignal("vpp", Pins("P21")),
Subsignal("hold", Pins("R21")),
Attrs(IOStandard="LVCMOS33")
),
Resource("usb_fifo_clock", 0, Pins("D17"), Attrs(IOStandard="LVCMOS33")),
Resource("usb_fifo", 0,
Subsignal("rst", Pins("K22")),
Subsignal("data", Pins("A16 F14 A15 F13 A14 E14 A13 E13 B13 C15 C13 C14 B16 E17 B15 F16"
"A20 E18 B20 F18 D19 D21 E19 E21 A21 B21 A19 A18 F20 F19 B18 B17")),
Subsignal("be", Pins("K16 L16 G20 H20")),
Subsignal("rxf_n", Pins("M13")),
Subsignal("txe_n", Pins("L13")),
Subsignal("rd_n", Pins("K19")),
Subsignal("wr_n", Pins("M15")),
Subsignal("oe_n", Pins("L21")),
Subsignal("siwua", Pins("M16")),
Attrs(IOStandard="LVCMOS33", SLEW="FAST")
),
Resource("ulpi_sw", 0,
Subsignal("s", Pins("Y8", dir="o")),
Subsignal("oe", PinsN("Y9", dir="o")),
Attrs(IOStandard="LVCMOS33"),
),
# Host PHY -- connects directly to the host port.
ULPIResource("target_phy",
data_sites="AB18 AA18 AA19 AB20 AA20 AB21 AA21 AB22",
clk_site="W19",
dir_site="W21", stp_site="Y22", nxt_site="W22", reset_site="V20",
attrs=Attrs(IOStandard="LVCMOS33", SLEW="FAST")
),
# Target PHY -- connects via a switch to the target port.
ULPIResource("sideband_phy",
data_sites="AB2 AA3 AB3 Y4 AA4 AB5 AA5 AB6",
clk_site="V4",
dir_site="AB7", stp_site="AA6", nxt_site="AB8", reset_site="AA8",
attrs=Attrs(IOStandard="LVCMOS33", SLEW="FAST")
)
]
connectors = []
def toolchain_program(self, products, name):
xc3sprog = os.environ.get("XC3SPROG", "xc3sprog")
with products.extract("{}.bit".format(name)) as bitstream_file:
subprocess.check_call([xc3sprog, "-c", "ft4232h", bitstream_file])
class ECPIX5PlatformRev02(LatticeECP5Platform, LUNAPlatform):
name = "ECPIX-5 R02"
device = "LFE5UM5G-85F"
package = "BG554"
speed = "8"
default_clk = "clk100"
default_rst = "rst"
# Provide the type that'll be used to create our clock domains.
clock_domain_generator = StubClockDomainGenerator
# We only have a single PHY; so use it directly.
default_usb_connection = "ulpi"
resources = [
Resource("rst", 0, PinsN("AB1", dir="i"), Attrs(IO_TYPE="LVCMOS33")),
Resource("clk100", 0, Pins("K23", dir="i"), Clock(100e6), Attrs(IO_TYPE="LVCMOS33")),
# LEDs
Resource("rgb_led", 0,
Subsignal("r", Pins("U21")),
Subsignal("g", Pins("W21")),
Subsignal("b", Pins("T24")),
Attrs(IO_TYPE="LVCMOS33"),
),
Resource("rgb_led", 1,
Subsignal("r", Pins("T23")),
Subsignal("g", Pins("R21")),
Subsignal("b", Pins("T22")),
Attrs(IO_TYPE="LVCMOS33"),
),
Resource("rgb_led", 2,
Subsignal("r", Pins("P21")),
Subsignal("g", Pins("R23")),
Subsignal("b", Pins("P22")),
Attrs(IO_TYPE="LVCMOS33"),
),
Resource("rgb_led", 3,
Subsignal("r", Pins("K21")),
Subsignal("g", Pins("K24")),
Subsignal("b", Pins("M21")),
Attrs(IO_TYPE="LVCMOS33"),
),
Resource("uart", 0,
Subsignal("rx", Pins("R26", dir="i")),
Subsignal("tx", Pins("R24", dir="o")),
Attrs(IO_TYPE="LVCMOS33", PULLMODE="UP")
),
Resource("eth_rgmii", 0,
Subsignal("rst", PinsN("C13", dir="o")),
Subsignal("mdio", Pins("A13", dir="io")),
Subsignal("mdc", Pins("C11", dir="o")),
Subsignal("tx_clk", Pins("A12", dir="o")),
Subsignal("tx_ctrl", Pins("C9", dir="o")),
Subsignal("tx_data", Pins("D8 C8 B8 A8", dir="o")),
Subsignal("rx_clk", Pins("E11", dir="i")),
Subsignal("rx_ctrl", Pins("A11", dir="i")),
Subsignal("rx_data", Pins("B11 A10 B10 A9", dir="i")),
Attrs(IO_TYPE="LVCMOS33")
),
Resource("eth_int", 0, PinsN("B13", dir="i"), Attrs(IO_TYPE="LVCMOS33")),
Resource("ddr3", 0,
Subsignal("clk", DiffPairs("H3", "J3", dir="o"), Attrs(IO_TYPE="SSTL135D_I")),
Subsignal("clk_en", Pins("P1", dir="o")),
Subsignal("we", PinsN("R3", dir="o")),
Subsignal("ras", PinsN("T3", dir="o")),
Subsignal("cas", PinsN("P2", dir="o")),
Subsignal("a", Pins("T5 M3 L3 V6 K2 W6 K3 L1 H2 L2 N1 J1 M1 K1", dir="o")),
Subsignal("ba", Pins("U6 N3 N4", dir="o")),
Subsignal("dqs", DiffPairs("V4 V1", "U5 U2", dir="io"), Attrs(IO_TYPE="SSTL135D_I")),
Subsignal("dq", Pins("T4 W4 R4 W5 R6 P6 P5 P4 R1 W3 T2 V3 U3 W1 T1 W2", dir="io")),
Subsignal("dm", Pins("J4 H5", dir="o")),
Subsignal("odt", Pins("L2", dir="o")),
Attrs(IO_TYPE="SSTL135_I")
),
Resource("hdmi", 0,
Subsignal("rst", PinsN("N6", dir="o")),
Subsignal("scl", Pins("C17", dir="io")),
Subsignal("sda", Pins("E17", dir="io")),
Subsignal("pclk", Pins("C1", dir="o")),
Subsignal("vsync", Pins("A4", dir="o")),
Subsignal("hsync", Pins("B4", dir="o")),
Subsignal("de", Pins("A3", dir="o")),
Subsignal("d",
Subsignal("b", Pins("AD25 AC26 AB24 AB25 B3 C3 D3 B1 C2 D2 D1 E3", dir="o")),
Subsignal("g", Pins("AA23 AA22 AA24 AA25 E1 F2 F1 D17 D16 E16 J6 H6", dir="o")),
Subsignal("r", Pins("AD26 AE25 AF25 AE26 E10 D11 D10 C10 D9 E8 H5 J4", dir="o")),
),
Subsignal("mclk", Pins("E19", dir="o")),
Subsignal("sck", Pins("D6", dir="o")),
Subsignal("ws", Pins("C6", dir="o")),
Subsignal("i2s", Pins("A6 B6 A5 C5", dir="o")),
Subsignal("int", PinsN("C4", dir="i")),
Attrs(IO_TYPE="LVTTL33")
),
Resource("sata", 0,
Subsignal("tx", DiffPairs("AD16", "AD17", dir="o")),
Subsignal("rx", DiffPairs("AF15", "AF16", dir="i")),
Attrs(IO_TYPE="LVDS")
),
ULPIResource("ulpi",
data_sites="M26 L25 L26 K25 K26 J23 P25 H25",
clk_site="H24",
dir_site="F22", stp_site="H23", nxt_site="F23", reset_site="E23",
attrs=Attrs(IO_TYPE="LVCMOS33")
),
Resource("usbc_cfg", 0,
Subsignal("scl", Pins("D24", dir="io")),
Subsignal("sda", Pins("C24", dir="io")),
Subsignal("dir", Pins("B23", dir="i")),
Subsignal("id", Pins("D23", dir="i")),
Subsignal("int", PinsN("B24", dir="i")),
Attrs(IO_TYPE="LVCMOS33")
),
Resource("usbc_mux", 0,
Subsignal("en", Pins("C23", dir="oe")),
Subsignal("amsel", Pins("B26", dir="oe")),
Subsignal("pol", Pins("D26", dir="o")),
#Subsignal("lna", DiffPairs( "AF9", "AF10", dir="i"), Attrs(IO_TYPE="LVCMOS18D")),
#Subsignal("lnb", DiffPairs("AD10", "AD11", dir="o"), Attrs(IO_TYPE="LVCMOS18D")),
#Subsignal("lnc", DiffPairs( "AD7", "AD8", dir="o"), Attrs(IO_TYPE="LVCMOS18D")),
#Subsignal("lnd", DiffPairs( "AF6", "AF7", dir="i"), Attrs(IO_TYPE="LVCMOS18D")),
Attrs(IO_TYPE="LVCMOS33")
),
# Compatibility aliases.
Resource("led", 0, Pins("W21", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 1, Pins("R21", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 2, Pins("R23", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 3, Pins("K24", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("user_io", 0, Pins("T25")),
Resource("user_io", 1, Pins("U25")),
Resource("user_io", 2, Pins("U24")),
Resource("user_io", 3, Pins("V24")),
]
connectors = [
Connector("pmod", 0, "T25 U25 U24 V24 - - T26 U26 V26 W26 - -"),
Connector("pmod", 1, "U23 V23 U22 V21 - - W25 W24 W23 W22 - -"),
Connector("pmod", 2, "J24 H22 E21 D18 - - K22 J21 H21 D22 - -"),
Connector("pmod", 3, " E4 F4 E6 H4 - - F3 D4 D5 F5 - -"),
Connector("pmod", 4, "E26 D25 F26 F25 - - A25 A24 C26 C25 - -"),
Connector("pmod", 5, "D19 C21 B21 C22 - - D21 A21 A22 A23 - -"),
Connector("pmod", 6, "C16 B17 C18 B19 - - A17 A18 A19 C19 - -"),
Connector("pmod", 7, "D14 B14 E14 B16 - - C14 A14 A15 A16 - -"),
]
@property
def file_templates(self):
return {
**super().file_templates,
"{{name}}-openocd.cfg": r"""
interface ftdi
ftdi_vid_pid 0x0403 0x6010
ftdi_channel 0
ftdi_layout_init 0xfff8 0xfffb
reset_config none
adapter_khz 25000
jtag newtap ecp5 tap -irlen 8 -expected-id 0x81113043
"""
}
def toolchain_program(self, products, name):
openocd = os.environ.get("OPENOCD", "openocd")
with products.extract("{}-openocd.cfg".format(name), "{}.svf".format(name)) \
as (config_filename, vector_filename):
subprocess.check_call([openocd,
"-f", config_filename,
"-c", "transport select jtag; init; svf -quiet {}; exit".format(vector_filename)
])
class Firestarter(LatticeICE40Platform, platform):
'''Kicad board available at
https://github.com/hstarmans/firestarter/
'''
name = "firestarter"
ic_dev_nr = 1 # spi connection
ic_address = 0x28 # spi address
enable_pin = 17 # enable pin for stepper motors
reset_pin = 26 # can be used to reset FPGA
laser_bits = 1 # enables adding pwm to laser (not widely tested)
poldegree = 2 # degree of polynomal to execute move, see movement.py
stepspermm = {'x': 76.2, 'y': 76.2, 'z': 1600}
laser_axis = 'y'
motors = len(stepspermm.keys())
memdepth = 256
device = 'iCE40UP5K'
package = 'SG48'
default_clk = "SB_HFOSC"
# This division setting selects the internal oscillator speed:
# 0: 48MHz, 1: 24MHz, 2: 12MHz, 3: 6MHz.
clks = {0: 48, 1: 24, 2: 12, 3: 6}
hfosc_div = 2
laser_var = {
'RPM': 2000,
'SPINUP_TIME': 1.5,
'STABLE_TIME': 1.125,
'FACETS': 4,
'CRYSTAL_HZ': clks[hfosc_div] * 1E6,
'LASER_HZ': 100E3,
'END%': 0.7,
'START%': 0.35,
'SINGLE_LINE': False,
'SINGLE_FACET': False,
'DIRECTION': 0
}
resources = [
Resource("clk13", 0, Pins("35", dir="i"), Clock(13.56e6),
Attrs(GLOBAL=True, IO_STANDARD="SB_LVCMOS")),
# TODO: replace with RGB led resource
# added fix for pins
*LEDResources(pins='39 40 41',
invert=True,
attrs=Attrs(IO_STANDARD="SB_LVCMOS")),
# NOTE: there is a proper resource in nmigen_boards
# this is used as it is also done by luna
Resource("debug_spi", 0, Subsignal("sck", Pins("18", dir="i")),
Subsignal("sdi", Pins("21", dir="i")),
Subsignal("sdo", Pins("19", dir="o")),
Subsignal("cs", PinsN("13", dir="i")),
Attrs(IO_STANDARD="SB_LVCMOS")),
# BLDC driver
BLDCResource(number=0,
uL="25",
uH="26",
vL="9",
vH="23",
wL="27",
wH="32",
sensor0="34",
sensor1="36",
sensor2="37",
attrs=Attrs(IO_STANDARD="SB_LVCMOS")),
]
connectors = []
def __init__(self):
super().__init__()
platform.__init__(self)
def build(self, *args, **kwargs):
apio = True
if apio:
base = 'apio raw "which '
end = '"'
else:
base = 'which yowasp-'
end = ''
os.environ['YOSYS'] = subprocess.getoutput(base + 'yosys' + end)
os.environ['NEXTPNR_ICE40'] = \
subprocess.getoutput(base+'nextpnr-ice40'+end)
os.environ['ICEPACK'] = subprocess.getoutput(base + 'icepack' + end)
super().build(*args, **kwargs)
def toolchain_program(self, products, name, **kwargs):
with products.extract("{}.bin".format(name)) as bitstream_filename:
subprocess.check_call(['fomu-flash', '-w', bitstream_filename])
subprocess.check_call(['fomu-flash', '-r'])
class Firestarter(LatticeICE40Platform, platform):
'''Kicad board available at
https://github.com/hstarmans/firestarter/
'''
name = "firestarter"
memdepth = 256
device = 'iCE40UP5K'
package = 'SG48'
default_clk = "SB_HFOSC"
# This division setting selects the internal oscillator speed:
# 0: 48MHz, 1: 24MHz, 2: 12MHz, 3: 6MHz.
clks = {0: 48, 1: 24, 2: 12, 3: 6}
hfosc_div = 2
laser_var = {
'RPM': 2000,
'SPINUP_TIME': 1.5,
'STABLE_TIME': 1.125,
'FACETS': 4,
'CRYSTAL_HZ': clks[hfosc_div] * 1E6,
'LASER_HZ': 100E3,
'END%': 0.7,
'START%': 0.35,
'SINGLE_LINE': False,
'SINGLE_FACET': False,
'DIRECTION': 0
}
# default_clk = "clk13"
# clock_domain_generator = FirestarterDomainGenerator
resources = [
Resource("clk13", 0, Pins("35", dir="i"), Clock(13.56e6),
Attrs(GLOBAL=True, IO_STANDARD="SB_LVCMOS")),
# TODO: replace with RGB led resource
*LEDResources(pins='39 40 41',
invert=True,
attrs=Attrs(IO_STANDARD="SB_LVCMOS")),
# NOTE: there is a proper resource in nmigen_boards
# this is used as it is also done by luna
Resource("debug_spi", 0, Subsignal("sck", Pins("18", dir="i")),
Subsignal("sdi", Pins("21", dir="i")),
Subsignal("sdo", Pins("19", dir="o")),
Subsignal("cs", PinsN("13", dir="i")),
Attrs(IO_STANDARD="SB_LVCMOS")),
# Laserscanner resource
LaserscannerResource(number=0,
laser0='31',
laser1='28',
photodiode='38',
attrs=Attrs(IO_STANDARD="SB_LVCMOS")),
# BLDC driver
BLDCResource(number=0,
uL="25",
uH="26",
vL="9",
vH="23",
wL="27",
wH="32",
sensor0="34",
sensor1="36",
sensor2="37",
attrs=Attrs(IO_STANDARD="SB_LVCMOS")),
# x-stepper
StepperResource(number=0,
step="6",
direction="4",
limit="3",
attrs=Attrs(IO_STANDARD="SB_LVCMOS")),
# y-stepper
StepperResource(number=1,
step="2",
direction="48",
limit="47",
attrs=Attrs(IO_STANDARD="SB_LVCMOS")),
# z-stepper
StepperResource(number=2,
step="46",
direction="45",
limit="44",
attrs=Attrs(IO_STANDARD="SB_LVCMOS"))
]
connectors = []
def __init__(self, micropython=False):
LatticeICE40Platform.__init__(self)
platform.__init__(self, micropython)
def build(self, *args, **kwargs):
if pltf.system() == 'Windows':
search_command = 'where'
else:
search_command = 'which'
base = f'{search_command} yowasp-'
end = ''
# yowasp-yosys doesn't work
# os.environ['YOSYS'] = subprocess.getoutput(base+'yosys'+end)
os.environ['NEXTPNR_ICE40'] = \
subprocess.getoutput(base+'nextpnr-ice40'+end)
os.environ['ICEPACK'] = subprocess.getoutput(base + 'icepack' + end)
super().build(*args, **kwargs)
def toolchain_program(self, products, name, **kwargs):
with products.extract("{}.bin".format(name)) as bitstream_filename:
subprocess.check_call(['fomu-flash', '-w', bitstream_filename])
subprocess.check_call(['fomu-flash', '-r'])
class LUNAPlatformRev0D1(LUNAApolloPlatform, LatticeECP5Platform):
""" Board description for the pre-release r0.1 revision of LUNA. """
name = "LUNA r0.1"
device = "LFE5U-12F"
package = "BG256"
# Different r0.1s have been produced with different speed grades; but there's
# some evidence (and some testing) that all of them are effectively speed grade 8.
# It's possible all ECP5 binning is artificial.
#
# We'll assume speed grade 8 unless the user overrides it on the command line.
speed = os.getenv("LUNA_SPEED_GRADE", "8")
default_clk = "clk_60MHz"
# Provide the type that'll be used to create our clock domains.
clock_domain_generator = LunaECP5DomainGenerator
# By default, assume we'll be connecting via our target PHY.
default_usb_connection = "target_phy"
#
# Default clock frequencies for each of our clock domains.
#
# Different revisions have different FPGA speed grades, and thus the
# default frequencies will vary.
#
DEFAULT_CLOCK_FREQUENCIES_MHZ = {"fast": 240, "sync": 120, "usb": 60}
#
# Preferred DRAM bus I/O (de)-skewing constants.
#
ram_timings = dict(clock_skew=64)
# Provides any platform-specific ULPI registers necessary.
# This is the spot to put any platform-specific vendor registers that need
# to be written.
ulpi_extra_registers = {
0x39: 0b000110 # USB3343: swap D+ and D- to match the LUNA boards
}
#
# I/O resources.
#
resources = [
# Primary, discrete 60MHz oscillator.
Resource("clk_60MHz", 0, Pins("A8", dir="i"), Clock(60e6),
Attrs(IO_TYPE="LVCMOS33")),
# Connection to our SPI flash; can be used to work with the flash
# from e.g. a bootloader.
Resource(
"spi_flash",
0,
# SCK is on pin 9; but doesn't have a traditional I/O buffer.
# Instead, we'll need to drive a clock into a USRMCLK instance.
# See interfaces/flash.py for more information.
Subsignal("sdi", Pins("T8", dir="o")),
Subsignal("sdo", Pins("T7", dir="i")),
# In r0.1, the chip select line can either be driven by the FPGA
# or by the Debug Controller. Accordingly, we'll mark the line as
# bidirectional, and let the user decide.
Subsignal("cs", PinsN("N8", dir="io")),
Attrs(IO_TYPE="LVCMOS33")),
#
# Note: r0.1 has a DFM issue that makes it difficult to solder a BGA with
# reliable connections on the intended SCK pin (P12), and lacks a CS pin on the
# debug SPI; which seems like a silly omission.
#
# Accordingly, we're mapping the debug SPI and UART over the same pins, as the
# microcontroller can use either.
#
# UART connected to the debug controller; can be routed to a host via CDC-ACM.
Resource("uart", 0, Subsignal("rx", Pins("R14", dir="i")),
Subsignal("tx", Pins("T14", dir="o")),
Attrs(IO_TYPE="LVCMOS33")),
# SPI bus connected to the debug controller, for simple register exchanges.
# Note that the Debug Controller is the master on this bus.
Resource("debug_spi", 0, Subsignal("sck", Pins("R14", dir="i")),
Subsignal("sdi", Pins("P13", dir="i")),
Subsignal("sdo", Pins("P11", dir="o")),
Subsignal("cs", PinsN("T14", dir="i")),
Attrs(IO_TYPE="LVCMOS33")),
# FPGA-connected LEDs.
Resource("led", 5, PinsN("P15", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 4, PinsN("N16", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 3, PinsN("M15", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 2, PinsN("M16", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 1, PinsN("L15", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 0, PinsN("L16", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
# USB PHYs
ULPIResource("sideband_phy",
data_sites="R2 R1 P2 P1 N1 M2 M1 L2",
clk_site="R4",
dir_site="T3",
nxt_site="T2",
stp_site="T4",
reset_site="R3"),
ULPIResource("host_phy",
data_sites="G2 G1 F2 F1 E1 D1 C1 B1",
clk_site="K2",
dir_site="J1",
nxt_site="H2",
stp_site="J2",
reset_site="K1"),
ULPIResource("target_phy",
data_sites="D16 E15 E16 F15 F16 G15 J16 K16",
clk_site="B15",
dir_site="C15",
nxt_site="C16",
stp_site="B16",
reset_site="G16"),
# Target port power switching
# Note: the r0.1 boards that have been produced incorrectly use the AP22814B
# instead of the AP22814A. This inverts the load-switch enables.
#
Resource("power_a_port", 0, PinsN("C14", dir="o"),
Attrs(IO_TYPE="LVCMOS33")),
Resource("pass_through_vbus", 0, PinsN("D14", dir="o"),
Attrs(IO_TYPE="LVCMOS33")),
Resource("target_vbus_fault", 0, Pins("K15", dir="i"),
Attrs(IO_TYPE="LVCMOS33")),
# HyperRAM (1V8 domain).
Resource(
"ram",
0,
# Note: our clock uses the pseudo-differential I/O present on the top tiles.
# This requires a recent version of trellis+nextpnr. If your build complains
# that LVCMOS18D is an invalid I/O type, you'll need to upgrade.
Subsignal("clk", DiffPairs("B14", "A15", dir="o"),
Attrs(IO_TYPE="LVCMOS18D")),
Subsignal("dq", Pins("A11 B10 B12 A12 B11 A10 B9 A9", dir="io")),
Subsignal("rwds", Pins("A13", dir="io")),
Subsignal("cs", PinsN("A14", dir="o")),
Subsignal("reset", PinsN("B13", dir="o")),
Attrs(IO_TYPE="LVCMOS18", SLEWRATE="FAST")),
# User I/O connections.
Resource("user_io", 0, Pins("A5", dir="io"),
Attrs(IO_TYPE="LVCMOS33", SLEWRATE="FAST")),
Resource("user_io", 1, Pins("A4", dir="io"),
Attrs(IO_TYPE="LVCMOS33", SLEWRATE="FAST")),
Resource("user_io", 2, Pins("A3", dir="io"),
Attrs(IO_TYPE="LVCMOS33", SLEWRATE="FAST")),
Resource("user_io", 3, Pins("A2", dir="io"),
Attrs(IO_TYPE="LVCMOS33", SLEWRATE="FAST")),
]
connectors = [
# User I/O connector.
Connector("user_io", 0, """
A5 - A2
A4 - A3
""")
]
def toolchain_prepare(self, fragment, name, **kwargs):
overrides = {
'ecppack_opts':
'--compress --idcode {} --freq 38.8'.format(0x21111043)
}
return super().toolchain_prepare(fragment, name, **overrides, **kwargs)