def StackSwap(self, ctx):
stsw_ptr = ctx.cpu.r_reg(REG_A0)
stsw = AccessStruct(ctx.mem, StackSwapStruct, struct_addr=stsw_ptr)
# get new stack values
new_lower = stsw.r_s("stk_Lower")
new_upper = stsw.r_s("stk_Upper")
new_pointer = stsw.r_s("stk_Pointer")
# retrieve current (old) stack
old_lower = self.stk_lower
old_upper = self.stk_upper
old_pointer = ctx.cpu.r_reg(REG_A7) # addr of sys call return
# get adress of callee
callee = ctx.mem.r32(old_pointer)
# is a label attached to new addr
if ctx.label_mgr:
label = ctx.label_mgr.get_label(new_lower)
if label is not None:
label.name = label.name + "=Stack"
# we report the old stack befor callee
old_pointer += 4
log_exec.info(
"StackSwap: old(lower=%06x,upper=%06x,ptr=%06x) new(lower=%06x,upper=%06x,ptr=%06x)"
% (old_lower, old_upper, old_pointer, new_lower, new_upper,
new_pointer))
stsw.w_s("stk_Lower", old_lower)
stsw.w_s("stk_Upper", old_upper)
stsw.w_s("stk_Pointer", old_pointer)
self.stk_lower = new_lower
self.stk_upper = new_upper
# put callee's address on new stack
new_pointer -= 4
ctx.mem.w32(new_pointer, callee)
# activate new stack
ctx.cpu.w_reg(REG_A7, new_pointer)
def mem_access_invalid_node_test():
mem = MockMemory()
a = AccessStruct(mem, NodeStruct, 0x42)
with pytest.raises(KeyError):
a.w_s("bla", 12)
with pytest.raises(KeyError):
a.r_s("blub")
def mem_access_invalid_node_test():
mem = MockMemory()
a = AccessStruct(mem, NodeStruct, 0x42)
with pytest.raises(KeyError):
a.w_s('bla', 12)
with pytest.raises(KeyError):
a.r_s('blub')
def read(self, ctx, mh_addr):
self.addr = mh_addr
mh = AccessStruct(ctx.mem, MemHeaderStruct, mh_addr)
self.first = mh.r_s("mh_First")
self.lower = mh.r_s("mh_Lower")
self.upper = mh.r_s("mh_Upper")
self.free = mh.r_s("mh_Free")
self.total = self.upper - self.lower
def mem_access_rw_field_node_test():
mem = MockMemory()
a = AccessStruct(mem, NodeStruct, 0x42)
a.w_s('ln_Succ', 42)
a.w_s('ln_Pred', 21)
a.w_s('ln_Pri', -27)
assert a.r_s('ln_Succ') == 42
assert a.r_s('ln_Pred') == 21
assert a.r_s('ln_Pri') == -27
def mem_access_rw_field_node_test():
mem = MockMemory()
a = AccessStruct(mem, NodeStruct, 0x42)
a.w_s("ln_Succ", 42)
a.w_s("ln_Pred", 21)
a.w_s("ln_Pri", -27)
assert a.r_s("ln_Succ") == 42
assert a.r_s("ln_Pred") == 21
assert a.r_s("ln_Pri") == -27
def mem_access_rw_field_node_test():
mem = MockMemory()
a = AccessStruct(mem, NodeStruct, 0x42)
a.w_s('ln_Succ', 42)
a.w_s('ln_Pred', 21)
a.w_s('ln_Pri', -27)
assert a.r_s('ln_Succ') == 42
assert a.r_s('ln_Pred') == 21
assert a.r_s('ln_Pri') == -27
def fs_put_msg(self, port_mgr, msg_addr):
msg = AccessStruct(self.mem, MessageStruct, struct_addr=msg_addr)
dos_pkt_addr = msg.r_s("mn_Node.ln_Name")
dos_pkt = AccessStruct(self.mem,
DosPacketStruct,
struct_addr=dos_pkt_addr)
reply_port_addr = dos_pkt.r_s("dp_Port")
pkt_type = dos_pkt.r_s("dp_Type")
log_file.info(
"FS DosPacket: msg=%06x -> pkt=%06x: reply_port=%06x type=%06x",
msg_addr,
dos_pkt_addr,
reply_port_addr,
pkt_type,
)
# handle packet
if pkt_type == ord("R"): # read
fh_b_addr = dos_pkt.r_s("dp_Arg1")
buf_ptr = dos_pkt.r_s("dp_Arg2")
size = dos_pkt.r_s("dp_Arg3")
# get fh and read
fh = self.get_by_b_addr(fh_b_addr)
data = fh.read(size)
self.mem.w_block(buf_ptr, data)
got = len(data)
log_file.info(
"DosPacket: Read fh_b_addr=%06x buf=%06x len=%06x -> got=%06x fh=%s",
fh_b_addr,
buf_ptr,
size,
got,
fh,
)
dos_pkt.w_s("dp_Res1", got)
elif pkt_type == ord("W"): # write
fh_b_addr = dos_pkt.r_s("dp_Arg1")
buf_ptr = dos_pkt.r_s("dp_Arg2")
size = dos_pkt.r_s("dp_Arg3")
fh = self.get_by_b_addr(fh_b_addr)
data = self.mem.r_block(buf_ptr, size)
fh.write(data)
put = len(data)
log_file.info(
"DosPacket: Write fh=%06x buf=%06x len=%06x -> put=%06x fh=%s",
fh_b_addr,
buf_ptr,
size,
put,
fh,
)
dos_pkt.w_s("dp_Res1", put)
else:
raise UnsupportedFeatureError("Unsupported DosPacket: type=%d" %
pkt_type)
# do reply
if not port_mgr.has_port(reply_port_addr):
port_mgr.register_port(reply_port_addr)
port_mgr.put_msg(reply_port_addr, msg_addr)
def RemTail(self, ctx):
list_addr = ctx.cpu.r_reg(REG_A0)
l = AccessStruct(ctx.mem, ListStruct, list_addr)
node_addr = l.r_s("lh_TailPred")
n = AccessStruct(ctx.mem, NodeStruct, node_addr)
succ = n.r_s("ln_Succ")
pred = n.r_s("ln_Pred")
if pred == 0:
log_exec.info("RemTail(%06x): null" % list_addr)
return 0
AccessStruct(ctx.mem, NodeStruct, pred).w_s("ln_Succ", succ)
AccessStruct(ctx.mem, NodeStruct, succ).w_s("ln_Pred", pred)
log_exec.info("RemTail(%06x): %06x" % (list_addr, node_addr))
return node_addr
def mem_access_rw_sub_field_task_test():
mem = MockMemory()
a = AccessStruct(mem, TaskStruct, 0x42)
a.w_s('tc_Node.ln_Succ', 42)
a.w_s('tc_Node.ln_Pred', 21)
assert a.r_s('tc_Node.ln_Succ') == 42
assert a.r_s('tc_Node.ln_Pred') == 21
def mem_access_rw_sub_field_task_test():
mem = MockMemory()
a = AccessStruct(mem, TaskStruct, 0x42)
a.w_s("tc_Node.ln_Succ", 42)
a.w_s("tc_Node.ln_Pred", 21)
assert a.r_s("tc_Node.ln_Succ") == 42
assert a.r_s("tc_Node.ln_Pred") == 21
def AddSemaphore(self, ctx):
addr = ctx.cpu.r_reg(REG_A1)
sstruct = AccessStruct(ctx.mem, SignalSemaphoreStruct, addr)
name_ptr = sstruct.r_s("ss_Link.ln_Name")
name = ctx.mem.r_cstr(name_ptr)
self.semaphore_mgr.AddSemaphore(addr, name)
log_exec.info("AddSemaphore(%06x,%s)" % (addr, name))
def mem_access_bptr_test():
mem = MockMemory()
a = AccessStruct(mem, MyBCPLStruct, 0x42)
# write/read addr
a.w_s("bs_TestBptr", 44)
assert a.r_s("bs_TestBptr") == 44
# check auto converted baddr
assert mem.r32(0x42) == 11
def put_msg(self, port_mgr, msg_addr):
msg = AccessStruct(self.mem,MessageStruct,struct_addr=msg_addr)
dos_pkt_addr = msg.r_s("mn_Node.ln_Name")
dos_pkt = AccessStruct(self.mem,DosPacketStruct,struct_addr=dos_pkt_addr)
reply_port_addr = dos_pkt.r_s("dp_Port")
pkt_type = dos_pkt.r_s("dp_Type")
log_file.info("DosPacket: msg=%06x -> pkt=%06x: reply_port=%06x type=%06x", msg_addr, dos_pkt_addr, reply_port_addr, pkt_type)
# handle packet
if pkt_type == ord('R'): # read
fh_b_addr = dos_pkt.r_s("dp_Arg1")
buf_ptr = dos_pkt.r_s("dp_Arg2")
size = dos_pkt.r_s("dp_Arg3")
# get fh and read
fh = self.get_by_b_addr(fh_b_addr)
data = fh.read(size)
self.mem.w_block(buf_ptr, data)
got = len(data)
log_file.info("DosPacket: Read fh_b_addr=%06x buf=%06x len=%06x -> got=%06x fh=%s", fh_b_addr, buf_ptr, size, got, fh)
dos_pkt.w_s("dp_Res1", got)
elif pkt_type == ord('W'): # write
fh_b_addr = dos_pkt.r_s("dp_Arg1")
buf_ptr = dos_pkt.r_s("dp_Arg2")
size = dos_pkt.r_s("dp_Arg3")
fh = self.get_by_b_addr(fh_b_addr)
data = self.mem.r_block(buf_ptr, size)
fh.write(data)
put = len(data)
log_file.info("DosPacket: Write fh=%06x buf=%06x len=%06x -> put=%06x fh=%s", fh_b_addr, buf_ptr, size, put, fh)
dos_pkt.w_s("dp_Res1", put)
else:
raise UnsupportedFeatureError("Unsupported DosPacket: type=%d" % pkt_type)
# do reply
if not port_mgr.has_port(reply_port_addr):
port_mgr.register_port(reply_port_addr)
port_mgr.put_msg(reply_port_addr, msg_addr)
def volume_name_of_lock(self, lock):
if lock == None:
return "SYS:"
else:
vol_addr = lock.mem.access.r_s("fl_Volume")
volnode = AccessStruct(self.mem,DosListVolumeStruct,vol_addr)
name_addr = volnode.r_s("dol_Name")
name = self.mem.access.r_bstr(name_addr) + ":"
return name
def CloseDevice(self, ctx):
io_addr = ctx.cpu.r_reg(REG_A1)
if io_addr != 0:
io = AccessStruct(ctx.mem, IORequestStruct, io_addr)
dev_addr = io.r_s("io_Device")
if dev_addr != 0:
log_exec.info("CloseDevice: %06x", dev_addr)
self.lib_mgr.close_lib(dev_addr)
io.w_s("io_Device", 0)
def Remove(self, ctx):
node_addr = ctx.cpu.r_reg(REG_A1)
n = AccessStruct(ctx.mem, NodeStruct, node_addr)
succ = n.r_s("ln_Succ")
pred = n.r_s("ln_Pred")
log_exec.info("Remove(%06x): ln_Pred=%06x ln_Succ=%06x" %
(node_addr, pred, succ))
AccessStruct(ctx.mem, NodeStruct, pred).w_s("ln_Succ", succ)
AccessStruct(ctx.mem, NodeStruct, succ).w_s("ln_Pred", pred)
return node_addr
def AddHead(self, ctx):
list_addr = ctx.cpu.r_reg(REG_A0)
node_addr = ctx.cpu.r_reg(REG_A1)
log_exec.info("AddHead(%06x, %06x)" % (list_addr, node_addr))
l = AccessStruct(ctx.mem, ListStruct, list_addr)
n = AccessStruct(ctx.mem, NodeStruct, node_addr)
n.w_s("ln_Pred", l.s_get_addr("lh_Head"))
h = l.r_s("lh_Head")
n.w_s("ln_Succ", h)
AccessStruct(ctx.mem, NodeStruct, h).w_s("ln_Pred", node_addr)
l.w_s("lh_Head", node_addr)
def console_put_msg(self, port_mgr, msg_addr):
msg = AccessStruct(self.mem, MessageStruct, struct_addr=msg_addr)
dos_pkt_addr = msg.r_s("mn_Node.ln_Name")
dos_pkt = AccessStruct(self.mem,
DosPacketStruct,
struct_addr=dos_pkt_addr)
reply_port_addr = dos_pkt.r_s("dp_Port")
pkt_type = dos_pkt.r_s("dp_Type")
log_file.info(
"Console DosPacket: msg=%06x -> pkt=%06x: reply_port=%06x type=%06x",
msg_addr,
dos_pkt_addr,
reply_port_addr,
pkt_type,
)
# fake result
dos_pkt.w_s("dp_Res1", 0)
# do reply
if not port_mgr.has_port(reply_port_addr):
port_mgr.register_port(reply_port_addr)
port_mgr.put_msg(reply_port_addr, msg_addr)
def _release_locklist(self, entry):
alist_addr = entry.access.r_s("dol_List")
entry.access.w_s("dol_List",0)
entry.alist = []
while alist_addr != 0:
alist = AccessStruct(self.mem,AssignListStruct,alist_addr)
oldlock_addr = alist.r_s("al_Lock")
oldlock = self.lock_mgr.get_by_b_addr(oldlock_addr >> 2)
self.lock_mgr.release_lock(oldlock)
entry.alist.remove(alist)
nextaddr = alist.access.r_s("al_Next")
self.alloc.free_struct(alist.mem)
alist_addr = nextaddr
def _release_locklist(self, entry):
alist_addr = entry.access.r_s("dol_List")
entry.access.w_s("dol_List",0)
entry.alist = []
while alist_addr != 0:
alist = AccessStruct(self.mem,AssignListStruct,alist_addr)
oldlock_addr = alist.r_s("al_Lock")
oldlock = self.lock_mgr.get_by_b_addr(oldlock_addr >> 2)
self.lock_mgr.release_lock(oldlock)
entry.alist.remove(alist)
nextaddr = alist.access.r_s("al_Next")
self.alloc.free_struct(alist.mem)
alist_addr = nextaddr
def read_clock_data(mem, data_ptr):
"""read Amiga ClockData and return corresponding Python datetime
return None if data is invalid
"""
data = AccessStruct(mem, ClockDataStruct, struct_addr=data_ptr)
# read date struct
sec = data.r_s('sec')
minute = data.r_s('min')
hour = data.r_s('hour')
mday = data.r_s('mday')
month = data.r_s('month')
year = data.r_s('year')
wday = data.r_s('wday')
try:
dt = datetime.datetime(year, month, mday, hour, minute, sec)
if year < 1978:
return None
if dt.weekday() != wday:
return None
return dt
except ValueError:
return None
def read_clock_data(mem, data_ptr):
"""read Amiga ClockData and return corresponding Python datetime
return None if data is invalid
"""
data = AccessStruct(mem, ClockDataStruct, struct_addr=data_ptr)
# read date struct
sec=data.r_s('sec')
minute=data.r_s('min')
hour=data.r_s('hour')
mday=data.r_s('mday')
month=data.r_s('month')
year=data.r_s('year')
wday=data.r_s('wday')
try:
dt = datetime.datetime(year, month, mday, hour, minute, sec)
if year < 1978:
return None
if dt.weekday() != wday:
return None
return dt
except ValueError:
return None
def get_by_b_addr(self, b_addr, none_if_missing=False):
if b_addr == 0:
return None
else:
raw_lock = AccessStruct(self.mem, FileLockStruct, b_addr << 2)
key = raw_lock.r_s("fl_Key")
lock_key = self.keys[key]
log_lock.debug(
"lookup key in baddr=%08x: %s -> lock_key=%r", b_addr, key, lock_key
)
lock = lock_key.find_lock_by_baddr(b_addr)
if lock:
return lock
else:
raise VamosInternalError("lock not found by b_addr?!")
def get_tag(ctx, ti_addr):
ti = AccessStruct(ctx.mem, TagItemStruct, ti_addr)
tag = ti.r_s("ti_Tag")
data = ti.r_s("ti_Data")
return tag, data
def get_tag(ctx, ti_addr):
ti = AccessStruct(ctx.mem, TagItemStruct, ti_addr)
tag = ti.r_s("ti_Tag")
data = ti.r_s("ti_Data")
return tag, data
def read(self, ctx, mc_addr):
self.addr = mc_addr
mc = AccessStruct(ctx.mem, MemChunkStruct, mc_addr)
self.next = mc.r_s("mc_Next")
self.bytes = mc.r_s("mc_Bytes")
