def __init__(self):
super().__init__("sw_reg_interface")
sw_addr = Port("sw_address", data_type="std_logic_vector")
sw_addr.overwrite_rule("sink_missing", "set_value(sw_address)")
self.add_port(sw_addr)
self.add_port(
Port("sw_data_out", data_type="std_logic_vector", direction="out"))
sw_data_in = Port("sw_data_in", data_type="std_logic_vector")
sw_data_in.overwrite_rule("sink_missing",
"set_value(axi_slv_reg_write_data)")
self.add_port(sw_data_in)
sw_data_out_ena = Port("sw_data_out_ena")
sw_data_out_ena.overwrite_rule("sink_missing",
"set_value(axi_slv_reg_read_enable)")
self.add_port(sw_data_out_ena)
sw_data_in_ena = Port("sw_data_in_ena")
sw_data_in_ena.overwrite_rule("sink_missing",
"set_value(axi_slv_reg_write_enable)")
self.add_port(sw_data_in_ena)
sw_byte_mask = Port("sw_byte_mask", data_type="std_logic_vector")
sw_byte_mask.overwrite_rule(
"sink_missing", "set_value(axi_slv_reg_write_byte_strobe)")
self.add_port(sw_byte_mask)
def __init__(self):
super().__init__(self.INTERFACE_TYPE_NAME)
# Ports for arbitration mode
mem_req = Port("mem_req", direction="out", optional=True)
mem_req.in_entity = False
self.add_port(mem_req)
# This port needs to be set to '1' if not connected!
mem_req_ack = Port("mem_req_ack", optional=True)
mem_req_ack.overwrite_rule("sink_missing", "set_value('1')")
mem_req_ack.in_entity = False
self.add_port(mem_req_ack)
# Ports towards AXI interface
self.add_port(Port("mem_go", direction="out"))
self.add_port(Port("mem_clr_go"))
self.add_port(Port("mem_busy"))
self.add_port(Port("mem_done"))
self.add_port(Port("mem_error"))
self.add_port(Port("mem_timeout"))
self.add_port(Port("mem_rd_req", direction="out"))
self.add_port(Port("mem_wr_req", direction="out"))
self.add_port(Port("mem_bus_lock", direction="out"))
self.add_port(Port("mem_burst", direction="out"))
self.add_port(
Port(
"mem_addr",
direction="out",
data_type="std_logic_vector",
data_width=Port.DataWidth(
"MEM_ADDRESS_BIT_WIDTH - 1", "downto", 0
),
)
)
self.add_port(
Port(
"mem_be",
direction="out",
data_type="std_logic_vector",
data_width=Port.DataWidth(15, "downto", 0),
)
)
self.add_port(
Port(
"mem_xfer_length",
direction="out",
data_type="std_logic_vector",
data_width=Port.DataWidth(
"BURST_LENGTH_BIT_WIDTH - 1", "downto", 0
),
)
)
self.add_port(Port("mem_in_en"))
self.add_port(
Port(
"mem_in_data",
data_type="std_logic_vector",
data_width=Port.DataWidth("MEMORY_DATA_WIDTH - 1", "downto", 0),
)
)
self.add_port(Port("mem_out_en"))
self.add_port(
Port(
"mem_out_data",
direction="out",
data_type="std_logic_vector",
data_width=Port.DataWidth("MEMORY_DATA_WIDTH - 1", "downto", 0),
)
)
# This interface usually always connects directly to an AXI Master
# Unless an Arbiter module manages access to the AXI interface
self.instantiate_module("AXI_Master")
def __init__(self):
super().__init__("AXI_Master_external")
self.add_port(Port("m_axi_aclk"))
self.add_port(Port("m_axi_aresetn"))
self.add_port(Port("m_axi_arready"))
self.add_port(Port("m_axi_arvalid", direction="out"))
self.add_port(
Port("m_axi_araddr",
direction="out",
data_type="std_logic_vector",
data_width=Port.DataWidth(a="C_M_AXI_ADDR_WIDTH - 1",
sep="downto",
b=0)))
self.add_port(
Port("m_axi_arlen",
direction="out",
data_type="std_logic_vector",
data_width=Port.DataWidth(a=7, sep="downto", b=0)))
self.add_port(
Port("m_axi_arsize",
direction="out",
data_type="std_logic_vector",
data_width=Port.DataWidth(a=2, sep="downto", b=0)))
self.add_port(
Port("m_axi_arburst",
direction="out",
data_type="std_logic_vector",
data_width=Port.DataWidth(a=1, sep="downto", b=0)))
self.add_port(
Port("m_axi_arprot",
direction="out",
data_type="std_logic_vector",
data_width=Port.DataWidth(a=2, sep="downto", b=0)))
self.add_port(
Port("m_axi_arcache",
direction="out",
data_type="std_logic_vector",
data_width=Port.DataWidth(a=3, sep="downto", b=0)))
self.add_port(Port("m_axi_rready", direction="out"))
self.add_port(Port("m_axi_rvalid"))
self.add_port(
Port("m_axi_rdata",
data_type="std_logic_vector",
data_width=Port.DataWidth(a="C_M_AXI_DATA_WIDTH - 1",
sep="downto",
b=0)))
self.add_port(
Port("m_axi_rresp",
data_type="std_logic_vector",
data_width=Port.DataWidth(a=1, sep="downto", b=0)))
self.add_port(Port("m_axi_rlast"))
self.add_port(Port("m_axi_awready"))
self.add_port(Port("m_axi_awvalid", direction="out"))
self.add_port(
Port("m_axi_awaddr",
direction="out",
data_type="std_logic_vector",
data_width=Port.DataWidth(a="C_M_AXI_ADDR_WIDTH - 1",
sep="downto",
b=0)))
self.add_port(
Port("m_axi_awlen",
direction="out",
data_type="std_logic_vector",
data_width=Port.DataWidth(a=7, sep="downto", b=0)))
self.add_port(
Port("m_axi_awsize",
direction="out",
data_type="std_logic_vector",
data_width=Port.DataWidth(a=2, sep="downto", b=0)))
self.add_port(
Port("m_axi_awburst",
direction="out",
data_type="std_logic_vector",
data_width=Port.DataWidth(a=1, sep="downto", b=0)))
self.add_port(
Port("m_axi_awprot",
direction="out",
data_type="std_logic_vector",
data_width=Port.DataWidth(a=2, sep="downto", b=0)))
self.add_port(
Port("m_axi_awcache",
direction="out",
data_type="std_logic_vector",
data_width=Port.DataWidth(a=3, sep="downto", b=0)))
self.add_port(Port("m_axi_wready"))
self.add_port(Port("m_axi_wvalid", direction="out"))
self.add_port(
Port("m_axi_wdata",
direction="out",
data_type="std_logic_vector",
data_width=Port.DataWidth(a="C_M_AXI_DATA_WIDTH - 1",
sep="downto",
b=0)))
self.add_port(
Port("m_axi_wstrb",
direction="out",
data_type="std_logic_vector",
data_width=Port.DataWidth(a="C_M_AXI_DATA_WIDTH / 8 - 1",
sep="downto",
b=0)))
self.add_port(Port("m_axi_wlast", direction="out"))
self.add_port(Port("m_axi_bready", direction="out"))
self.add_port(Port("m_axi_bvalid"))
self.add_port(
Port("m_axi_bresp",
data_type="std_logic_vector",
data_width=Port.DataWidth(a=1, sep="downto", b=0)))
md_err = Port("md_error", direction="out", optional=True)
md_err.overwrite_rule("sink_missing", "set_value(open)")
self.add_port(md_err)
self.to_external = True
