def loadLocalConfig(useBaseline=True):
atbConfig = atb.BoardConfig()
loadTriggerMap(atbConfig, "basic_channel.map", "basic_trigger.map")
atbConfig.triggerMinimumToT = 150E-9
atbConfig.triggerCoincidenceWindow = 25E-9
# HV DAC calibration
loadHVDACParams(atbConfig, "config/febd1/hvdac.Config")
### FEBA (F1) configuration
loadAsicConfig(atbConfig, 0, 2, "config/FEBA1/asic.config")
if useBaseline:
loadBaseline(atbConfig, 0, 2, "config/FEBA1/asic.baseline");
### FEBA (F2) configuration
loadAsicConfig(atbConfig, 2, 4, "config/FEBA2/asic.config")
if useBaseline:
loadBaseline(atbConfig, 2, 4, "config/FEBA2/asic.baseline");
### FEBA (F3) configuration
loadAsicConfig(atbConfig, 4, 6, "config/FEBA3/asic.config")
if useBaseline:
loadBaseline(atbConfig, 4, 6, "config/FEBA3/asic.baseline");
### FEBA (F4) configuration
loadAsicConfig(atbConfig, 6, 8, "config/FEBA4/asic.config")
if useBaseline:
loadBaseline(atbConfig, 6, 8, "config/FEBA4/asic.baseline");
### FEBA (F5) configuration
loadAsicConfig(atbConfig, 8, 10, "config/FEBA5/asic.config")
if useBaseline:
loadBaseline(atbConfig, 8, 10, "config/FEBA5/asic.baseline");
### FEBA (F6) configuration
loadAsicConfig(atbConfig, 10, 12, "config/FEBA6/asic.config")
if useBaseline:
loadBaseline(atbConfig, 10, 12, "config/FEBA6/asic.baseline");
### FEBA (F7) configuration
loadAsicConfig(atbConfig, 12, 14, "config/FEBA7/asic.config")
if useBaseline:
loadBaseline(atbConfig, 12, 14, "config/FEBA7/asic.baseline");
### FEBA (F8) configuration
loadAsicConfig(atbConfig, 14, 16, "config/FEBA8/asic.config")
if useBaseline:
loadBaseline(atbConfig, 14, 16, "config/FEBA8/asic.baseline");
return atbConfig
def loadLocalConfig(useBaseline=True):
atbConfig = atb.BoardConfig()
# HV DAC calibration
loadHVDACParams(atbConfig, 0, 32, "config/pab1/hvdac.Config")
### Mezzanine A (J15) configuration
loadAsicConfig(atbConfig, 0, 1, "config/M1/asic.config")
if useBaseline:
loadBaseline(atbConfig, 0, 1, "config/M1/asic.baseline")
### Mezzanine B (J16) configuration
loadAsicConfig(atbConfig, 2, 3, "config/M2/asic.config")
if useBaseline:
loadBaseline(atbConfig, 2, 3, "config/M2/asic.baseline")
return atbConfig
def loadLocalConfig(useBaseline=True):
atbConfig = atb.BoardConfig()
# HV DAC calibration
loadHVDACParams(atbConfig, "config/febd1/hvdac.Config")
### FEBA (F1) configuration
loadAsicConfig(atbConfig, 0, 2, "config/FEBA1/asic.config")
if useBaseline:
loadBaseline(atbConfig, 0, 2, "config/FEBA1/asic.baseline")
### FEBA (F2) configuration
loadAsicConfig(atbConfig, 2, 4, "config/FEBA2/asic.config")
if useBaseline:
loadBaseline(atbConfig, 2, 4, "config/FEBA2/asic.baseline")
### FEBA (F3) configuration
loadAsicConfig(atbConfig, 4, 6, "config/FEBA3/asic.config")
if useBaseline:
loadBaseline(atbConfig, 4, 6, "config/FEBA3/asic.baseline")
### FEBA (F4) configuration
loadAsicConfig(atbConfig, 6, 8, "config/FEBA4/asic.config")
if useBaseline:
loadBaseline(atbConfig, 6, 8, "config/FEBA4/asic.baseline")
### FEBA (F5) configuration
loadAsicConfig(atbConfig, 8, 10, "config/FEBA5/asic.config")
if useBaseline:
loadBaseline(atbConfig, 8, 10, "config/FEBA5/asic.baseline")
### FEBA (F6) configuration
loadAsicConfig(atbConfig, 10, 12, "config/FEBA6/asic.config")
if useBaseline:
loadBaseline(atbConfig, 10, 12, "config/FEBA6/asic.baseline")
### FEBA (F7) configuration
loadAsicConfig(atbConfig, 12, 14, "config/FEBA7/asic.config")
if useBaseline:
loadBaseline(atbConfig, 12, 14, "config/FEBA7/asic.baseline")
### FEBA (F8) configuration
loadAsicConfig(atbConfig, 14, 16, "config/FEBA8/asic.config")
if useBaseline:
loadBaseline(atbConfig, 14, 16, "config/FEBA8/asic.baseline")
return atbConfig
def loadLocalConfig(useBaseline=True):
atbConfig = atb.BoardConfig()
loadTriggerMap(atbConfig, "basic_channel.map", "basic_trigger.map")
atbConfig.triggerMinimumToT = 150E-9
atbConfig.triggerCoincidenceWindow = 25E-9
# HV DAC calibration
loadHVDACParams(atbConfig, 0, 64, "config/pab1/hvdac.Config")
#loadHVBias(atbConfig, 0, 32, "config/sipm_set1/hvbias.config")
### Mezzanine A (J15) configuration
loadAsicConfig(atbConfig, 0, 2, "config/M1/asic.config")
if useBaseline:
loadBaseline(atbConfig, 0, 2, "config/M1/asic.baseline")
### Mezzanine B (J16) configuration
loadAsicConfig(atbConfig, 2, 4, "config/M2/asic.config")
if useBaseline:
loadBaseline(atbConfig, 2, 4, "config/M2/asic.baseline")
return atbConfig
# -*- coding: utf-8 -*-
import atb
from atbUtils import loadAsicConfig, dumpAsicConfig, loadHVDACParams
from sys import argv
import tofpet
AsicConfig = tofpet.AsicConfig
AsicGlobalConfig = tofpet.AsicGlobalConfig
AsicChannelConfig = tofpet.AsicChannelConfig
intToBin = tofpet.intToBin
# Create a default configuration for target ASICSs (2 per board)
atbConfig = atb.BoardConfig()
atbConfig.asicConfig[0] = AsicConfig()
atbConfig.asicConfig[1] = AsicConfig()
atbConfig.asicConfig[2] = AsicConfig()
atbConfig.asicConfig[3] = AsicConfig()
# Global input DC level adjustment
# Default is 48
atbConfig.asicConfig[0].globalConfig.setValue("sipm_idac_dcstart", 48)
atbConfig.asicConfig[1].globalConfig.setValue("sipm_idac_dcstart", 48)
atbConfig.asicConfig[2].globalConfig.setValue("sipm_idac_dcstart", 48)
atbConfig.asicConfig[3].globalConfig.setValue("sipm_idac_dcstart", 48)
# Channel input DC level adjustment
# Default is 44
for channelConfig in atbConfig.asicConfig[0].channelConfig:
channelConfig.setValue("vbl", 44)
for channelConfig in atbConfig.asicConfig[1].channelConfig:
channelConfig.setValue("vbl", 44)
# -*- coding: utf-8 -*-
import atb
from time import sleep
from sys import argv
uut = atb.ATB("/tmp/d.sock")
uut.config = atb.BoardConfig()
f = open(argv[1])
print "Configuring SI53xx clock filter"
for line in f:
if line[0] == '#': continue
line = line.rstrip('\r\n')
regNum, regValue = line.split(', ')
regNum = int(regNum)
regValue = '0x' + regValue[:-1]
regValue = int(regValue, base=16)
print "Register %02x set to %02x" % (regNum, regValue)
uut.setSI53xxRegister(regNum, regValue)
print "Done"