def bench(): # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) port0_axil_awaddr = Signal(intbv(0)[32:]) port0_axil_awprot = Signal(intbv(0)[3:]) port0_axil_awvalid = Signal(bool(False)) port0_axil_wdata = Signal(intbv(0)[32:]) port0_axil_wstrb = Signal(intbv(0)[4:]) port0_axil_wvalid = Signal(bool(False)) port0_axil_bready = Signal(bool(False)) port0_axil_araddr = Signal(intbv(0)[32:]) port0_axil_arprot = Signal(intbv(0)[3:]) port0_axil_arvalid = Signal(bool(False)) port0_axil_rready = Signal(bool(False)) # Outputs port0_axil_awready = Signal(bool(False)) port0_axil_wready = Signal(bool(False)) port0_axil_bresp = Signal(intbv(0)[2:]) port0_axil_bvalid = Signal(bool(False)) port0_axil_arready = Signal(bool(False)) port0_axil_rdata = Signal(intbv(0)[32:]) port0_axil_rresp = Signal(intbv(0)[2:]) port0_axil_rvalid = Signal(bool(False)) # AXI4-Lite master axil_master_inst = axil.AXILiteMaster() axil_master_pause = Signal(bool(False)) axil_master_logic = axil_master_inst.create_logic( clk, rst, m_axil_awaddr=port0_axil_awaddr, m_axil_awprot=port0_axil_awprot, m_axil_awvalid=port0_axil_awvalid, m_axil_awready=port0_axil_awready, m_axil_wdata=port0_axil_wdata, m_axil_wstrb=port0_axil_wstrb, m_axil_wvalid=port0_axil_wvalid, m_axil_wready=port0_axil_wready, m_axil_bresp=port0_axil_bresp, m_axil_bvalid=port0_axil_bvalid, m_axil_bready=port0_axil_bready, m_axil_araddr=port0_axil_araddr, m_axil_arprot=port0_axil_arprot, m_axil_arvalid=port0_axil_arvalid, m_axil_arready=port0_axil_arready, m_axil_rdata=port0_axil_rdata, m_axil_rresp=port0_axil_rresp, m_axil_rvalid=port0_axil_rvalid, m_axil_rready=port0_axil_rready, pause=axil_master_pause, name='master') # AXI4-Lite RAM model axil_ram_inst = axil.AXILiteRam(2**16) axil_ram_pause = Signal(bool(False)) axil_ram_port0 = axil_ram_inst.create_port( clk, s_axil_awaddr=port0_axil_awaddr, s_axil_awprot=port0_axil_awprot, s_axil_awvalid=port0_axil_awvalid, s_axil_awready=port0_axil_awready, s_axil_wdata=port0_axil_wdata, s_axil_wstrb=port0_axil_wstrb, s_axil_wvalid=port0_axil_wvalid, s_axil_wready=port0_axil_wready, s_axil_bresp=port0_axil_bresp, s_axil_bvalid=port0_axil_bvalid, s_axil_bready=port0_axil_bready, s_axil_araddr=port0_axil_araddr, s_axil_arprot=port0_axil_arprot, s_axil_arvalid=port0_axil_arvalid, s_axil_arready=port0_axil_arready, s_axil_rdata=port0_axil_rdata, s_axil_rresp=port0_axil_rresp, s_axil_rvalid=port0_axil_rvalid, s_axil_rready=port0_axil_rready, pause=axil_ram_pause, latency=1, name='port0') @always(delay(4)) def clkgen(): clk.next = not clk def wait_normal(): while not axil_master_inst.idle(): yield clk.posedge def wait_pause_master(): while not axil_master_inst.idle(): axil_master_pause.next = True yield clk.posedge yield clk.posedge yield clk.posedge axil_master_pause.next = False yield clk.posedge def wait_pause_slave(): while not axil_master_inst.idle(): axil_ram_pause.next = True yield clk.posedge yield clk.posedge yield clk.posedge axil_ram_pause.next = False yield clk.posedge @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge yield clk.posedge print("test 1: baseline") current_test.next = 1 data = axil_ram_inst.read_mem(0, 32) for i in range(0, len(data), 16): print(" ".join( ("{:02x}".format(c) for c in bytearray(data[i:i + 16])))) yield delay(100) yield clk.posedge print("test 2: direct write") current_test.next = 2 axil_ram_inst.write_mem(0, b'test') data = axil_ram_inst.read_mem(0, 32) for i in range(0, len(data), 16): print(" ".join( ("{:02x}".format(c) for c in bytearray(data[i:i + 16])))) assert axil_ram_inst.read_mem(0, 4) == b'test' yield delay(100) yield clk.posedge print("test 3: write via port0") current_test.next = 3 addr = 4 test_data = b'\x11\x22\x33\x44' axil_master_inst.init_write(addr, test_data) yield axil_master_inst.wait() yield clk.posedge data = axil_ram_inst.read_mem(addr & 0xffffff80, 32) for i in range(0, len(data), 16): print(" ".join( ("{:02x}".format(c) for c in bytearray(data[i:i + 16])))) assert axil_ram_inst.read_mem(addr, len(test_data)) == test_data yield delay(100) yield clk.posedge print("test 4: read via port0") current_test.next = 4 addr = 4 test_data = b'\x11\x22\x33\x44' axil_ram_inst.write_mem(addr, test_data) axil_master_inst.init_read(addr, len(test_data)) yield axil_master_inst.wait() yield clk.posedge data = axil_master_inst.get_read_data() assert data[0] == addr assert data[1] == test_data yield delay(100) yield clk.posedge print("test 5: various writes") current_test.next = 5 for length in range(1, 8): for offset in range(4, 8): for wait in wait_normal, wait_pause_master, wait_pause_slave: print("length %d, offset %d" % (length, offset)) addr = 256 * (16 * offset + length) + offset test_data = b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length] axil_ram_inst.write_mem(256 * (16 * offset + length), b'\xAA' * 32) axil_master_inst.init_write(addr, test_data) yield wait() yield clk.posedge data = axil_ram_inst.read_mem(256 * (16 * offset + length), 32) for i in range(0, len(data), 16): print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i + 16])))) assert axil_ram_inst.read_mem(addr, length) == test_data assert axil_ram_inst.read_mem(addr - 1, 1) == b'\xAA' assert axil_ram_inst.read_mem(addr + length, 1) == b'\xAA' yield delay(100) yield clk.posedge print("test 6: various reads") current_test.next = 6 for length in range(1, 8): for offset in range(4, 8): for wait in wait_normal, wait_pause_master, wait_pause_slave: print("length %d, offset %d" % (length, offset)) addr = 256 * (16 * offset + length) + offset test_data = b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length] axil_master_inst.init_read(addr, length) yield wait() yield clk.posedge data = axil_master_inst.get_read_data() assert data[0] == addr assert data[1] == test_data yield delay(100) raise StopSimulation return instances()
def bench(): # Parameters DATA_WIDTH = 32 ADDR_WIDTH = 16 STRB_WIDTH = int(DATA_WIDTH / 8) PIPELINE_OUTPUT = 0 # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) a_clk = Signal(bool(0)) a_rst = Signal(bool(0)) b_clk = Signal(bool(0)) b_rst = Signal(bool(0)) s_axil_a_awaddr = Signal(intbv(0)[ADDR_WIDTH:]) s_axil_a_awprot = Signal(intbv(0)[3:]) s_axil_a_awvalid = Signal(bool(0)) s_axil_a_wdata = Signal(intbv(0)[DATA_WIDTH:]) s_axil_a_wstrb = Signal(intbv(0)[STRB_WIDTH:]) s_axil_a_wvalid = Signal(bool(0)) s_axil_a_bready = Signal(bool(0)) s_axil_a_araddr = Signal(intbv(0)[ADDR_WIDTH:]) s_axil_a_arprot = Signal(intbv(0)[3:]) s_axil_a_arvalid = Signal(bool(0)) s_axil_a_rready = Signal(bool(0)) s_axil_b_awaddr = Signal(intbv(0)[ADDR_WIDTH:]) s_axil_b_awprot = Signal(intbv(0)[3:]) s_axil_b_awvalid = Signal(bool(0)) s_axil_b_wdata = Signal(intbv(0)[DATA_WIDTH:]) s_axil_b_wstrb = Signal(intbv(0)[STRB_WIDTH:]) s_axil_b_wvalid = Signal(bool(0)) s_axil_b_bready = Signal(bool(0)) s_axil_b_araddr = Signal(intbv(0)[ADDR_WIDTH:]) s_axil_b_arprot = Signal(intbv(0)[3:]) s_axil_b_arvalid = Signal(bool(0)) s_axil_b_rready = Signal(bool(0)) # Outputs s_axil_a_awready = Signal(bool(0)) s_axil_a_wready = Signal(bool(0)) s_axil_a_bresp = Signal(intbv(0)[2:]) s_axil_a_bvalid = Signal(bool(0)) s_axil_a_arready = Signal(bool(0)) s_axil_a_rdata = Signal(intbv(0)[DATA_WIDTH:]) s_axil_a_rresp = Signal(intbv(0)[2:]) s_axil_a_rvalid = Signal(bool(0)) s_axil_b_awready = Signal(bool(0)) s_axil_b_wready = Signal(bool(0)) s_axil_b_bresp = Signal(intbv(0)[2:]) s_axil_b_bvalid = Signal(bool(0)) s_axil_b_arready = Signal(bool(0)) s_axil_b_rdata = Signal(intbv(0)[DATA_WIDTH:]) s_axil_b_rresp = Signal(intbv(0)[2:]) s_axil_b_rvalid = Signal(bool(0)) # AXI4-Lite master axil_a_master_inst = axil.AXILiteMaster() axil_a_master_pause = Signal(bool(False)) axil_a_master_logic = axil_a_master_inst.create_logic( a_clk, a_rst, m_axil_awaddr=s_axil_a_awaddr, m_axil_awprot=s_axil_a_awprot, m_axil_awvalid=s_axil_a_awvalid, m_axil_awready=s_axil_a_awready, m_axil_wdata=s_axil_a_wdata, m_axil_wstrb=s_axil_a_wstrb, m_axil_wvalid=s_axil_a_wvalid, m_axil_wready=s_axil_a_wready, m_axil_bresp=s_axil_a_bresp, m_axil_bvalid=s_axil_a_bvalid, m_axil_bready=s_axil_a_bready, m_axil_araddr=s_axil_a_araddr, m_axil_arprot=s_axil_a_arprot, m_axil_arvalid=s_axil_a_arvalid, m_axil_arready=s_axil_a_arready, m_axil_rdata=s_axil_a_rdata, m_axil_rresp=s_axil_a_rresp, m_axil_rvalid=s_axil_a_rvalid, m_axil_rready=s_axil_a_rready, pause=axil_a_master_pause, name='master_a') axil_b_master_inst = axil.AXILiteMaster() axil_b_master_pause = Signal(bool(False)) axil_b_master_logic = axil_b_master_inst.create_logic( b_clk, b_rst, m_axil_awaddr=s_axil_b_awaddr, m_axil_awprot=s_axil_b_awprot, m_axil_awvalid=s_axil_b_awvalid, m_axil_awready=s_axil_b_awready, m_axil_wdata=s_axil_b_wdata, m_axil_wstrb=s_axil_b_wstrb, m_axil_wvalid=s_axil_b_wvalid, m_axil_wready=s_axil_b_wready, m_axil_bresp=s_axil_b_bresp, m_axil_bvalid=s_axil_b_bvalid, m_axil_bready=s_axil_b_bready, m_axil_araddr=s_axil_b_araddr, m_axil_arprot=s_axil_b_arprot, m_axil_arvalid=s_axil_b_arvalid, m_axil_arready=s_axil_b_arready, m_axil_rdata=s_axil_b_rdata, m_axil_rresp=s_axil_b_rresp, m_axil_rvalid=s_axil_b_rvalid, m_axil_rready=s_axil_b_rready, pause=axil_b_master_pause, name='master_b') # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench, clk=clk, rst=rst, current_test=current_test, a_clk=a_clk, a_rst=a_rst, b_clk=b_clk, b_rst=b_rst, s_axil_a_awaddr=s_axil_a_awaddr, s_axil_a_awprot=s_axil_a_awprot, s_axil_a_awvalid=s_axil_a_awvalid, s_axil_a_awready=s_axil_a_awready, s_axil_a_wdata=s_axil_a_wdata, s_axil_a_wstrb=s_axil_a_wstrb, s_axil_a_wvalid=s_axil_a_wvalid, s_axil_a_wready=s_axil_a_wready, s_axil_a_bresp=s_axil_a_bresp, s_axil_a_bvalid=s_axil_a_bvalid, s_axil_a_bready=s_axil_a_bready, s_axil_a_araddr=s_axil_a_araddr, s_axil_a_arprot=s_axil_a_arprot, s_axil_a_arvalid=s_axil_a_arvalid, s_axil_a_arready=s_axil_a_arready, s_axil_a_rdata=s_axil_a_rdata, s_axil_a_rresp=s_axil_a_rresp, s_axil_a_rvalid=s_axil_a_rvalid, s_axil_a_rready=s_axil_a_rready, s_axil_b_awaddr=s_axil_b_awaddr, s_axil_b_awprot=s_axil_b_awprot, s_axil_b_awvalid=s_axil_b_awvalid, s_axil_b_awready=s_axil_b_awready, s_axil_b_wdata=s_axil_b_wdata, s_axil_b_wstrb=s_axil_b_wstrb, s_axil_b_wvalid=s_axil_b_wvalid, s_axil_b_wready=s_axil_b_wready, s_axil_b_bresp=s_axil_b_bresp, s_axil_b_bvalid=s_axil_b_bvalid, s_axil_b_bready=s_axil_b_bready, s_axil_b_araddr=s_axil_b_araddr, s_axil_b_arprot=s_axil_b_arprot, s_axil_b_arvalid=s_axil_b_arvalid, s_axil_b_arready=s_axil_b_arready, s_axil_b_rdata=s_axil_b_rdata, s_axil_b_rresp=s_axil_b_rresp, s_axil_b_rvalid=s_axil_b_rvalid, s_axil_b_rready=s_axil_b_rready) @always(delay(4)) def clkgen(): clk.next = not clk a_clk.next = not a_clk b_clk.next = not b_clk def wait_normal(): while not axil_a_master_inst.idle() or not axil_b_master_inst.idle(): yield clk.posedge def wait_pause_master(): while not axil_a_master_inst.idle() or not axil_b_master_inst.idle(): axil_a_master_pause.next = True axil_b_master_pause.next = True yield clk.posedge yield clk.posedge yield clk.posedge axil_a_master_pause.next = False axil_b_master_pause.next = False yield clk.posedge @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 a_rst.next = 1 b_rst.next = 1 yield clk.posedge rst.next = 0 a_rst.next = 0 b_rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus yield clk.posedge print("test 1: read and write, port A") current_test.next = 1 addr = 4 test_data = b'\x11\x22\x33\x44' axil_a_master_inst.init_write(addr, test_data) yield axil_a_master_inst.wait() yield clk.posedge axil_a_master_inst.init_read(addr, len(test_data)) yield axil_a_master_inst.wait() yield clk.posedge data = axil_a_master_inst.get_read_data() assert data[0] == addr assert data[1] == test_data yield delay(100) yield clk.posedge print("test 2: read and write, port B") current_test.next = 2 addr = 4 test_data = b'\x11\x22\x33\x44' axil_b_master_inst.init_write(addr, test_data) yield axil_b_master_inst.wait() yield clk.posedge axil_b_master_inst.init_read(addr, len(test_data)) yield axil_b_master_inst.wait() yield clk.posedge data = axil_b_master_inst.get_read_data() assert data[0] == addr assert data[1] == test_data yield delay(100) yield clk.posedge print("test 3: various reads and writes on port A") current_test.next = 3 for length in range(1, 8): for offset in range(4, 8): for wait in wait_normal, wait_pause_master: print("length %d, offset %d" % (length, offset)) addr = 256 * (16 * offset + length) + offset test_data = b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length] axil_a_master_inst.init_write(addr - 4, b'\xAA' * (length + 8)) yield axil_a_master_inst.wait() axil_a_master_inst.init_write(addr, test_data) yield wait() axil_a_master_inst.init_read(addr - 1, length + 2) yield axil_a_master_inst.wait() data = axil_a_master_inst.get_read_data() assert data[0] == addr - 1 assert data[1] == b'\xAA' + test_data + b'\xAA' for length in range(1, 8): for offset in range(4, 8): for wait in wait_normal, wait_pause_master: print("length %d, offset %d" % (length, offset)) addr = 256 * (16 * offset + length) + offset test_data = b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length] axil_a_master_inst.init_write(addr, test_data) yield axil_a_master_inst.wait() axil_a_master_inst.init_read(addr, length) yield wait() yield clk.posedge data = axil_a_master_inst.get_read_data() assert data[0] == addr assert data[1] == test_data yield delay(100) yield clk.posedge print("test 4: various reads and writes on port B") current_test.next = 4 for length in range(1, 8): for offset in range(4, 8): for wait in wait_normal, wait_pause_master: print("length %d, offset %d" % (length, offset)) addr = 256 * (16 * offset + length) + offset test_data = b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length] axil_b_master_inst.init_write(addr - 4, b'\xAA' * (length + 8)) yield axil_b_master_inst.wait() axil_b_master_inst.init_write(addr, test_data) yield wait() axil_b_master_inst.init_read(addr - 1, length + 2) yield axil_b_master_inst.wait() data = axil_b_master_inst.get_read_data() assert data[0] == addr - 1 assert data[1] == b'\xAA' + test_data + b'\xAA' for length in range(1, 8): for offset in range(4, 8): for wait in wait_normal, wait_pause_master: print("length %d, offset %d" % (length, offset)) addr = 256 * (16 * offset + length) + offset test_data = b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length] axil_b_master_inst.init_write(addr, test_data) yield axil_b_master_inst.wait() axil_b_master_inst.init_read(addr, length) yield wait() yield clk.posedge data = axil_b_master_inst.get_read_data() assert data[0] == addr assert data[1] == test_data yield delay(100) yield clk.posedge print("test 5: arbitration test") current_test.next = 5 for k in range(10): axil_a_master_inst.init_write(k * 256, b'\x11\x22\x33\x44') axil_a_master_inst.init_read(k * 256, 4) axil_b_master_inst.init_write(k * 256, b'\x11\x22\x33\x44') axil_b_master_inst.init_read(k * 256, 4) yield wait_normal() for k in range(10): axil_a_master_inst.get_read_data() axil_b_master_inst.get_read_data() yield delay(100) raise StopSimulation return instances()
def bench(): # Parameters DEFAULT_PRESCALE = 1 FIXED_PRESCALE = 0 CMD_FIFO = 1 CMD_FIFO_ADDR_WIDTH = 5 WRITE_FIFO = 1 WRITE_FIFO_ADDR_WIDTH = 5 READ_FIFO = 1 READ_FIFO_ADDR_WIDTH = 5 # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) s_axil_awaddr = Signal(intbv(0)[4:]) s_axil_awprot = Signal(intbv(0)[3:]) s_axil_awvalid = Signal(bool(0)) s_axil_wdata = Signal(intbv(0)[32:]) s_axil_wstrb = Signal(intbv(0)[4:]) s_axil_wvalid = Signal(bool(0)) s_axil_bready = Signal(bool(0)) s_axil_araddr = Signal(intbv(0)[4:]) s_axil_arprot = Signal(intbv(0)[3:]) s_axil_arvalid = Signal(bool(0)) s_axil_rready = Signal(bool(0)) i2c_scl_i = Signal(bool(1)) i2c_sda_i = Signal(bool(1)) s1_scl_i = Signal(bool(1)) s1_sda_i = Signal(bool(1)) s2_scl_i = Signal(bool(1)) s2_sda_i = Signal(bool(1)) # Outputs s_axil_awready = Signal(bool(0)) s_axil_wready = Signal(bool(0)) s_axil_bresp = Signal(intbv(0)[2:]) s_axil_bvalid = Signal(bool(0)) s_axil_arready = Signal(bool(0)) s_axil_rdata = Signal(intbv(0)[32:]) s_axil_rresp = Signal(intbv(0)[2:]) s_axil_rvalid = Signal(bool(0)) i2c_scl_o = Signal(bool(1)) i2c_scl_t = Signal(bool(1)) i2c_sda_o = Signal(bool(1)) i2c_sda_t = Signal(bool(1)) s1_scl_o = Signal(bool(1)) s1_scl_t = Signal(bool(1)) s1_sda_o = Signal(bool(1)) s1_sda_t = Signal(bool(1)) s2_scl_o = Signal(bool(1)) s2_scl_t = Signal(bool(1)) s2_sda_o = Signal(bool(1)) s2_sda_t = Signal(bool(1)) # AXI4-Lite master axil_master_inst = axil.AXILiteMaster() axil_master_pause = Signal(bool(False)) axil_master_logic = axil_master_inst.create_logic( clk, rst, m_axil_awaddr=s_axil_awaddr, m_axil_awprot=s_axil_awprot, m_axil_awvalid=s_axil_awvalid, m_axil_awready=s_axil_awready, m_axil_wdata=s_axil_wdata, m_axil_wstrb=s_axil_wstrb, m_axil_wvalid=s_axil_wvalid, m_axil_wready=s_axil_wready, m_axil_bresp=s_axil_bresp, m_axil_bvalid=s_axil_bvalid, m_axil_bready=s_axil_bready, m_axil_araddr=s_axil_araddr, m_axil_arprot=s_axil_arprot, m_axil_arvalid=s_axil_arvalid, m_axil_arready=s_axil_arready, m_axil_rdata=s_axil_rdata, m_axil_rresp=s_axil_rresp, m_axil_rvalid=s_axil_rvalid, m_axil_rready=s_axil_rready, pause=axil_master_pause, name='master') # I2C memory model 1 i2c_mem_inst1 = i2c.I2CMem(1024) i2c_mem_logic1 = i2c_mem_inst1.create_logic(scl_i=s1_scl_i, scl_o=s1_scl_o, scl_t=s1_scl_t, sda_i=s1_sda_i, sda_o=s1_sda_o, sda_t=s1_sda_t, abw=2, address=0x50, latency=0, name='slave1') # I2C memory model 2 i2c_mem_inst2 = i2c.I2CMem(1024) i2c_mem_logic2 = i2c_mem_inst2.create_logic(scl_i=s2_scl_i, scl_o=s2_scl_o, scl_t=s2_scl_t, sda_i=s2_sda_i, sda_o=s2_sda_o, sda_t=s2_sda_t, abw=2, address=0x51, latency=1000, name='slave2') # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench, clk=clk, rst=rst, current_test=current_test, s_axil_awaddr=s_axil_awaddr, s_axil_awprot=s_axil_awprot, s_axil_awvalid=s_axil_awvalid, s_axil_awready=s_axil_awready, s_axil_wdata=s_axil_wdata, s_axil_wstrb=s_axil_wstrb, s_axil_wvalid=s_axil_wvalid, s_axil_wready=s_axil_wready, s_axil_bresp=s_axil_bresp, s_axil_bvalid=s_axil_bvalid, s_axil_bready=s_axil_bready, s_axil_araddr=s_axil_araddr, s_axil_arprot=s_axil_arprot, s_axil_arvalid=s_axil_arvalid, s_axil_arready=s_axil_arready, s_axil_rdata=s_axil_rdata, s_axil_rresp=s_axil_rresp, s_axil_rvalid=s_axil_rvalid, s_axil_rready=s_axil_rready, i2c_scl_i=i2c_scl_i, i2c_scl_o=i2c_scl_o, i2c_scl_t=i2c_scl_t, i2c_sda_i=i2c_sda_i, i2c_sda_o=i2c_sda_o, i2c_sda_t=i2c_sda_t) @always_comb def bus(): # emulate I2C wired AND scl = i2c_scl_o & s1_scl_o & s2_scl_o sda = i2c_sda_o & s1_sda_o & s2_sda_o i2c_scl_i.next = scl i2c_sda_i.next = sda s1_scl_i.next = scl s1_sda_i.next = sda s2_scl_i.next = scl s2_sda_i.next = sda @always(delay(4)) def clkgen(): clk.next = not clk @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus yield clk.posedge print("test 1: write") current_test.next = 1 axil_master_inst.init_write(4, b'\x50\x04\x00\x00\x00') axil_master_inst.init_write(4, b'\x50\x04\x00\x00\x04') axil_master_inst.init_write(4, b'\x50\x04\x00\x00\x11') axil_master_inst.init_write(4, b'\x50\x04\x00\x00\x22') axil_master_inst.init_write(4, b'\x50\x04\x00\x00\x33') axil_master_inst.init_write(4, b'\x50\x14\x00\x00\x44') yield axil_master_inst.wait() yield clk.posedge while True: axil_master_inst.init_read(0, 1) yield axil_master_inst.wait() data = axil_master_inst.get_read_data() if data[1][0] & 0x03 == 0: break data = i2c_mem_inst1.read_mem(0, 32) for i in range(0, len(data), 16): print(" ".join( ("{:02x}".format(c) for c in bytearray(data[i:i + 16])))) assert i2c_mem_inst1.read_mem(4, 4) == b'\x11\x22\x33\x44' yield delay(100) yield clk.posedge print("test 2: read") current_test.next = 2 axil_master_inst.init_write(4, b'\x50\x04\x00\x00\x00') axil_master_inst.init_write(4, b'\x50\x04\x00\x00\x04') axil_master_inst.init_write(4, b'\x50\x03') axil_master_inst.init_write(4, b'\x50\x02') axil_master_inst.init_write(4, b'\x50\x02') axil_master_inst.init_write(4, b'\x50\x12') yield axil_master_inst.wait() yield clk.posedge while True: axil_master_inst.init_read(0, 1) yield axil_master_inst.wait() data = axil_master_inst.get_read_data() if data[1][0] & 0x03 == 0: break axil_master_inst.init_read(8, 2) axil_master_inst.init_read(8, 2) axil_master_inst.init_read(8, 2) axil_master_inst.init_read(8, 2) yield axil_master_inst.wait() yield clk.posedge data = axil_master_inst.get_read_data() assert data[1] == b'\x11\x01' data = axil_master_inst.get_read_data() assert data[1] == b'\x22\x01' data = axil_master_inst.get_read_data() assert data[1] == b'\x33\x01' data = axil_master_inst.get_read_data() assert data[1] == b'\x44\x03' yield delay(100) yield clk.posedge print("test 3: write to slave 2") current_test.next = 3 axil_master_inst.init_write(4, b'\x51\x08\x00\x00\x00\x00') axil_master_inst.init_write(8, b'\x04\x00') axil_master_inst.init_write(8, b'\x44\x00') axil_master_inst.init_write(8, b'\x33\x00') axil_master_inst.init_write(8, b'\x22\x00') axil_master_inst.init_write(8, b'\x11\x02') axil_master_inst.init_write(4, b'\x51\x10') yield axil_master_inst.wait() yield clk.posedge while True: axil_master_inst.init_read(0, 1) yield axil_master_inst.wait() data = axil_master_inst.get_read_data() if data[1][0] & 0x03 == 0: break data = i2c_mem_inst2.read_mem(0, 32) for i in range(0, len(data), 16): print(" ".join( ("{:02x}".format(c) for c in bytearray(data[i:i + 16])))) assert i2c_mem_inst2.read_mem(4, 4) == b'\x44\x33\x22\x11' yield delay(100) yield clk.posedge print("test 4: read from slave 2") current_test.next = 4 axil_master_inst.init_write(4, b'\x51\x04\x00\x00\x00') axil_master_inst.init_write(4, b'\x51\x04\x00\x00\x04') axil_master_inst.init_write(4, b'\x51\x03') axil_master_inst.init_write(4, b'\x51\x02') axil_master_inst.init_write(4, b'\x51\x02') axil_master_inst.init_write(4, b'\x51\x12') yield axil_master_inst.wait() yield clk.posedge while True: axil_master_inst.init_read(0, 1) yield axil_master_inst.wait() data = axil_master_inst.get_read_data() if data[1][0] & 0x03 == 0: break axil_master_inst.init_read(8, 2) axil_master_inst.init_read(8, 2) axil_master_inst.init_read(8, 2) axil_master_inst.init_read(8, 2) yield axil_master_inst.wait() yield clk.posedge data = axil_master_inst.get_read_data() assert data[1] == b'\x44\x01' data = axil_master_inst.get_read_data() assert data[1] == b'\x33\x01' data = axil_master_inst.get_read_data() assert data[1] == b'\x22\x01' data = axil_master_inst.get_read_data() assert data[1] == b'\x11\x03' yield delay(100) yield clk.posedge print("test 5: write to nonexistent device") current_test.next = 5 axil_master_inst.init_write(4, b'\x52\x04\x00\x00\x00') axil_master_inst.init_write(4, b'\x52\x04\x00\x00\x04') axil_master_inst.init_write(4, b'\x52\x04\x00\x00\xde') axil_master_inst.init_write(4, b'\x52\x04\x00\x00\xad') axil_master_inst.init_write(4, b'\x52\x04\x00\x00\xbe') axil_master_inst.init_write(4, b'\x52\x14\x00\x00\xef') yield axil_master_inst.wait() yield clk.posedge got_missed_ack = False while True: axil_master_inst.init_read(0, 1) yield axil_master_inst.wait() data = axil_master_inst.get_read_data() if data[1][0] & 0x08: got_missed_ack = True if data[1][0] & 0x03 == 0: break assert got_missed_ack yield delay(100) raise StopSimulation return instances()
def bench(): # Parameters ADDR_WIDTH = 32 S_DATA_WIDTH = 32 S_STRB_WIDTH = (S_DATA_WIDTH / 8) M_DATA_WIDTH = 32 M_STRB_WIDTH = (M_DATA_WIDTH / 8) # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) s_axil_awaddr = Signal(intbv(0)[ADDR_WIDTH:]) s_axil_awprot = Signal(intbv(0)[3:]) s_axil_awvalid = Signal(bool(0)) s_axil_wdata = Signal(intbv(0)[S_DATA_WIDTH:]) s_axil_wstrb = Signal(intbv(0)[S_STRB_WIDTH:]) s_axil_wvalid = Signal(bool(0)) s_axil_bready = Signal(bool(0)) s_axil_araddr = Signal(intbv(0)[ADDR_WIDTH:]) s_axil_arprot = Signal(intbv(0)[3:]) s_axil_arvalid = Signal(bool(0)) s_axil_rready = Signal(bool(0)) m_axil_awready = Signal(bool(0)) m_axil_wready = Signal(bool(0)) m_axil_bresp = Signal(intbv(0)[2:]) m_axil_bvalid = Signal(bool(0)) m_axil_arready = Signal(bool(0)) m_axil_rdata = Signal(intbv(0)[M_DATA_WIDTH:]) m_axil_rresp = Signal(intbv(0)[2:]) m_axil_rvalid = Signal(bool(0)) # Outputs s_axil_awready = Signal(bool(0)) s_axil_wready = Signal(bool(0)) s_axil_bresp = Signal(intbv(0)[2:]) s_axil_bvalid = Signal(bool(0)) s_axil_arready = Signal(bool(0)) s_axil_rdata = Signal(intbv(0)[S_DATA_WIDTH:]) s_axil_rresp = Signal(intbv(0)[2:]) s_axil_rvalid = Signal(bool(0)) m_axil_awaddr = Signal(intbv(0)[ADDR_WIDTH:]) m_axil_awprot = Signal(intbv(0)[3:]) m_axil_awvalid = Signal(bool(0)) m_axil_wdata = Signal(intbv(0)[M_DATA_WIDTH:]) m_axil_wstrb = Signal(intbv(0)[M_STRB_WIDTH:]) m_axil_wvalid = Signal(bool(0)) m_axil_bready = Signal(bool(0)) m_axil_araddr = Signal(intbv(0)[ADDR_WIDTH:]) m_axil_arprot = Signal(intbv(0)[3:]) m_axil_arvalid = Signal(bool(0)) m_axil_rready = Signal(bool(0)) # AXIl4 master axil_master_inst = axil.AXILiteMaster() axil_master_pause = Signal(bool(False)) axil_master_logic = axil_master_inst.create_logic( clk, rst, m_axil_awaddr=s_axil_awaddr, m_axil_awprot=s_axil_awprot, m_axil_awvalid=s_axil_awvalid, m_axil_awready=s_axil_awready, m_axil_wdata=s_axil_wdata, m_axil_wstrb=s_axil_wstrb, m_axil_wvalid=s_axil_wvalid, m_axil_wready=s_axil_wready, m_axil_bresp=s_axil_bresp, m_axil_bvalid=s_axil_bvalid, m_axil_bready=s_axil_bready, m_axil_araddr=s_axil_araddr, m_axil_arprot=s_axil_arprot, m_axil_arvalid=s_axil_arvalid, m_axil_arready=s_axil_arready, m_axil_rdata=s_axil_rdata, m_axil_rresp=s_axil_rresp, m_axil_rvalid=s_axil_rvalid, m_axil_rready=s_axil_rready, pause=axil_master_pause, name='master') # AXIl4 RAM model axil_ram_inst = axil.AXILiteRam(2**16) axil_ram_pause = Signal(bool(False)) axil_ram_port0 = axil_ram_inst.create_port(clk, s_axil_awaddr=m_axil_awaddr, s_axil_awprot=m_axil_awprot, s_axil_awvalid=m_axil_awvalid, s_axil_awready=m_axil_awready, s_axil_wdata=m_axil_wdata, s_axil_wstrb=m_axil_wstrb, s_axil_wvalid=m_axil_wvalid, s_axil_wready=m_axil_wready, s_axil_bresp=m_axil_bresp, s_axil_bvalid=m_axil_bvalid, s_axil_bready=m_axil_bready, s_axil_araddr=m_axil_araddr, s_axil_arprot=m_axil_arprot, s_axil_arvalid=m_axil_arvalid, s_axil_arready=m_axil_arready, s_axil_rdata=m_axil_rdata, s_axil_rresp=m_axil_rresp, s_axil_rvalid=m_axil_rvalid, s_axil_rready=m_axil_rready, pause=axil_ram_pause, name='port0') # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench, clk=clk, rst=rst, current_test=current_test, s_axil_awaddr=s_axil_awaddr, s_axil_awprot=s_axil_awprot, s_axil_awvalid=s_axil_awvalid, s_axil_awready=s_axil_awready, s_axil_wdata=s_axil_wdata, s_axil_wstrb=s_axil_wstrb, s_axil_wvalid=s_axil_wvalid, s_axil_wready=s_axil_wready, s_axil_bresp=s_axil_bresp, s_axil_bvalid=s_axil_bvalid, s_axil_bready=s_axil_bready, s_axil_araddr=s_axil_araddr, s_axil_arprot=s_axil_arprot, s_axil_arvalid=s_axil_arvalid, s_axil_arready=s_axil_arready, s_axil_rdata=s_axil_rdata, s_axil_rresp=s_axil_rresp, s_axil_rvalid=s_axil_rvalid, s_axil_rready=s_axil_rready, m_axil_awaddr=m_axil_awaddr, m_axil_awprot=m_axil_awprot, m_axil_awvalid=m_axil_awvalid, m_axil_awready=m_axil_awready, m_axil_wdata=m_axil_wdata, m_axil_wstrb=m_axil_wstrb, m_axil_wvalid=m_axil_wvalid, m_axil_wready=m_axil_wready, m_axil_bresp=m_axil_bresp, m_axil_bvalid=m_axil_bvalid, m_axil_bready=m_axil_bready, m_axil_araddr=m_axil_araddr, m_axil_arprot=m_axil_arprot, m_axil_arvalid=m_axil_arvalid, m_axil_arready=m_axil_arready, m_axil_rdata=m_axil_rdata, m_axil_rresp=m_axil_rresp, m_axil_rvalid=m_axil_rvalid, m_axil_rready=m_axil_rready) @always(delay(4)) def clkgen(): clk.next = not clk def wait_normal(): while not axil_master_inst.idle(): yield clk.posedge def wait_pause_master(): while not axil_master_inst.idle(): axil_master_pause.next = True yield clk.posedge yield clk.posedge yield clk.posedge axil_master_pause.next = False yield clk.posedge def wait_pause_slave(): while not axil_master_inst.idle(): axil_ram_pause.next = True yield clk.posedge yield clk.posedge yield clk.posedge axil_ram_pause.next = False yield clk.posedge @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus yield clk.posedge print("test 1: write") current_test.next = 1 addr = 4 test_data = b'\x11\x22\x33\x44' axil_master_inst.init_write(addr, test_data) yield axil_master_inst.wait() yield clk.posedge data = axil_ram_inst.read_mem(addr & 0xffffff80, 32) for i in range(0, len(data), 16): print(" ".join( ("{:02x}".format(c) for c in bytearray(data[i:i + 16])))) assert axil_ram_inst.read_mem(addr, len(test_data)) == test_data yield delay(100) yield clk.posedge print("test 2: read") current_test.next = 2 addr = 4 test_data = b'\x11\x22\x33\x44' axil_ram_inst.write_mem(addr, test_data) axil_master_inst.init_read(addr, len(test_data)) yield axil_master_inst.wait() yield clk.posedge data = axil_master_inst.get_read_data() assert data[0] == addr assert data[1] == test_data yield delay(100) yield clk.posedge print("test 3: various writes") current_test.next = 3 for length in range(1, 8): for offset in range(4, 8): for wait in wait_normal, wait_pause_master, wait_pause_slave: print("length %d, offset %d" % (length, offset)) addr = 256 * (16 * offset + length) + offset test_data = bytearray([x % 256 for x in range(length)]) axil_ram_inst.write_mem(addr & 0xffffff80, b'\xAA' * (length + 256)) axil_master_inst.init_write(addr, test_data) yield wait() yield clk.posedge data = axil_ram_inst.read_mem(addr & 0xffffff80, 32) for i in range(0, len(data), 16): print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i + 16])))) assert axil_ram_inst.read_mem(addr, length) == test_data assert axil_ram_inst.read_mem(addr - 1, 1) == b'\xAA' assert axil_ram_inst.read_mem(addr + length, 1) == b'\xAA' yield delay(100) yield clk.posedge print("test 4: various reads") current_test.next = 4 for length in range(1, 8): for offset in range(4, 8): for wait in wait_normal, wait_pause_master, wait_pause_slave: print("length %d, offset %d" % (length, offset)) addr = 256 * (16 * offset + length) + offset test_data = bytearray([x % 256 for x in range(length)]) axil_ram_inst.write_mem(addr, test_data) axil_master_inst.init_read(addr, length) yield wait() yield clk.posedge data = axil_master_inst.get_read_data() assert data[0] == addr assert data[1] == test_data yield delay(100) raise StopSimulation return instances()
def bench(): # Parameters ADDR_WIDTH = 64 REQ_TAG_WIDTH = 8 OP_TABLE_SIZE = 16 OP_TAG_WIDTH = 8 QUEUE_INDEX_WIDTH = 8 EVENT_WIDTH = 8 QUEUE_PTR_WIDTH = 16 QUEUE_LOG_SIZE_WIDTH = 4 CPL_SIZE = 16 PIPELINE = 2 AXIL_DATA_WIDTH = 32 AXIL_ADDR_WIDTH = 16 AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH / 8) # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) s_axis_enqueue_req_queue = Signal(intbv(0)[QUEUE_INDEX_WIDTH:]) s_axis_enqueue_req_tag = Signal(intbv(0)[REQ_TAG_WIDTH:]) s_axis_enqueue_req_valid = Signal(bool(0)) m_axis_enqueue_resp_ready = Signal(bool(0)) s_axis_enqueue_commit_op_tag = Signal(intbv(0)[OP_TAG_WIDTH:]) s_axis_enqueue_commit_valid = Signal(bool(0)) s_axil_awaddr = Signal(intbv(0)[AXIL_ADDR_WIDTH:]) s_axil_awprot = Signal(intbv(0)[3:]) s_axil_awvalid = Signal(bool(0)) s_axil_wdata = Signal(intbv(0)[AXIL_DATA_WIDTH:]) s_axil_wstrb = Signal(intbv(0)[AXIL_STRB_WIDTH:]) s_axil_wvalid = Signal(bool(0)) s_axil_bready = Signal(bool(0)) s_axil_araddr = Signal(intbv(0)[AXIL_ADDR_WIDTH:]) s_axil_arprot = Signal(intbv(0)[3:]) s_axil_arvalid = Signal(bool(0)) s_axil_rready = Signal(bool(0)) enable = Signal(bool(0)) # Outputs s_axis_enqueue_req_ready = Signal(bool(0)) m_axis_enqueue_resp_ptr = Signal(intbv(0)[QUEUE_PTR_WIDTH:]) m_axis_enqueue_resp_addr = Signal(intbv(0)[ADDR_WIDTH:]) m_axis_enqueue_resp_event = Signal(intbv(0)[EVENT_WIDTH:]) m_axis_enqueue_resp_tag = Signal(intbv(0)[REQ_TAG_WIDTH:]) m_axis_enqueue_resp_op_tag = Signal(intbv(0)[OP_TAG_WIDTH:]) m_axis_enqueue_resp_full = Signal(bool(0)) m_axis_enqueue_resp_error = Signal(bool(0)) m_axis_enqueue_resp_valid = Signal(bool(0)) s_axis_enqueue_commit_ready = Signal(bool(0)) m_axis_event = Signal(intbv(0)[EVENT_WIDTH:]) m_axis_event_source = Signal(intbv(0)[QUEUE_INDEX_WIDTH:]) m_axis_event_valid = Signal(bool(0)) s_axil_awready = Signal(bool(0)) s_axil_wready = Signal(bool(0)) s_axil_bresp = Signal(intbv(0)[2:]) s_axil_bvalid = Signal(bool(0)) s_axil_arready = Signal(bool(0)) s_axil_rdata = Signal(intbv(0)[AXIL_DATA_WIDTH:]) s_axil_rresp = Signal(intbv(0)[2:]) s_axil_rvalid = Signal(bool(0)) # sources and sinks enqueue_req_source = axis_ep.AXIStreamSource() enqueue_req_source_logic = enqueue_req_source.create_logic( clk, rst, tdata=(s_axis_enqueue_req_queue, s_axis_enqueue_req_tag), tvalid=s_axis_enqueue_req_valid, tready=s_axis_enqueue_req_ready, name='enqueue_req_source') enqueue_resp_sink = axis_ep.AXIStreamSink() enqueue_resp_sink_logic = enqueue_resp_sink.create_logic( clk, rst, tdata=(m_axis_enqueue_resp_ptr, m_axis_enqueue_resp_addr, m_axis_enqueue_resp_event, m_axis_enqueue_resp_tag, m_axis_enqueue_resp_op_tag, m_axis_enqueue_resp_full, m_axis_enqueue_resp_error), tvalid=m_axis_enqueue_resp_valid, tready=m_axis_enqueue_resp_ready, name='enqueue_resp_sink') enqueue_commit_source = axis_ep.AXIStreamSource() enqueue_commit_source_logic = enqueue_commit_source.create_logic( clk, rst, tdata=(s_axis_enqueue_commit_op_tag, ), tvalid=s_axis_enqueue_commit_valid, tready=s_axis_enqueue_commit_ready, name='enqueue_commit_source') event_sink = axis_ep.AXIStreamSink() event_sink_logic = event_sink.create_logic(clk, rst, tdata=(m_axis_event, m_axis_event_source), tvalid=m_axis_event_valid, name='event_sink') # AXI4-Lite master axil_master_inst = axil.AXILiteMaster() axil_master_pause = Signal(bool(False)) axil_master_logic = axil_master_inst.create_logic( clk, rst, m_axil_awaddr=s_axil_awaddr, m_axil_awprot=s_axil_awprot, m_axil_awvalid=s_axil_awvalid, m_axil_awready=s_axil_awready, m_axil_wdata=s_axil_wdata, m_axil_wstrb=s_axil_wstrb, m_axil_wvalid=s_axil_wvalid, m_axil_wready=s_axil_wready, m_axil_bresp=s_axil_bresp, m_axil_bvalid=s_axil_bvalid, m_axil_bready=s_axil_bready, m_axil_araddr=s_axil_araddr, m_axil_arprot=s_axil_arprot, m_axil_arvalid=s_axil_arvalid, m_axil_arready=s_axil_arready, m_axil_rdata=s_axil_rdata, m_axil_rresp=s_axil_rresp, m_axil_rvalid=s_axil_rvalid, m_axil_rready=s_axil_rready, pause=axil_master_pause, name='master') # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation( "vvp -m myhdl %s.vvp -lxt2" % testbench, clk=clk, rst=rst, current_test=current_test, s_axis_enqueue_req_queue=s_axis_enqueue_req_queue, s_axis_enqueue_req_tag=s_axis_enqueue_req_tag, s_axis_enqueue_req_valid=s_axis_enqueue_req_valid, s_axis_enqueue_req_ready=s_axis_enqueue_req_ready, m_axis_enqueue_resp_ptr=m_axis_enqueue_resp_ptr, m_axis_enqueue_resp_addr=m_axis_enqueue_resp_addr, m_axis_enqueue_resp_event=m_axis_enqueue_resp_event, m_axis_enqueue_resp_tag=m_axis_enqueue_resp_tag, m_axis_enqueue_resp_op_tag=m_axis_enqueue_resp_op_tag, m_axis_enqueue_resp_full=m_axis_enqueue_resp_full, m_axis_enqueue_resp_error=m_axis_enqueue_resp_error, m_axis_enqueue_resp_valid=m_axis_enqueue_resp_valid, m_axis_enqueue_resp_ready=m_axis_enqueue_resp_ready, s_axis_enqueue_commit_op_tag=s_axis_enqueue_commit_op_tag, s_axis_enqueue_commit_valid=s_axis_enqueue_commit_valid, s_axis_enqueue_commit_ready=s_axis_enqueue_commit_ready, m_axis_event=m_axis_event, m_axis_event_source=m_axis_event_source, m_axis_event_valid=m_axis_event_valid, s_axil_awaddr=s_axil_awaddr, s_axil_awprot=s_axil_awprot, s_axil_awvalid=s_axil_awvalid, s_axil_awready=s_axil_awready, s_axil_wdata=s_axil_wdata, s_axil_wstrb=s_axil_wstrb, s_axil_wvalid=s_axil_wvalid, s_axil_wready=s_axil_wready, s_axil_bresp=s_axil_bresp, s_axil_bvalid=s_axil_bvalid, s_axil_bready=s_axil_bready, s_axil_araddr=s_axil_araddr, s_axil_arprot=s_axil_arprot, s_axil_arvalid=s_axil_arvalid, s_axil_arready=s_axil_arready, s_axil_rdata=s_axil_rdata, s_axil_rresp=s_axil_rresp, s_axil_rvalid=s_axil_rvalid, s_axil_rready=s_axil_rready, enable=enable) @always(delay(4)) def clkgen(): clk.next = not clk @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus enable.next = 1 yield clk.posedge print("test 1: read and write queue configuration registers") current_test.next = 1 axil_master_inst.init_write(0 * 32 + 0, struct.pack('<Q', 0x8877665544332211)) # address axil_master_inst.init_write(0 * 32 + 8, struct.pack( '<L', 0x00000004)) # active, log size axil_master_inst.init_write(0 * 32 + 12, struct.pack( '<L', 0x80000001)) # armed, continuous, event axil_master_inst.init_write(0 * 32 + 16, struct.pack('<L', 0x00000000)) # head pointer axil_master_inst.init_write(0 * 32 + 24, struct.pack('<L', 0x00000000)) # tail pointer axil_master_inst.init_write(0 * 32 + 8, struct.pack( '<L', 0x80000004)) # active, log size yield axil_master_inst.wait() yield clk.posedge axil_master_inst.init_read(0 * 32 + 0, 8) axil_master_inst.init_read(0 * 32 + 8, 4) axil_master_inst.init_read(0 * 32 + 12, 4) yield axil_master_inst.wait() yield clk.posedge data = axil_master_inst.get_read_data() assert struct.unpack('<Q', data[1])[0] == 0x8877665544332211 data = axil_master_inst.get_read_data() assert struct.unpack('<L', data[1])[0] == 0x80000004 data = axil_master_inst.get_read_data() assert struct.unpack('<L', data[1])[0] == 0x00000001 yield delay(100) yield clk.posedge print("test 2: enqueue and dequeue") current_test.next = 2 # read head pointer axil_master_inst.init_read(0 * 32 + 16, 4) # head pointer yield axil_master_inst.wait() data = axil_master_inst.get_read_data() head_ptr = struct.unpack('<L', data[1])[0] # enqueue request enqueue_req_source.send([(0, 1)]) yield enqueue_resp_sink.wait() resp = enqueue_resp_sink.recv() print(resp) # enqueue commit enqueue_commit_source.send([(resp.data[0][4], )]) # check event yield event_sink.wait() event = event_sink.recv() assert event.data[0][0] == 1 # event assert event.data[0][1] == 0 # source (queue) yield delay(100) # read head pointer axil_master_inst.init_read(0 * 32 + 16, 4) # head pointer yield axil_master_inst.wait() data = axil_master_inst.get_read_data() new_head_ptr = struct.unpack('<L', data[1])[0] assert new_head_ptr - head_ptr == 1 # increment tail pointer axil_master_inst.init_read(0 * 32 + 24, 4) # tail pointer yield axil_master_inst.wait() data = axil_master_inst.get_read_data() tail_ptr = struct.unpack('<L', data[1])[0] axil_master_inst.init_write(0 * 32 + 24, struct.pack('<L', tail_ptr + 1)) # tail pointer yield axil_master_inst.wait() yield clk.posedge yield delay(100) yield clk.posedge print("test 3: set up more queues") current_test.next = 3 axil_master_inst.init_write(0 * 32 + 8, struct.pack( '<L', 0x00000004)) # active, log size axil_master_inst.init_write(0 * 32 + 0, struct.pack('<Q', 0x5555555555000000)) # address axil_master_inst.init_write(0 * 32 + 8, struct.pack( '<L', 0x00000004)) # active, log size axil_master_inst.init_write(0 * 32 + 12, struct.pack( '<L', 0xC0000000)) # armed, continuous, event axil_master_inst.init_write(0 * 32 + 16, struct.pack('<L', 0x0000fff0)) # head pointer axil_master_inst.init_write(0 * 32 + 24, struct.pack('<L', 0x0000fff0)) # tail pointer axil_master_inst.init_write(0 * 32 + 8, struct.pack( '<L', 0x80000004)) # active, log size axil_master_inst.init_write(1 * 32 + 8, struct.pack( '<L', 0x00000004)) # active, log size axil_master_inst.init_write(1 * 32 + 0, struct.pack('<Q', 0x5555555555010000)) # address axil_master_inst.init_write(1 * 32 + 8, struct.pack( '<L', 0x00000004)) # active, log size axil_master_inst.init_write(1 * 32 + 12, struct.pack( '<L', 0xC0000001)) # armed, continuous, event axil_master_inst.init_write(1 * 32 + 16, struct.pack('<L', 0x0000fff0)) # head pointer axil_master_inst.init_write(1 * 32 + 24, struct.pack('<L', 0x0000fff0)) # tail pointer axil_master_inst.init_write(1 * 32 + 8, struct.pack( '<L', 0x80000004)) # active, log size axil_master_inst.init_write(2 * 32 + 8, struct.pack( '<L', 0x00000004)) # active, log size axil_master_inst.init_write(2 * 32 + 0, struct.pack('<Q', 0x5555555555020000)) # address axil_master_inst.init_write(2 * 32 + 8, struct.pack( '<L', 0x00000004)) # active, log size axil_master_inst.init_write(2 * 32 + 12, struct.pack( '<L', 0xC0000002)) # armed, continuous, event axil_master_inst.init_write(2 * 32 + 16, struct.pack('<L', 0x0000fff0)) # head pointer axil_master_inst.init_write(2 * 32 + 24, struct.pack('<L', 0x0000fff0)) # tail pointer axil_master_inst.init_write(2 * 32 + 8, struct.pack( '<L', 0x80000004)) # active, log size axil_master_inst.init_write(3 * 32 + 8, struct.pack( '<L', 0x00000004)) # active, log size axil_master_inst.init_write(3 * 32 + 0, struct.pack('<Q', 0x5555555555030000)) # address axil_master_inst.init_write(3 * 32 + 8, struct.pack( '<L', 0x00000004)) # active, log size axil_master_inst.init_write(3 * 32 + 12, struct.pack( '<L', 0xC0000003)) # armed, continuous, event axil_master_inst.init_write(3 * 32 + 16, struct.pack('<L', 0x0000fff0)) # head pointer axil_master_inst.init_write(3 * 32 + 24, struct.pack('<L', 0x0000fff0)) # tail pointer axil_master_inst.init_write(3 * 32 + 8, struct.pack( '<L', 0x80000004)) # active, log size yield axil_master_inst.wait() yield clk.posedge yield delay(100) yield clk.posedge print("test 4: multiple enqueue and dequeue") current_test.next = 4 current_tag = 1 queue_head_ptr = [0xfff0] * 4 queue_tail_ptr = [0xfff0] * 4 queue_depth = [0] * 4 queue_uncommit_depth = [0] * 4 commit_list = [] random.seed(123456) for i in range(50): # enqueue for k in range(random.randrange(8)): q = random.randrange(4) if len(commit_list) < OP_TABLE_SIZE: print("Try enqueue into queue %d" % q) # enqueue request enqueue_req_source.send([(q, current_tag)]) yield enqueue_resp_sink.wait() resp = enqueue_resp_sink.recv() print(resp) #assert resp.data[0][0] == queue_head_ptr[q] assert (resp.data[0][1] >> 16) & 0xf == q assert ( resp.data[0][1] >> 4) & 0xf == queue_head_ptr[q] & 0xf assert resp.data[0][2] == q assert resp.data[0][3] == current_tag # tag assert not resp.data[0][6] # error if queue_uncommit_depth[q] < 16: commit_list.append((q, resp.data[0][4])) queue_head_ptr[q] = (queue_head_ptr[q] + 1) & 0xffff queue_uncommit_depth[q] += 1 else: print("Queue was full") assert resp.data[0][5] # full current_tag = (current_tag + 1) % 256 # commit #random.shuffle(commit_list) for k in range(random.randrange(8)): if commit_list: q, t = commit_list.pop(0) print("Commit enqueue into queue %d" % q) # enqueue commit enqueue_commit_source.send([(t, )]) queue_depth[q] += 1 # check event yield event_sink.wait() event = event_sink.recv() assert event.data[0][0] == q # event assert event.data[0][1] == q # source (queue) # dequeue for k in range(random.randrange(8)): q = random.randrange(4) if queue_depth[q] > 0: print("Dequeue from queue %d" % q) # increment tail pointer axil_master_inst.init_read(q * 32 + 24, 4) # tail pointer yield axil_master_inst.wait() data = axil_master_inst.get_read_data() tail_ptr = struct.unpack('<L', data[1])[0] assert tail_ptr == queue_tail_ptr[q] tail_ptr = (tail_ptr + 1) & 0xffff queue_tail_ptr[q] = tail_ptr queue_depth[q] -= 1 queue_uncommit_depth[q] -= 1 axil_master_inst.init_write( q * 32 + 24, struct.pack('<L', tail_ptr)) # tail pointer yield axil_master_inst.wait() yield delay(100) raise StopSimulation return instances()
def bench(): # Parameters S_COUNT = 4 M_COUNT = 4 DATA_WIDTH = 32 ADDR_WIDTH = 32 STRB_WIDTH = (DATA_WIDTH/8) M_REGIONS = 1 M_BASE_ADDR = [0x00000000, 0x01000000, 0x02000000, 0x03000000] M_ADDR_WIDTH = [24]*M_COUNT*M_REGIONS M_CONNECT_READ = [0b1111]*M_COUNT M_CONNECT_WRITE = [0b1111]*M_COUNT M_SECURE = 0b0000 # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) s_axil_awaddr_list = [Signal(intbv(0)[ADDR_WIDTH:]) for i in range(S_COUNT)] s_axil_awprot_list = [Signal(intbv(0)[3:]) for i in range(S_COUNT)] s_axil_awvalid_list = [Signal(bool(0)) for i in range(S_COUNT)] s_axil_wdata_list = [Signal(intbv(0)[DATA_WIDTH:]) for i in range(S_COUNT)] s_axil_wstrb_list = [Signal(intbv(0)[STRB_WIDTH:]) for i in range(S_COUNT)] s_axil_wvalid_list = [Signal(bool(0)) for i in range(S_COUNT)] s_axil_bready_list = [Signal(bool(0)) for i in range(S_COUNT)] s_axil_araddr_list = [Signal(intbv(0)[ADDR_WIDTH:]) for i in range(S_COUNT)] s_axil_arprot_list = [Signal(intbv(0)[3:]) for i in range(S_COUNT)] s_axil_arvalid_list = [Signal(bool(0)) for i in range(S_COUNT)] s_axil_rready_list = [Signal(bool(0)) for i in range(S_COUNT)] m_axil_awready_list = [Signal(bool(0)) for i in range(M_COUNT)] m_axil_wready_list = [Signal(bool(0)) for i in range(M_COUNT)] m_axil_bresp_list = [Signal(intbv(0)[2:]) for i in range(M_COUNT)] m_axil_bvalid_list = [Signal(bool(0)) for i in range(M_COUNT)] m_axil_arready_list = [Signal(bool(0)) for i in range(M_COUNT)] m_axil_rdata_list = [Signal(intbv(0)[DATA_WIDTH:]) for i in range(M_COUNT)] m_axil_rresp_list = [Signal(intbv(0)[2:]) for i in range(M_COUNT)] m_axil_rvalid_list = [Signal(bool(0)) for i in range(M_COUNT)] s_axil_awaddr = ConcatSignal(*reversed(s_axil_awaddr_list)) s_axil_awprot = ConcatSignal(*reversed(s_axil_awprot_list)) s_axil_awvalid = ConcatSignal(*reversed(s_axil_awvalid_list)) s_axil_wdata = ConcatSignal(*reversed(s_axil_wdata_list)) s_axil_wstrb = ConcatSignal(*reversed(s_axil_wstrb_list)) s_axil_wvalid = ConcatSignal(*reversed(s_axil_wvalid_list)) s_axil_bready = ConcatSignal(*reversed(s_axil_bready_list)) s_axil_araddr = ConcatSignal(*reversed(s_axil_araddr_list)) s_axil_arprot = ConcatSignal(*reversed(s_axil_arprot_list)) s_axil_arvalid = ConcatSignal(*reversed(s_axil_arvalid_list)) s_axil_rready = ConcatSignal(*reversed(s_axil_rready_list)) m_axil_awready = ConcatSignal(*reversed(m_axil_awready_list)) m_axil_wready = ConcatSignal(*reversed(m_axil_wready_list)) m_axil_bresp = ConcatSignal(*reversed(m_axil_bresp_list)) m_axil_bvalid = ConcatSignal(*reversed(m_axil_bvalid_list)) m_axil_arready = ConcatSignal(*reversed(m_axil_arready_list)) m_axil_rdata = ConcatSignal(*reversed(m_axil_rdata_list)) m_axil_rresp = ConcatSignal(*reversed(m_axil_rresp_list)) m_axil_rvalid = ConcatSignal(*reversed(m_axil_rvalid_list)) # Outputs s_axil_awready = Signal(intbv(0)[S_COUNT:]) s_axil_wready = Signal(intbv(0)[S_COUNT:]) s_axil_bresp = Signal(intbv(0)[S_COUNT*2:]) s_axil_bvalid = Signal(intbv(0)[S_COUNT:]) s_axil_arready = Signal(intbv(0)[S_COUNT:]) s_axil_rdata = Signal(intbv(0)[S_COUNT*DATA_WIDTH:]) s_axil_rresp = Signal(intbv(0)[S_COUNT*2:]) s_axil_rvalid = Signal(intbv(0)[S_COUNT:]) m_axil_awaddr = Signal(intbv(0)[M_COUNT*ADDR_WIDTH:]) m_axil_awprot = Signal(intbv(0)[M_COUNT*3:]) m_axil_awvalid = Signal(intbv(0)[M_COUNT:]) m_axil_wdata = Signal(intbv(0)[M_COUNT*DATA_WIDTH:]) m_axil_wstrb = Signal(intbv(0)[M_COUNT*STRB_WIDTH:]) m_axil_wvalid = Signal(intbv(0)[M_COUNT:]) m_axil_bready = Signal(intbv(0)[M_COUNT:]) m_axil_araddr = Signal(intbv(0)[M_COUNT*ADDR_WIDTH:]) m_axil_arprot = Signal(intbv(0)[M_COUNT*3:]) m_axil_arvalid = Signal(intbv(0)[M_COUNT:]) m_axil_rready = Signal(intbv(0)[M_COUNT:]) s_axil_awready_list = [s_axil_awready(i) for i in range(S_COUNT)] s_axil_wready_list = [s_axil_wready(i) for i in range(S_COUNT)] s_axil_bresp_list = [s_axil_bresp((i+1)*2, i*2) for i in range(S_COUNT)] s_axil_bvalid_list = [s_axil_bvalid(i) for i in range(S_COUNT)] s_axil_arready_list = [s_axil_arready(i) for i in range(S_COUNT)] s_axil_rdata_list = [s_axil_rdata((i+1)*DATA_WIDTH, i*DATA_WIDTH) for i in range(S_COUNT)] s_axil_rresp_list = [s_axil_rresp((i+1)*2, i*2) for i in range(S_COUNT)] s_axil_rvalid_list = [s_axil_rvalid(i) for i in range(S_COUNT)] m_axil_awaddr_list = [m_axil_awaddr((i+1)*ADDR_WIDTH, i*ADDR_WIDTH) for i in range(M_COUNT)] m_axil_awprot_list = [m_axil_awprot((i+1)*3, i*3) for i in range(M_COUNT)] m_axil_awvalid_list = [m_axil_awvalid(i) for i in range(M_COUNT)] m_axil_wdata_list = [m_axil_wdata((i+1)*DATA_WIDTH, i*DATA_WIDTH) for i in range(M_COUNT)] m_axil_wstrb_list = [m_axil_wstrb((i+1)*STRB_WIDTH, i*STRB_WIDTH) for i in range(M_COUNT)] m_axil_wvalid_list = [m_axil_wvalid(i) for i in range(M_COUNT)] m_axil_bready_list = [m_axil_bready(i) for i in range(M_COUNT)] m_axil_araddr_list = [m_axil_araddr((i+1)*ADDR_WIDTH, i*ADDR_WIDTH) for i in range(M_COUNT)] m_axil_arprot_list = [m_axil_arprot((i+1)*3, i*3) for i in range(M_COUNT)] m_axil_arvalid_list = [m_axil_arvalid(i) for i in range(M_COUNT)] m_axil_rready_list = [m_axil_rready(i) for i in range(M_COUNT)] # AXI4-Lite masters axil_master_inst_list = [] axil_master_pause_list = [] axil_master_logic = [] for k in range(S_COUNT): m = axil.AXILiteMaster() p = Signal(bool(False)) axil_master_inst_list.append(m) axil_master_pause_list.append(p) axil_master_logic.append(m.create_logic( clk, rst, m_axil_awaddr=s_axil_awaddr_list[k], m_axil_awprot=s_axil_awprot_list[k], m_axil_awvalid=s_axil_awvalid_list[k], m_axil_awready=s_axil_awready_list[k], m_axil_wdata=s_axil_wdata_list[k], m_axil_wstrb=s_axil_wstrb_list[k], m_axil_wvalid=s_axil_wvalid_list[k], m_axil_wready=s_axil_wready_list[k], m_axil_bresp=s_axil_bresp_list[k], m_axil_bvalid=s_axil_bvalid_list[k], m_axil_bready=s_axil_bready_list[k], m_axil_araddr=s_axil_araddr_list[k], m_axil_arprot=s_axil_arprot_list[k], m_axil_arvalid=s_axil_arvalid_list[k], m_axil_arready=s_axil_arready_list[k], m_axil_rdata=s_axil_rdata_list[k], m_axil_rresp=s_axil_rresp_list[k], m_axil_rvalid=s_axil_rvalid_list[k], m_axil_rready=s_axil_rready_list[k], pause=p, name='master_%d' % k )) # AXI4-Lite RAM models axil_ram_inst_list = [] axil_ram_pause_list = [] axil_ram_logic = [] for k in range(M_COUNT): r = axil.AXILiteRam(2**16) p = Signal(bool(False)) axil_ram_inst_list.append(r) axil_ram_pause_list.append(p) axil_ram_logic.append(r.create_port( clk, s_axil_awaddr=m_axil_awaddr_list[k], s_axil_awprot=m_axil_awprot_list[k], s_axil_awvalid=m_axil_awvalid_list[k], s_axil_awready=m_axil_awready_list[k], s_axil_wdata=m_axil_wdata_list[k], s_axil_wstrb=m_axil_wstrb_list[k], s_axil_wvalid=m_axil_wvalid_list[k], s_axil_wready=m_axil_wready_list[k], s_axil_bresp=m_axil_bresp_list[k], s_axil_bvalid=m_axil_bvalid_list[k], s_axil_bready=m_axil_bready_list[k], s_axil_araddr=m_axil_araddr_list[k], s_axil_arprot=m_axil_arprot_list[k], s_axil_arvalid=m_axil_arvalid_list[k], s_axil_arready=m_axil_arready_list[k], s_axil_rdata=m_axil_rdata_list[k], s_axil_rresp=m_axil_rresp_list[k], s_axil_rvalid=m_axil_rvalid_list[k], s_axil_rready=m_axil_rready_list[k], pause=p, latency=1, name='ram_%d' % k )) # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation( "vvp -m myhdl %s.vvp -lxt2" % testbench, clk=clk, rst=rst, current_test=current_test, s_axil_awaddr=s_axil_awaddr, s_axil_awprot=s_axil_awprot, s_axil_awvalid=s_axil_awvalid, s_axil_awready=s_axil_awready, s_axil_wdata=s_axil_wdata, s_axil_wstrb=s_axil_wstrb, s_axil_wvalid=s_axil_wvalid, s_axil_wready=s_axil_wready, s_axil_bresp=s_axil_bresp, s_axil_bvalid=s_axil_bvalid, s_axil_bready=s_axil_bready, s_axil_araddr=s_axil_araddr, s_axil_arprot=s_axil_arprot, s_axil_arvalid=s_axil_arvalid, s_axil_arready=s_axil_arready, s_axil_rdata=s_axil_rdata, s_axil_rresp=s_axil_rresp, s_axil_rvalid=s_axil_rvalid, s_axil_rready=s_axil_rready, m_axil_awaddr=m_axil_awaddr, m_axil_awprot=m_axil_awprot, m_axil_awvalid=m_axil_awvalid, m_axil_awready=m_axil_awready, m_axil_wdata=m_axil_wdata, m_axil_wstrb=m_axil_wstrb, m_axil_wvalid=m_axil_wvalid, m_axil_wready=m_axil_wready, m_axil_bresp=m_axil_bresp, m_axil_bvalid=m_axil_bvalid, m_axil_bready=m_axil_bready, m_axil_araddr=m_axil_araddr, m_axil_arprot=m_axil_arprot, m_axil_arvalid=m_axil_arvalid, m_axil_arready=m_axil_arready, m_axil_rdata=m_axil_rdata, m_axil_rresp=m_axil_rresp, m_axil_rvalid=m_axil_rvalid, m_axil_rready=m_axil_rready ) @always(delay(4)) def clkgen(): clk.next = not clk def wait_normal(): while not all([axil_master_inst_list[k].idle() for k in range(S_COUNT)]): yield clk.posedge def wait_pause_master(): while not all([axil_master_inst_list[k].idle() for k in range(S_COUNT)]): for k in range(S_COUNT): axil_master_pause_list[k].next = True yield clk.posedge yield clk.posedge yield clk.posedge for k in range(S_COUNT): axil_master_pause_list[k].next = False yield clk.posedge def wait_pause_slave(): while not all([axil_master_inst_list[k].idle() for k in range(S_COUNT)]): for k in range(M_COUNT): axil_ram_pause_list[k].next = True yield clk.posedge yield clk.posedge yield clk.posedge for k in range(M_COUNT): axil_ram_pause_list[k].next = False yield clk.posedge @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus yield clk.posedge print("test 1: write") current_test.next = 1 addr = 4 test_data = b'\x11\x22\x33\x44' axil_master_inst_list[0].init_write(addr, test_data) yield axil_master_inst_list[0].wait() yield clk.posedge data = axil_ram_inst_list[0].read_mem(addr&0xffffff80, 32) for i in range(0, len(data), 16): print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16])))) assert axil_ram_inst_list[0].read_mem(addr, len(test_data)) == test_data yield delay(100) yield clk.posedge print("test 2: read") current_test.next = 2 addr = 4 test_data = b'\x11\x22\x33\x44' axil_ram_inst_list[0].write_mem(addr, test_data) axil_master_inst_list[0].init_read(addr, len(test_data)) yield axil_master_inst_list[0].wait() yield clk.posedge data = axil_master_inst_list[0].get_read_data() assert data[0] == addr assert data[1] == test_data yield delay(100) yield clk.posedge print("test 3: one to many") current_test.next = 3 addr = 4 test_data = b'\x11\x22\x33\x44' for k in range(S_COUNT): axil_master_inst_list[0].init_write(addr+M_BASE_ADDR[k], test_data) yield axil_master_inst_list[0].wait() yield clk.posedge for k in range(S_COUNT): data = axil_ram_inst_list[k].read_mem(addr&0xffffff80, 32) for i in range(0, len(data), 16): print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16])))) for k in range(S_COUNT): assert axil_ram_inst_list[k].read_mem(addr, len(test_data)) == test_data for k in range(S_COUNT): axil_master_inst_list[0].init_read(addr+M_BASE_ADDR[k], len(test_data)) yield axil_master_inst_list[0].wait() yield clk.posedge for k in range(S_COUNT): data = axil_master_inst_list[0].get_read_data() assert data[0] == addr+M_BASE_ADDR[k] assert data[1] == test_data yield delay(100) yield clk.posedge print("test 4: many to one") current_test.next = 4 for k in range(M_COUNT): axil_master_inst_list[k].init_write(k*4, bytearray([(k+1)*17]*4)) for k in range(M_COUNT): yield axil_master_inst_list[k].wait() yield clk.posedge data = axil_ram_inst_list[0].read_mem(addr&0xffffff80, 32) for i in range(0, len(data), 16): print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16])))) for k in range(M_COUNT): assert axil_ram_inst_list[0].read_mem(k*4, 4) == bytearray([(k+1)*17]*4) for k in range(M_COUNT): axil_master_inst_list[k].init_read(k*4, 4) for k in range(M_COUNT): yield axil_master_inst_list[k].wait() yield clk.posedge for k in range(M_COUNT): data = axil_master_inst_list[k].get_read_data() assert data[0] == k*4 assert data[1] == bytearray([(k+1)*17]*4) yield delay(100) yield clk.posedge print("test 5: various writes") current_test.next = 5 for length in range(1,8): for offset in range(4,8): for wait in wait_normal, wait_pause_master, wait_pause_slave: print("length %d, offset %d"% (length, offset)) addr = 256*(16*offset+length)+offset test_data = b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length] axil_ram_inst_list[0].write_mem(256*(16*offset+length), b'\xAA'*32) axil_master_inst_list[0].init_write(addr, test_data) yield wait() yield clk.posedge data = axil_ram_inst_list[0].read_mem(256*(16*offset+length), 32) for i in range(0, len(data), 16): print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16])))) assert axil_ram_inst_list[0].read_mem(addr, length) == test_data assert axil_ram_inst_list[0].read_mem(addr-1, 1) == b'\xAA' assert axil_ram_inst_list[0].read_mem(addr+length, 1) == b'\xAA' yield delay(100) yield clk.posedge print("test 6: various reads") current_test.next = 6 for length in range(1,8): for offset in range(4,8): for wait in wait_normal, wait_pause_master, wait_pause_slave: print("length %d, offset %d"% (length, offset)) addr = 256*(16*offset+length)+offset test_data = b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length] axil_master_inst_list[0].init_read(addr, length) yield wait() yield clk.posedge data = axil_master_inst_list[0].get_read_data() assert data[0] == addr assert data[1] == test_data yield delay(100) yield clk.posedge print("test 7: concurrent operations") current_test.next = 7 for count in [1, 2, 4, 8]: for stride in [2, 3, 5, 7]: for wait in wait_normal, wait_pause_master, wait_pause_slave: print("count %d, stride %d"% (count, stride)) for k in range(S_COUNT): for l in range(count): ram = ((k*61+l)*stride)%M_COUNT offset = k*256+l*4 axil_ram_inst_list[ram].write_mem(offset, b'\xAA'*4) axil_master_inst_list[k].init_write(M_BASE_ADDR[ram]+offset, bytearray([0xaa, k, l, 0xaa])) ram = ((k*61+l+67)*stride)%M_COUNT offset = k*256+l*4 axil_ram_inst_list[ram].write_mem(offset+0x8000, bytearray([0xaa, k, l, 0xaa])) axil_master_inst_list[k].init_read(M_BASE_ADDR[ram]+offset+0x8000, 4) yield wait() yield clk.posedge for k in range(S_COUNT): for l in range(count): ram = ((k*61+l)*stride)%M_COUNT offset = k*256+l*4 axil_ram_inst_list[ram].read_mem(offset, 4) == bytearray([0xaa, k, l, 0xaa]) ram = ((k*61+l+67)*stride)%M_COUNT offset = k*256+l*4 data = axil_master_inst_list[k].get_read_data() assert data[0] == M_BASE_ADDR[ram]+offset+0x8000 assert data[1] == bytearray([0xaa, k, l, 0xaa]) yield delay(100) yield clk.posedge print("test 8: bad write") current_test.next = 8 axil_master_inst_list[0].init_write(0xff000000, b'\xDE\xAD\xBE\xEF') yield axil_master_inst_list[0].wait() yield clk.posedge yield delay(100) yield clk.posedge print("test 9: bad read") current_test.next = 9 axil_master_inst_list[0].init_read(0xff000000, 4) yield axil_master_inst_list[0].wait() yield clk.posedge data = axil_master_inst_list[0].get_read_data() assert data[0] == 0xff000000 yield delay(100) raise StopSimulation return instances()
def bench(): # Parameters COUNT = 2 INDEX_WIDTH = 6 SLICE_WIDTH = 5 AXIL_DATA_WIDTH = 32 AXIL_ADDR_WIDTH = INDEX_WIDTH + 4 + 1 + (COUNT - 1).bit_length() AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH / 8) SCHEDULE_START_S = 0x0 SCHEDULE_START_NS = 0x0 SCHEDULE_PERIOD_S = 0 SCHEDULE_PERIOD_NS = 1000000 TIMESLOT_PERIOD_S = 0 TIMESLOT_PERIOD_NS = 100000 ACTIVE_PERIOD_S = 0 ACTIVE_PERIOD_NS = 100000 # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) phy_tx_clk = Signal(intbv(0)[COUNT:]) phy_rx_clk = Signal(intbv(0)[COUNT:]) phy_rx_error_count = Signal(intbv(0)[COUNT * 7:]) s_axil_awaddr = Signal(intbv(0)[AXIL_ADDR_WIDTH:]) s_axil_awprot = Signal(intbv(0)[3:]) s_axil_awvalid = Signal(bool(0)) s_axil_wdata = Signal(intbv(0)[AXIL_DATA_WIDTH:]) s_axil_wstrb = Signal(intbv(0)[AXIL_STRB_WIDTH:]) s_axil_wvalid = Signal(bool(0)) s_axil_bready = Signal(bool(0)) s_axil_araddr = Signal(intbv(0)[AXIL_ADDR_WIDTH:]) s_axil_arprot = Signal(intbv(0)[3:]) s_axil_arvalid = Signal(bool(0)) s_axil_rready = Signal(bool(0)) ptp_ts_96 = Signal(intbv(0)[96:]) ptp_ts_step = Signal(bool(0)) # Outputs phy_tx_prbs31_enable = Signal(intbv(0)[COUNT:]) phy_rx_prbs31_enable = Signal(intbv(0)[COUNT:]) s_axil_awready = Signal(bool(0)) s_axil_wready = Signal(bool(0)) s_axil_bresp = Signal(intbv(0)[2:]) s_axil_bvalid = Signal(bool(0)) s_axil_arready = Signal(bool(0)) s_axil_rdata = Signal(intbv(0)[AXIL_DATA_WIDTH:]) s_axil_rresp = Signal(intbv(0)[2:]) s_axil_rvalid = Signal(bool(0)) # AXI4-Lite master axil_master_inst = axil.AXILiteMaster() axil_master_pause = Signal(bool(False)) axil_master_logic = axil_master_inst.create_logic( clk, rst, m_axil_awaddr=s_axil_awaddr, m_axil_awprot=s_axil_awprot, m_axil_awvalid=s_axil_awvalid, m_axil_awready=s_axil_awready, m_axil_wdata=s_axil_wdata, m_axil_wstrb=s_axil_wstrb, m_axil_wvalid=s_axil_wvalid, m_axil_wready=s_axil_wready, m_axil_bresp=s_axil_bresp, m_axil_bvalid=s_axil_bvalid, m_axil_bready=s_axil_bready, m_axil_araddr=s_axil_araddr, m_axil_arprot=s_axil_arprot, m_axil_arvalid=s_axil_arvalid, m_axil_arready=s_axil_arready, m_axil_rdata=s_axil_rdata, m_axil_rresp=s_axil_rresp, m_axil_rvalid=s_axil_rvalid, m_axil_rready=s_axil_rready, pause=axil_master_pause, name='master') # PTP clock ptp_clock = ptp.PtpClock() ptp_logic = ptp_clock.create_logic(clk, rst, ts_96=ptp_ts_96) # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench, clk=clk, rst=rst, current_test=current_test, phy_tx_clk=phy_tx_clk, phy_rx_clk=phy_rx_clk, phy_rx_error_count=phy_rx_error_count, phy_tx_prbs31_enable=phy_tx_prbs31_enable, phy_rx_prbs31_enable=phy_rx_prbs31_enable, s_axil_awaddr=s_axil_awaddr, s_axil_awprot=s_axil_awprot, s_axil_awvalid=s_axil_awvalid, s_axil_awready=s_axil_awready, s_axil_wdata=s_axil_wdata, s_axil_wstrb=s_axil_wstrb, s_axil_wvalid=s_axil_wvalid, s_axil_wready=s_axil_wready, s_axil_bresp=s_axil_bresp, s_axil_bvalid=s_axil_bvalid, s_axil_bready=s_axil_bready, s_axil_araddr=s_axil_araddr, s_axil_arprot=s_axil_arprot, s_axil_arvalid=s_axil_arvalid, s_axil_arready=s_axil_arready, s_axil_rdata=s_axil_rdata, s_axil_rresp=s_axil_rresp, s_axil_rvalid=s_axil_rvalid, s_axil_rready=s_axil_rready, ptp_ts_96=ptp_ts_96, ptp_ts_step=ptp_ts_step) @always(delay(4)) def clkgen(): clk.next = not clk @always(delay(3)) def clkgen2(): phy_tx_clk.next = ~phy_tx_clk phy_rx_clk.next = ~phy_rx_clk @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus yield clk.posedge print("test 1: Test pulse out") current_test.next = 1 axil_master_inst.init_write(0x0110, struct.pack('<LLLL', 0, 500, 0, 0)) axil_master_inst.init_write(0x0120, struct.pack('<LLLL', 0, 2000, 0, 0)) axil_master_inst.init_write(0x0130, struct.pack('<LLLL', 0, 400, 0, 0)) axil_master_inst.init_write(0x0140, struct.pack('<LLLL', 0, 300, 0, 0)) axil_master_inst.init_write(0x0100, struct.pack('<L', 0x00000001)) yield delay(10000) yield delay(100) raise StopSimulation return instances()