def __init__(self, prj, spec_file):
# type: (Optional[BagProject], str) -> None
self.prj = prj
self._specs = None
if os.path.isfile(spec_file):
self._specs = read_yaml(spec_file)
root_dir = os.path.abspath(self._specs['root_dir'])
save_spec_file = os.path.join(root_dir, 'specs.yaml')
elif os.path.isdir(spec_file):
root_dir = os.path.abspath(spec_file)
save_spec_file = spec_file = os.path.join(root_dir, 'specs.yaml')
self._specs = read_yaml(spec_file)
else:
raise ValueError(
'%s is neither data directory or specification file.' %
spec_file)
self._swp_var_list = tuple(sorted(self._specs['sweep_params'].keys()))
# save root_dir as absolute path, in this way everything will still work
# if the user start python from a different directory.
self._specs['root_dir'] = root_dir
os.makedirs(root_dir, exist_ok=True)
with open_file(save_spec_file, 'w') as f:
yaml.dump(self._specs, f)
def run_main(prj: BagProject, args: argparse.Namespace) -> None:
specs_path = Path(args.specs)
root_dir = specs_path.parent
specs = read_yaml(specs_path)
lib_config = read_yaml(root_dir / 'lib_config.yaml')
sim_config = read_yaml(root_dir / 'sim_config.yaml')
generate_liberty(prj, lib_config, sim_config, specs, fake=args.fake, extract=args.extract,
force_sim=args.force_sim, force_extract=args.force_extract,
gen_sch=args.gen_sch, gen_all_env=args.gen_all_env, export_lay=args.export_lay)
def design_cell(cls,
prj: BagProject,
specs: Mapping[str, Any],
extract: bool = False,
force_sim: bool = False,
force_extract: bool = False,
gen_sch: bool = False,
log_level: LogLevel = LogLevel.DEBUG) -> None:
dsn_str: Union[str, Type[DesignerBase]] = specs['dsn_class']
root_dir: Union[str, Path] = specs['root_dir']
impl_lib: str = specs['impl_lib']
dsn_params: Mapping[str, Any] = specs['dsn_params']
precision: int = specs.get('precision', 6)
dsn_cls = cast(Type[DesignerBase], import_class(dsn_str))
if isinstance(root_dir, str):
root_path = Path(root_dir)
else:
root_path = root_dir
dsn_options = dict(
extract=extract,
force_extract=force_extract,
gen_sch=gen_sch,
log_level=log_level,
)
log_file = str(root_path / 'dsn.log')
sim_db = prj.make_sim_db(root_path / 'dsn',
log_file,
impl_lib,
dsn_options=dsn_options,
force_sim=force_sim,
precision=precision,
log_level=log_level)
designer = dsn_cls(root_path, sim_db, dsn_params)
summary = designer.run_design()
if 'gen_specs' in summary:
prj.generate_cell(summary['gen_specs'], **summary['gen_args'])
if 'gen_lib' in summary['gen_specs'] and summary['gen_specs'][
'gen_lib']:
lib_specs = summary['gen_specs']['lib_specs']
lib_args = summary['gen_specs']['lib_args']
lib_file = lib_specs['lib_file']
lib_file_path = Path(lib_file)
lib_file_specs = read_yaml(lib_file_path)
root_dir = lib_file_path.parent
lib_config = read_yaml(root_dir / 'lib_config.yaml')
sim_config = read_yaml(root_dir / 'sim_config.yaml')
generate_liberty(prj, lib_config, sim_config, lib_file_specs,
**lib_args)
else:
pprint.pprint(summary)
def __init__(self, prj, spec_file):
# type: (Optional[BagProject], str) -> None
self.prj = prj
self._specs = None
if os.path.isfile(spec_file):
self._specs = read_yaml(spec_file)
self._root_dir = os.path.abspath(self._specs['root_dir'])
elif os.path.isdir(spec_file):
self._root_dir = os.path.abspath(spec_file)
self._specs = read_yaml(os.path.join(self._root_dir, 'specs.yaml'))
else:
raise ValueError('%s is neither data directory or specification file.' % spec_file)
self._swp_var_list = tuple(sorted(self._specs['sweep_params'].keys()))
def run_main(prj):
amp_dsn_specs_fname = 'specs_design/diffamp_paper.yaml'
amp_char_specs_fname = 'specs_char/diffamp_paper.yaml'
amp_char_specs_out_fname = 'specs_char/diffamp_paper_mod.yaml'
# simulate(prj, amp_char_specs_out_fname)
# return
amp_dsn_specs = read_yaml(amp_dsn_specs_fname)
gain_min_orig = amp_dsn_specs['gain_min']
bw_min_orig = amp_dsn_specs['bw_min']
result = None
done = False
gain, w3db = 0, 0
while not done:
result = design(amp_dsn_specs, amp_char_specs_fname,
amp_char_specs_out_fname)
gain, w3db = simulate(prj, amp_char_specs_out_fname)
if gain >= gain_min_orig and w3db >= bw_min_orig:
done = True
else:
if gain < gain_min_orig:
gain_expected = result['gain']
gain_scale = gain / gain_expected
amp_dsn_specs['gain_min'] = gain_min_orig / gain_scale
if w3db < bw_min_orig:
bw_expected = result['bw']
bw_scale = w3db / bw_expected
amp_dsn_specs['bw_min'] = bw_min_orig / bw_scale
pprint.pprint(result)
print('final gain = %.4g' % gain)
print('final w3db = %.4g' % w3db)
def __init__(self, design_specs_fname):
"""
:param design_specs_fname: The main yaml file that should have some specific structure,
the template is given in ...
"""
self.bprj = BagProject()
self.design_specs_fname = design_specs_fname
self.ver_specs = read_yaml(self.design_specs_fname)
root_dir = self.ver_specs['root_dir']
self.gen_yamls_dir = os.path.join(root_dir, 'gen_yamls')
self.top_level_main_file = os.path.join(self.gen_yamls_dir, self.ver_specs['sim_spec_fname'])
self.gen_yamls_dir = os.path.join(self.gen_yamls_dir, 'swp_spec_files')
os.makedirs(self.gen_yamls_dir, exist_ok=True)
self.spec_range = self.ver_specs['spec_range']
self.param_choices_layout = self.break_hierarchy(self.ver_specs['params']['layout_params'])
self.param_choices_measurement = self.break_hierarchy(self.ver_specs['params']['measurements'])
# self.params contains the dictionary corresponding to the params part of the main yaml file where empty
# dicts are replaces with None
self.params = self.break_hierarchy(self.ver_specs['params'])
self.params_vec = {}
self.search_space_size = 1
for key, value in self.params.items():
if value is not None:
# self.params_vec contains keys of the main parameters and the corresponding search vector for each
self.params_vec[key] = np.arange(value[0], value[1], value[2]).tolist()
self.search_space_size = self.search_space_size * len(self.params_vec[key])
self.id_encoder = IDEncoder(self.params_vec)
self._unique_suffix = 0
self.temp_db = None
def design(amp_dsn_specs, amp_char_specs_fname, amp_char_specs_out_fname):
nch_config = amp_dsn_specs['nch_config']
pch_config = amp_dsn_specs['pch_config']
print('create transistor database')
nch_db = MOSDBDiscrete([nch_config])
pch_db = MOSDBDiscrete([pch_config])
nch_db.set_dsn_params(**amp_dsn_specs['nch'])
pch_db.set_dsn_params(**amp_dsn_specs['pch'])
result = design_amp(amp_dsn_specs, nch_db, pch_db)
if result is None:
raise ValueError('No solution.')
pprint.pprint(result)
# update characterization spec file
amp_char_specs = read_yaml(amp_char_specs_fname)
# update bias
var_dict = amp_char_specs['measurements'][0]['testbenches']['ac'][
'sim_vars']
for key in ('vtail', 'vindc', 'voutdc'):
var_dict[key] = result[key]
for key in ('vdd', 'cload'):
var_dict[key] = amp_dsn_specs[key]
# update segments
seg_dict = amp_char_specs['layout_params']['seg_dict']
for key in ('in', 'load', 'tail'):
seg_dict[key] = result['seg_' + key]
with open_file(amp_char_specs_out_fname, 'w') as f:
yaml.dump(amp_char_specs, f)
return result
def run_main(prj: BagProject, args: argparse.Namespace) -> None:
specs: Mapping[str, Any] = read_yaml(args.specs)
DesignerBase.design_cell(prj,
specs,
extract=args.extract,
force_sim=args.force_sim,
force_extract=args.force_extract,
gen_sch=args.gen_sch)
def __init__(self, bprj, spec_file, gds_layermap=''):
self.prj = bprj
self.tdb = None # templateDB instance for layout creation
self.impl_lib = None # Virtuoso library where generated cells are stored
self.cell_name_list = None # list of names for each created cell
self.specs = read_yaml(spec_file)
# Initialize self.tdb with appropriate templateDB instance
self.make_tdb(gds_layermap)
def run_test(db: TemplateDB, lay_list: List[Tuple[TemplateBase, str]],
fpath_list: List[Path]) -> None:
for fpath in fpath_list:
print(f'creating layout from file: {fpath.name}')
specs = read_yaml(fpath)
lay_cls = cast(Type[TemplateBase], import_class(specs['lay_class']))
params = specs['params']
master = db.new_template(lay_cls, params=params)
lay_list.append((master, fpath.stem))
def run_main(prj: BagProject, args: argparse.Namespace) -> None:
specs = read_yaml(args.specs)
ans = prj.measure_cell_old(specs,
gen_dut=args.gen_dut,
load_from_file=args.load_from_file,
extract=args.extract,
mismatch=args.mismatch)
print('measurement results:')
pprint.pprint(ans)
def run_main(prj: BagProject, args: argparse.Namespace) -> None:
specs: Mapping[str, Any] = read_yaml(args.specs)
log_level = LogLevel.WARN if args.quiet else LogLevel.INFO
prj.measure_cell(specs,
extract=args.extract,
force_sim=args.force_sim,
force_extract=args.force_extract,
gen_sch=args.gen_sch,
log_level=log_level,
fake=args.fake)
def __init__(self, temp_db, lib_name, params, used_names, **kwargs):
# type: (TemplateDB, str, Dict[str, Any], Set[str], **Any) -> None
self._config = read_yaml(params['config_file'])
self._tech_params = self._config['tech_params']
self._cells = self._config['cells']
self._spaces = self._config['spaces']
self._bound_params = self._config['boundaries']
TemplateBase.__init__(self, temp_db, lib_name, params, used_names,
**kwargs)
self._std_size = None # type: Optional[Tuple[int, int]]
self._std_size_bare = None # type: Optional[Tuple[int, int]]
self._draw_boundaries = False # type: bool
self._used_blocks = [] # type: List[IntervalSet]
def main():
eval_core = OpampEvaluationEngine(design_specs_fname='specs_design/opamp_two_stage_1e8.yaml')
content = read_yaml('specs_design/opamp_two_stage_1e8.yaml')
db_dir = content['database_dir']
np.random.seed(10)
random.seed(10)
start = time.time()
sample_designs = eval_core.generate_data_set(n=1, evaluate=True)
print("time for simulating one instance: {}".format((time.time() - start)))
pdb.set_trace()
def run_main(prj: BagProject, gen_sch: bool = True, gen_cdl: bool = True, run_lvs: bool = True) \
-> None:
lib_name = 'AAA_XBASE_TEST'
fname = '00_mom_cap.yaml'
impl_cell = 'MOMCap_core'
fname_cdl = 'pvs_run/lvs_run_dir/' + lib_name + '/' + impl_cell + '/schematic.net'
params = read_yaml(Path('specs_test', 'xbase', fname))
db = TemplateDB(prj.grid, lib_name, prj=prj)
print('creating new template')
master = db.new_template(MOMCapCore, params)
print('creating batch layout')
# db.batch_layout([(master, '')], DesignOutput.LAYOUT)
db.batch_layout([(master, impl_cell)], DesignOutput.LAYOUT)
print('done')
if gen_sch or gen_cdl:
sch_db = ModuleDB(prj.tech_info, lib_name, prj=prj)
sch_master = sch_db.new_master(xbase__momcap_core, master.sch_params)
cv_info_list = []
print('creating schematic')
sch_db.batch_schematic([(sch_master, impl_cell)],
cv_info_out=cv_info_list)
print('schematic creation done')
if gen_cdl:
print('creating CDL netlist')
sch_db.batch_schematic([(sch_master, impl_cell)],
output=DesignOutput.CDL,
fname=fname_cdl,
cv_info_list=cv_info_list)
print('netlist creation done')
if run_lvs:
print('Running LVS ...')
lvs_passed, lvs_log = prj.run_lvs(lib_name,
impl_cell,
netlist=fname_cdl)
print('LVS log file:' + lvs_log)
if lvs_passed:
print('LVS passed!')
else:
print('LVS failed :(')
def design_only():
interp_method = 'spline'
nch_conf_list = [
'data/nch_w4_stack/specs.yaml',
]
pch_conf_list = [
'data/pch_w4_stack/specs.yaml',
]
amp_specs_fname = 'specs_design/opamp_two_stage_1e8.yaml'
print('create transistor database')
nch_db = MOSDBDiscrete(nch_conf_list, interp_method=interp_method)
pch_db = MOSDBDiscrete(pch_conf_list, interp_method=interp_method)
top_specs = read_yaml(amp_specs_fname)
design(top_specs, nch_db, pch_db)
def get_layout_params(self, val_list):
# type: (Tuple[Any, ...]) -> Dict[str, Any]
"""Returns the layout dictionary from the given sweep parameter values. Overwritten to incorporate
the discrete evaluation problem, instead of a sweep"""
# sanity check
assert len(self.swp_var_list) == 1 and 'swp_spec_file' in self.swp_var_list , \
"when using DeepCKTDesignManager for replacing file name, just (swp_spec_file) should be part of the " \
"sweep_params dictionary"
lay_params = deepcopy(self.specs['layout_params'])
yaml_fname = self.specs['root_dir']+'/gen_yamls/swp_spec_files/' + val_list[0] + '.yaml'
print(yaml_fname)
updated_top_specs = read_yaml(yaml_fname)
new_lay_params = updated_top_specs['layout_params']
lay_params.update(new_lay_params)
return lay_params
def run_main(prj: BagProject, args: argparse.Namespace) -> None:
specs = read_yaml(args.specs)
prj.generate_cell(specs,
raw=args.raw,
gen_lay=args.gen_lay,
run_drc=args.run_drc,
gen_sch=args.gen_sch,
run_lvs=args.run_lvs,
run_rcx=args.run_rcx,
gen_lef=args.gen_lef,
flat=args.flat,
sim_netlist=args.gen_sim,
gen_hier=args.gen_hier,
gen_model=args.gen_mod,
gen_shell=args.gen_shell,
export_lay=args.export_lay,
gen_netlist=args.gen_netlist)
def generate_and_sim_ckt(self, file_name, new_flag=True):
results = []
specs = read_yaml(file_name)
sim = CustomDesignManager(self.bprj, file_name)
if self.temp_db is None:
self.temp_db = sim.make_tdb()
sim.set_tdb(self.temp_db)
results_ph1 = sim.characterize_designs(generate=new_flag,
measure=False,
load_from_file=False)
impl_lib = specs['impl_lib']
coro_list = []
file_list = specs['sweep_params']['swp_spec_file']
# hacky: do parallel measurements, you should not sweep anything other than 'swp_spec_file' in sweep_params
# the new yaml files themselves should not include any sweep_param
for ph1_iter_index, combo_list in enumerate(
sim.get_combinations_iter()):
dsn_name = sim.get_design_name(combo_list)
specs_fname = file_list[ph1_iter_index]
if isinstance(results_ph1[ph1_iter_index], Exception):
continue
coro_list.append(
self.async_characterization(impl_lib,
dsn_name,
specs_fname,
load_from_file=not new_flag))
results_ph2 = batch_async_task(coro_list)
# this part returns the correct order of results if some of the instances failed phase1 of evaluation
ph2_iter_index = 0
for ph1_iter_index, combo_list in enumerate(
sim.get_combinations_iter()):
if isinstance(results_ph1[ph1_iter_index], Exception):
results.append(results_ph1[ph1_iter_index])
else:
# if isinstance(results_ph2[ph2_iter_index], Exception):
# raise results_ph2[ph2_iter_index]
results.append(results_ph2[ph2_iter_index])
ph2_iter_index += 1
return results
def __init__(self, design_specs_fname):
self.bprj = BagProject()
self.design_specs_fname = design_specs_fname
self.ver_specs = read_yaml(self.design_specs_fname)
root_dir = os.path.abspath(self.ver_specs['root_dir'])
self.gen_yamls_dir = os.path.join(root_dir, 'gen_yamls')
self.top_level_dir = os.path.join(self.gen_yamls_dir, 'top_level')
self.top_level_main_file = os.path.join(self.gen_yamls_dir,
'top_level.yaml')
os.makedirs(self.top_level_dir, exist_ok=True)
self.spec_range = self.ver_specs['spec_range']
self.param_choices_layout = self.break_hierarchy(
self.ver_specs['params']['layout_params'])
self.param_choices_measurement = self.break_hierarchy(
self.ver_specs['params']['measurements'])
# self.params contains the dictionary corresponding to the params part of the main yaml file where empty
# dicts are replaces with None
self.params = self.break_hierarchy(self.ver_specs['params'])
self.params_vec = {}
self.search_space_size = 1
for key, value in self.params.items():
if value is not None:
# self.params_vec contains keys of the main parameters and the corresponding search vector for each
self.params_vec[key] = np.arange(value[0], value[1],
value[2]).tolist()
self.search_space_size = self.search_space_size * len(
self.params_vec[key])
self.id_encoder = IDEncoder(self.params_vec)
self._unique_suffix = 0
self.temp_db = None
self.subckts_template = self.ver_specs['sub_system_sim']
self.subckts_yaml_dirs = dict()
self.subckts_main_file = dict()
for key in self.subckts_template.keys():
directory = os.path.join(self.gen_yamls_dir,
'subckt_{}'.format(key))
self.subckts_yaml_dirs[key] = directory
self.subckts_main_file[key] = directory + '.yaml'
os.makedirs(self.subckts_yaml_dirs[key], exist_ok=True)
def generate_and_sim(prj, generate=True):
ver_specs_fname = 'specs_verification/opamp_two_stage_1e8.yaml'
sim_specs_fname = 'specs_verification/opamp_two_stage_1e8_sim.yaml'
ver_specs = read_yaml(ver_specs_fname)
ver_specs['measurements'][0]['find_cfb'] = False
with open_file(sim_specs_fname, 'w') as f:
yaml.dump(ver_specs, f)
sim = DesignManager(prj, sim_specs_fname)
sim.characterize_designs(generate=generate,
measure=True,
load_from_file=False)
dsn_name = list(sim.get_dsn_name_iter())[0]
summary = sim.get_result(dsn_name)['opamp_ac']
print('result:')
pprint.pprint(summary)
def get_result(self, dsn_name):
# type: (str) -> Dict[str, Any]
"""Returns the measurement result summary dictionary.
Parameters
----------
dsn_name : str
the design name.
Returns
-------
result : Dict[str, Any]
the result dictionary.
"""
fname = os.path.join(self._root_dir, dsn_name,
self.specs['summary_fname'])
summary = read_yaml(fname)
return summary
def __init__(self, database, yaml_fname, **kwargs):
# type: (ModuleDB, str, **Any) -> None
lib_name = kwargs['lib_name']
params = kwargs['params']
used_names = kwargs['used_names']
design_fun = kwargs['design_fun']
design_args = kwargs['design_args']
self.tech_info = database.tech_info
self.instances = {
} # type: Dict[str, Union[SchInstance, List[SchInstance]]]
self.pin_map = {}
self.new_pins = []
self.parameters = {}
self._pin_list = None
self._yaml_fname = os.path.abspath(yaml_fname)
self.sch_info = read_yaml(self._yaml_fname)
self._orig_lib_name = self.sch_info['lib_name']
self._orig_cell_name = self.sch_info['cell_name']
self._design_fun = design_fun
self._design_args = design_args
# create initial instances and populate instance map
for inst_name, inst_attr in self.sch_info['instances'].items():
lib_name = inst_attr['lib_name']
cell_name = inst_attr['cell_name']
static = database.is_lib_excluded(lib_name)
self.instances[inst_name] = SchInstance(database,
lib_name,
cell_name,
inst_name,
static=static)
# fill in pin map
for pin in self.sch_info['pins']:
self.pin_map[pin] = pin
# initialize schematic master
DesignMaster.__init__(self, database, lib_name, params, used_names)
def run_main(prj: BagProject, args: argparse.Namespace) -> None:
specs = read_yaml(args.specs)
lay_db = prj.make_template_db(specs['impl_lib']) if args.gen_lay else None
sch_db = prj.make_module_db(specs['impl_lib'])
cv_info = []
dut_params = specs['dut_params']
dut_netlist = prj.generate_cell(dut_params,
lay_db=lay_db,
sch_db=sch_db,
gen_lay=args.gen_lay,
gen_sch=args.gen_sch,
cv_info_out=cv_info,
run_rcx=args.run_rcx)
print(f'dut_netlist: {dut_netlist}')
wrapper_params = specs['wrapper_params']
prj.replace_dut_in_wrapper(wrapper_params['params'],
dut_params['impl_lib'], dut_params['impl_cell'])
generate_wrapper(sch_db,
wrapper_params,
cv_info,
dut_netlist,
gen_sch=args.gen_sch)
elif isinstance(val, str):
print('%s = %s' % (key, val))
else:
print('%s = %.3g' % (key, val))
if __name__ == '__main__':
nch_config = 'specs_mos_char/mos_char_nch_stack_w2.yaml'
load_specs = 'specs_dsn/load_diode_pfb.yaml'
noise_fstart = 20e3
noise_fstop = noise_fstart + 500
noise_scale = 1.0
noise_temp = 310
load_specs = read_yaml(load_specs)
print('create transistor database')
nch_db = MOSDBDiscrete([nch_config],
noise_fstart,
noise_fstop,
noise_scale=noise_scale,
noise_temp=noise_temp)
print('create design class')
load_dsn = LoadDiodePFB(nch_db)
print('run design')
load_dsn.design(**load_specs)
dsn_info = load_dsn.get_dsn_info()
print_dsn_info(dsn_info)
elif isinstance(val, str):
print('%s = %s' % (key, val))
else:
print('%s = %.3g' % (key, val))
if __name__ == '__main__':
pch_config = 'specs_mos_char/mos_char_pch_stack_w2.yaml'
gm_specs = 'specs_dsn/input_gm.yaml'
noise_fstart = 20e3
noise_fstop = noise_fstart + 500
noise_scale = 1.0
noise_temp = 310
gm_specs = read_yaml(gm_specs)
print('create transistor database')
pch_db = MOSDBDiscrete([pch_config],
noise_fstart,
noise_fstop,
noise_scale=noise_scale,
noise_temp=noise_temp)
print('create design class')
gm_dsn = InputGm(pch_db)
print('design gm')
gm_dsn.design(**gm_specs)
gm_info = gm_dsn.get_dsn_info()
print('gm info:')
print_dsn_info(gm_info)
processed_result['cost'] = cost
else:
processed_result['valid'] = False
processed_results.append(processed_result)
return processed_results
if __name__ == '__main__':
import pickle
np.random.seed(100)
random.seed(100)
fname = 'specs_design/DiffTIA.yaml'
evalEngine = DiffTIAEvaluationEngine(design_specs_fname=fname)
content = read_yaml(fname)
dir = content['database_dir']
start = time.time()
sample_designs = evalEngine.generate_data_set(n=100, evaluate=True)
print("time: {}".format(time.time() - start))
os.makedirs(dir, exist_ok=True)
with open(dir + "/init_data.pickle", 'wb') as f:
pickle.dump(sample_designs, f)
with open(dir + "/init_data.pickle", 'rb') as f:
data = pickle.load(f)
se = [x.cost for x in data]
se = sorted(se, key=lambda x: x)
a = 1 / 0
async def async_design(self,
num_units: int,
num_units_nom: int,
num_units_min: int,
r_targ: float,
r_min_weak: float,
c_ext: float,
freq: float,
trf_max: float,
trst: float,
rel_err: float,
del_err: float,
td_max: float,
stack_max: int,
dig_tbm_specs: Dict[str, Any],
dig_buf_params: Dict[str, Any],
cap_in_search_params: Dict[str, Any],
res_mm_specs: Dict[str, Any],
c_odat: float,
c_odat_async: float,
c_oclkp: float,
c_oclkn: float,
cin: float,
tp_targ: float,
tmismatch: float,
trf_in: float,
tile_specs: Mapping[str, Any],
k_ratio_ctrl: float,
k_ratio_data: float,
num_sup_clear: int = 0,
design_env_name: str = '',
tile_name: str = '',
ridx_p: int = 1,
ridx_n: int = 1,
tran_options: Optional[Mapping[str, Any]] = None,
inv_input_cap_meas_seg: Optional[int] = 16,
sim_options: Optional[Mapping[str, Any]] = None,
unit_inv_cin: float = 0,
cap_in_mm_specs: str = '',
tx_dsn_specs: Mapping[str, Any] = None,
rx_dsn_specs: Mapping[str, Any] = None,
frontend_dsn_specs: Dict[str, Any] = None,
with_esd: bool = False,
**kwargs: Any) -> Mapping[str, Any]:
gen_specs: Optional[Mapping[str,
Any]] = kwargs.get('gen_cell_specs', None)
gen_cell_args: Optional[Mapping[str, Any]] = kwargs.get(
'gen_cell_args', None)
"""Run sub-hierarchy design scripts and stitch together
"""
# Get and set max widths of final drivers from tech defaults; set this in tile info
tech_info = self.dsn_tech_info
w_p = tech_info['w_maxp']
w_n = tech_info['w_maxn']
if 'lch' not in tile_specs['arr_info']:
tile_specs['arr_info']['lch'] = tech_info['lch_min']
tile_specs['place_info'][tile_name]['row_specs'][0]['width'] = w_n
tile_specs['place_info'][tile_name]['row_specs'][1]['width'] = w_p
# Make tile info
tinfo_table = TileInfoTable.make_tiles(self.grid, tile_specs)
tile_name_dict = dict(name=tile_name)
pinfo = tinfo_table.make_place_info(tile_name_dict)
if tx_dsn_specs is None and frontend_dsn_specs is None:
tx_args = dict(
num_units=num_units,
num_units_nom=num_units_nom,
num_units_min=num_units_min,
r_targ=r_targ,
r_min_weak=r_min_weak,
c_ext=c_ext,
freq=freq,
trf_max=trf_max,
trst=trst,
trf_in=trf_in,
k_ratio_ctrl=k_ratio_ctrl,
k_ratio_data=k_ratio_data,
rel_err=rel_err,
del_err=del_err,
td_max=td_max,
stack_max=stack_max,
tile_name=tile_name,
tile_specs=tile_specs,
dig_tbm_specs=dig_tbm_specs,
dig_buf_params=dig_buf_params,
cap_in_search_params=cap_in_search_params,
res_mm_specs=res_mm_specs,
ridx_p=ridx_p,
ridx_n=ridx_n,
tran_options=tran_options,
inv_input_cap_meas_seg=inv_input_cap_meas_seg,
sim_options=sim_options,
)
self._txanlg_dsnr = TXAnalogCoreDesigner(self._root_dir,
self._sim_db,
self._dsn_specs)
tx_params = await self._txanlg_dsnr.async_design(**tx_args)
else:
tx_params = tx_dsn_specs
if rx_dsn_specs is None and frontend_dsn_specs is None:
# Calculate POR cap for RX POR level shifter sizing
tx_ctrl_lv_params = tx_params['ctrl_lvshift']['dut_params'][
'params']['lv_params']
tx_data_lv_params = tx_params['data_lvshift']['dut_params'][
'params']['lv_params']
w_ctrl = tx_ctrl_lv_params['seg_dict']['rst'] * tx_ctrl_lv_params[
'w_dict']['rst']
w_data = tx_data_lv_params['seg_dict']['rst'] * tx_data_lv_params[
'w_dict']['rst']
cin_tx_por_total_w = 7 * w_ctrl + w_data
cin_tx_por_vccl = cin_tx_por_total_w / tech_info['cin_inv']['w_per_seg'] * \
tech_info['cin_inv']['cin_per_seg']
rx_args = read_yaml(kwargs['rx_specs_file'])
rx_dsn_params = rx_args['dsn_params']
rx_dsn_params['c_por_vccl_tx'] = cin_tx_por_vccl
self._rxanlg_dsnr = RXAnalogDesigner(self._root_dir, self._sim_db,
rx_dsn_params)
rx_params = (await self._rxanlg_dsnr.async_design(**rx_args
))['rx_params']
else:
rx_params = rx_dsn_specs
if frontend_dsn_specs is None:
dut_params = dict(
pinfo=pinfo,
buf_ctrl_lv_params=tx_params['ctrl_lvshift']['dut_params']
['params']['in_buf_params'],
ctrl_lv_params=tx_params['ctrl_lvshift']['dut_params']
['params']['lv_params'],
buf_por_lv_params=rx_params['buf_por_lv_params'],
por_lv_params=rx_params['por_lv_params'],
rx_lv_params=rx_params['data_lv_params'],
inv_params=rx_params['inv_params'],
se_params=rx_params['se_params'],
match_params=rx_params['match_params'],
buf_data_lv_params=tx_params['data_lvshift']['dut_params']
['params']['in_buf_params'],
tx_lv_params=tx_params['data_lvshift']['dut_params']['params']
['lv_params'],
drv_params=tx_params['driver']['dut_params']['params'],
)
else:
dut_params = frontend_dsn_specs
if not with_esd:
dut_params['pinfo'] = pinfo
print("=" * 80)
print("Frontend: Running Signoff...")
await self.verify_design(dut_params, tp_targ, tmismatch, c_ext, freq,
trst, td_max, trf_max, c_odat, c_odat_async,
c_oclkp, c_oclkn, trf_in, with_esd)
if gen_specs is not None and gen_cell_args is not None:
gen_cell_specs = dict(
lay_class=IPMarginTemplate.get_qualified_name(),
params=dict(
cls_name=GenericWrapper.get_qualified_name(),
params=dict(
cls_name=Frontend.get_qualified_name(),
params=dut_params,
),
),
**gen_specs,
)
return dict(gen_specs=gen_cell_specs, gen_args=gen_cell_args)
return dut_params
penalty += abs(
(spec_num - spec_max) / (spec_num + spec_max))
if spec_min is not None:
if spec_num < spec_min:
# penalty += abs(spec_num / spec_min - 1.0)
penalty += abs(
(spec_num - spec_min) / (spec_num + spec_min))
penalties.append(penalty)
return penalties
if __name__ == '__main__':
import pickle
evalEngine = DTSAEvaluationEngine(
design_specs_fname='specs_design/DTSA.yaml')
content = read_yaml('specs_design/DTSA.yaml')
dir = content['database_dir']
np.random.seed(10)
random.seed(10)
start = time.time()
sample_designs = evalEngine.generate_data_set(n=1, evaluate=True)
print("time: {}".format(time.time() - start))
os.makedirs(dir, exist_ok=True)
with open(dir + "/init_data.pickle", 'wb') as f:
pickle.dump(sample_designs, f)
with open(dir + "/init_data.pickle", 'rb') as f:
data = pickle.load(f)
se = [x.cost for x in data]
# generate design/testbench schematics
gen_schematics(prj, specs, dsn_name, dsn_sch_params, check_lvs=run_lvs)
# run simulation and import results
simulate(prj, specs, dsn_name)
# load simulation results from save file
res_dict = load_sim_data(specs, dsn_name)
# post-process simulation results
plot_data(res_dict)
if __name__ == '__main__':
spec_fname = 'specs_demo/demo.yaml'
# load specifications from file
top_specs = read_yaml(spec_fname)
# create BagProject object
local_dict = locals()
if 'bprj' in local_dict:
print('using existing BagProject')
bprj = local_dict['bprj']
else:
print('creating BagProject')
bprj = BagProject()
# routing_demo(bprj, top_specs)
run_flow(bprj, top_specs, 'amp_cs')
# gen_layout(bprj, top_specs, 'amp_sf')
# bprj.import_design_library('demo_templates')
# run_flow(bprj, top_specs, 'amp_sf')
