def cover_pending_counter(bld: Builder):
m = Module()
m.submodules.pc = pc = PendingCounter(3, 5)
was_full = Signal()
was_emptied = Signal()
m.d.comb += pc.i_remove.eq(AnySeq(1))
m.d.comb += Assume(~(pc.i_remove & ~pc.o_any))
m.d.comb += Assume(~(~pc.i_remove & pc.o_full))
with m.If(pc.o_full):
m.d.sync += was_full.eq(1)
with m.If(~pc.o_any & was_full):
m.d.sync += was_emptied.eq(1)
m.d.comb += Cover(was_emptied)
with bld.temp_open("formal.il") as f:
il_text = rtlil.convert(m, ports=[pc.pending, pc.timer])
f.write(il_text)
sby.verify(
bld,
"formal.sby",
"formal.il",
sby.Task("sby", "cover", depth=40, engines=["smtbmc", "yices"]),
)
def cover(bld: Builder):
build_formal(bld)
sby.verify(
bld,
"cover.sby",
"formal.il",
sby.Task("sby_cover", "cover", depth=8, engines=["smtbmc", "yices"]),
)
def prove(bld: Builder):
build_formal(bld)
sby.verify(
bld,
"prove.sby",
"formal.il",
sby.Task("sby_prove", "prove", depth=3, engines=["smtbmc", "yices"]),
)
def bmc_pending_counter(bld: Builder):
m = Module()
m.submodules.pc = pc = PendingCounter(3, 5)
m.d.comb += pc.i_remove.eq(AnySeq(1))
m.d.comb += Assume(~(pc.i_remove & ~pc.o_any))
m.d.comb += Assume(~(~pc.i_remove & pc.o_full))
with bld.temp_open("formal.il") as f:
il_text = rtlil.convert(m, ports=[pc.pending, pc.timer])
f.write(il_text)
sby.verify(
bld,
"formal.sby",
"formal.il",
sby.Task("sby", "bmc", depth=40, engines=["smtbmc", "yices"]),
)