def test_type_invalid_2(self, not_an_int: Any) -> None:
circuit = Circuit(4, [2, 2, 3, 3])
try:
circuit.append_circuit(not_an_int, not_an_int)
except TypeError:
return
except BaseException:
assert False, 'Unexpected Exception.'
def test_type_valid_2(self) -> None:
circuit = Circuit(4, [2, 2, 3, 3])
circuit_to_add = Circuit(1)
circuit_to_add.append_gate(HGate(), [0])
try:
circuit.append_circuit(circuit_to_add, [0])
except TypeError:
assert False, 'Unexpected TypeError.'
except BaseException:
return
def run(self, circuit: Circuit, data: dict[str, Any]) -> None:
"""
Perform the pass's operation, see BasePass for more info.
Raises:
ValueError: if a block file and the corresponding index in
`structure.pickle` are differnt lengths.
"""
# If the circuit is empty, just append blocks in order
if circuit.get_depth() == 0:
for block in self.block_list:
# Get block
block_num = int(findall(r'\d+', block)[0])
with open(self.proj_dir + '/' + block) as f:
block_circ = OPENQASM2Language().decode(f.read())
# Get location
block_location = self.structure[block_num]
if block_circ.get_size() != len(block_location):
raise ValueError(
f'{block} and `structure.pickle` locations are '
'different sizes.', )
# Append to circuit
circuit.append_circuit(block_circ, block_location)
