def test_ne_uuid(self):
cc1 = bt2.CtfWriterClock(name='name', description='some description',
frequency=1001, precision=176,
offset=bt2.ClockClassOffset(45, 3003),
is_absolute=True, uuid=uuid.uuid1())
cc2 = bt2.CtfWriterClock(name='name', description='some description',
frequency=1001, precision=176,
offset=bt2.ClockClassOffset(45, 3003),
is_absolute=True, uuid=uuid.uuid1())
self.assertNotEqual(cc1, cc2)
def source_setup(src, test_name):
cc1 = src._create_clock_class(frequency=1,
name='La Baie',
offset=bt2.ClockClassOffset(0))
cc2 = src._create_clock_class(frequency=1,
name='Chicoutimi',
offset=bt2.ClockClassOffset(0))
src._add_output_port('out1', (test_name, cc1))
src._add_output_port('out2', (test_name, cc2))
def source_setup(src, test_name):
tc1 = src._create_trace_class()
cc1 = src._create_clock_class(frequency=1, offset=bt2.ClockClassOffset(0))
tc2 = src._create_trace_class()
cc2 = src._create_clock_class(frequency=1, offset=bt2.ClockClassOffset(0))
stream_id1 = 18
stream_id2 = 23
src._add_output_port('out1', (test_name, 1, tc1, cc1, stream_id1))
src._add_output_port('out2', (test_name, 2, tc2, cc2, stream_id2))
def source_setup(src, test_name):
tc1 = src._create_trace_class()
cc1 = src._create_clock_class(frequency=1, offset=bt2.ClockClassOffset(0))
tc2 = src._create_trace_class()
cc2 = src._create_clock_class(frequency=1, offset=bt2.ClockClassOffset(0))
stream_name1 = 'port-daniel'
stream_name2 = 'gascon'
src._add_output_port('out1', (test_name, 1, tc1, cc1, stream_name1))
src._add_output_port('out2', (test_name, 2, tc2, cc2, stream_name2))
def source_setup(src, test_name):
tc1 = src._create_trace_class(assigns_automatic_stream_class_id=False)
cc1 = src._create_clock_class(frequency=1, offset=bt2.ClockClassOffset(0))
tc2 = src._create_trace_class(assigns_automatic_stream_class_id=False)
cc2 = src._create_clock_class(frequency=1, offset=bt2.ClockClassOffset(0))
event_class_id1 = 1
event_class_id2 = 2
src._add_output_port('out1', (test_name, 1, tc1, cc1, event_class_id1))
src._add_output_port('out2', (test_name, 2, tc2, cc2, event_class_id2))
def source_setup(src, test_name):
tc1 = src._create_trace_class()
cc1 = src._create_clock_class(frequency=1, offset=bt2.ClockClassOffset(0))
tc2 = src._create_trace_class()
cc2 = src._create_clock_class(frequency=1, offset=bt2.ClockClassOffset(0))
trace_name1 = 'rouyn'
trace_name2 = 'noranda'
src._add_output_port('out1', (test_name, 1, tc1, cc1, trace_name1))
src._add_output_port('out2', (test_name, 2, tc2, cc2, trace_name2))
def source_setup(src, test_name):
tc1 = src._create_trace_class(assigns_automatic_stream_class_id=False)
cc1 = src._create_clock_class(frequency=1, offset=bt2.ClockClassOffset(0))
tc2 = src._create_trace_class(assigns_automatic_stream_class_id=False)
cc2 = src._create_clock_class(frequency=1, offset=bt2.ClockClassOffset(0))
stream_class_name1 = 'one'
stream_class_name2 = 'two'
src._add_output_port('out1', (test_name, 1, tc1, cc1, stream_class_name1))
src._add_output_port('out2', (test_name, 2, tc2, cc2, stream_class_name2))
def test_create_full(self):
my_uuid = uuid.uuid1()
cc = bt2.CtfWriterClock(name='name', description='some description',
frequency=1001, precision=176,
offset=bt2.ClockClassOffset(45, 3003),
is_absolute=True, uuid=my_uuid)
self.assertEqual(cc.name, 'name')
self.assertEqual(cc.description, 'some description')
self.assertEqual(cc.frequency, 1001)
self.assertEqual(cc.precision, 176)
self.assertEqual(cc.offset, bt2.ClockClassOffset(45, 3003))
self.assertEqual(cc.is_absolute, True)
self.assertEqual(cc.uuid, copy.deepcopy(my_uuid))
def f(comp_self):
cc = comp_self._create_clock_class(
1000, 'my_cc', offset=bt2.ClockClassOffset(45, 354)
)
tc = comp_self._create_trace_class()
return (cc, tc)
def test_create_offset(self):
def f(comp_self):
return comp_self._create_clock_class(
offset=bt2.ClockClassOffset(12, 56))
cc = run_in_component_init(f)
self.assertEqual(cc.offset, bt2.ClockClassOffset(12, 56))
def offset(self):
ret, offset_s = native_bt.ctf_clock_get_offset_s(self._ptr)
utils._handle_ret(
ret, "cannot get CTF writer clock object's offset (seconds)")
ret, offset_cycles = native_bt.ctf_clock_get_offset(self._ptr)
utils._handle_ret(
ret, "cannot get CTF writer clock object's offset (cycles)")
return bt2.ClockClassOffset(offset_s, offset_cycles)
def test_eq(self):
my_uuid = uuid.uuid1()
cc1 = bt2.ClockClass(name='name',
description='some description',
frequency=1001,
precision=176,
offset=bt2.ClockClassOffset(45, 3003),
is_absolute=True,
uuid=my_uuid)
cc2 = bt2.ClockClass(name='name',
description='some description',
frequency=1001,
precision=176,
offset=bt2.ClockClassOffset(45, 3003),
is_absolute=True,
uuid=my_uuid)
self.assertEqual(cc1, cc2)
def test_create_default(self):
cc = run_in_component_init(lambda comp_self: comp_self._create_clock_class())
self.assertIsNone(cc.name)
self.assertEqual(cc.frequency, 1000000000)
self.assertIsNone(cc.description)
self.assertEqual(cc.precision, 0)
self.assertEqual(cc.offset, bt2.ClockClassOffset())
self.assertTrue(cc.origin_is_unix_epoch)
self.assertIsNone(cc.uuid)
self.assertEqual(len(cc.user_attributes), 0)
def source_setup(src, test_name):
tc1 = src._create_trace_class(assigns_automatic_stream_class_id=False)
tc2 = src._create_trace_class(assigns_automatic_stream_class_id=False)
tc3 = src._create_trace_class(assigns_automatic_stream_class_id=False)
tc4 = src._create_trace_class(assigns_automatic_stream_class_id=False)
cc = src._create_clock_class(frequency=1, offset=bt2.ClockClassOffset(0))
src._add_output_port('out1', (test_name, 1, tc1, cc))
src._add_output_port('out2', (test_name, 2, tc2, cc))
src._add_output_port('out3', (test_name, 3, tc3, cc))
src._add_output_port('out4', (test_name, 4, tc4, cc))
def source_setup(src, test_name):
tc = src._create_trace_class()
cc = src._create_clock_class(frequency=1, offset=bt2.ClockClassOffset(0))
timestamp1 = 0
timestamp2 = 120
timestamp3 = 4
src._add_output_port('out1', (test_name, 1, tc, cc, timestamp1))
src._add_output_port('out2', (test_name, 2, tc, cc, timestamp2))
src._add_output_port('out3', (test_name, 3, tc, cc, timestamp3))
def __init__(self, config, params, obj):
# Checks what types of event are available
self.connection = connect_to_db(str(params["input"]))
if self.connection is None:
raise Exception("Trace input not supported: {}".format(
params["input"]))
event_types_available = detect_input_table(self.connection)
# Add performance counter to the list of fields of compute_kernels_hsa
if "compute_kernels_hsa" in event_types_available:
event_types_available["compute_kernels_hsa"] = add_optional_fields(
self.connection, event_types_available["compute_kernels_hsa"])
# Initiliazes the metadata objects of the trace
rocm_trace = self._create_trace_class()
# Initializes the clock
frequency = 1000000000
offset = time.time() - time.clock_gettime(time.CLOCK_MONOTONIC)
offset_seconds = int(offset)
offset_cycles = int((offset - offset_seconds) * frequency)
clock_class = self._create_clock_class(
name="rocm_monotonic",
frequency=frequency, # 1 GHz
precision=1, # Nanosecond precision
offset=bt2.ClockClassOffset(offset_seconds, offset_cycles),
origin_is_unix_epoch=True,
uuid=uuid.uuid4())
for event_type in event_types_available:
# Stream classes
event_types_available[event_type]["stream_class"] = (
rocm_trace.create_stream_class(
default_clock_class=clock_class))
# Field classes
payload_class = rocm_trace.create_structure_field_class()
event_types_available[event_type]["payload_class"] = payload_class
get_payload_class(event_types_available[event_type], rocm_trace,
payload_class)
# Event classes
event_types_available[event_type]["event_class"] = (
event_types_available[event_type]
["stream_class"].create_event_class(
name=event_type,
payload_field_class=event_types_available[event_type]
["payload_class"]))
# Same trace object for all ports
trace = rocm_trace(environment={"tracer_name": "roctracer"})
for event_type in event_types_available:
self._add_output_port(
"out_" + event_type, {
"trace": trace,
"event_type": event_types_available[event_type],
"connection": self.connection
})
def __init__(self, config, params, obj):
tc = self._create_trace_class()
# Use a clock class with an offset, so we can test with --begin or --end
# smaller than this offset (in other words, a time that it's not
# possible to represent with this clock class).
cc = self._create_clock_class(frequency=1,
offset=bt2.ClockClassOffset(10000))
sc = tc.create_stream_class(
default_clock_class=cc,
supports_packets=True,
packets_have_beginning_default_clock_snapshot=True,
packets_have_end_default_clock_snapshot=True,
)
ec1 = sc.create_event_class(name='event 1')
ec2 = sc.create_event_class(name='event 2')
self._add_output_port('out', (tc, sc, ec1, ec2, params))
def test_create(self):
cco = bt2.ClockClassOffset(23, 4871232)
self.assertEqual(cco.seconds, 23)
self.assertEqual(cco.cycles, 4871232)
def test_eq_invalid(self):
self.assertFalse(bt2.ClockClassOffset() == 23)
def test_ne_cycles(self):
cco1 = bt2.ClockClassOffset(23, 42)
cco2 = bt2.ClockClassOffset(23, 43)
self.assertNotEqual(cco1, cco2)
def test_ne_seconds(self):
cco1 = bt2.ClockClassOffset(23, 42)
cco2 = bt2.ClockClassOffset(24, 42)
self.assertNotEqual(cco1, cco2)
def test_eq(self):
cco1 = bt2.ClockClassOffset(23, 42)
cco2 = bt2.ClockClassOffset(23, 42)
self.assertEqual(cco1, cco2)
def test_create_invalid_cycles(self):
with self.assertRaises(TypeError):
bt2.ClockClassOffset(23, 'hello')
def test_create_invalid_seconds(self):
with self.assertRaises(TypeError):
bt2.ClockClassOffset('hello', 4871232)
def test_create_kwargs(self):
cco = bt2.ClockClassOffset(seconds=23, cycles=4871232)
self.assertEqual(cco.seconds, 23)
self.assertEqual(cco.cycles, 4871232)
def test_create_default(self):
cco = bt2.ClockClassOffset()
self.assertEqual(cco.seconds, 0)
self.assertEqual(cco.cycles, 0)
def f(comp_self):
return comp_self._create_clock_class(offset=bt2.ClockClassOffset(12, 56))
def offset(self):
ret, offset_s = native_bt.ctf_clock_get_offset_s(self._ptr)
assert (ret == 0)
ret, offset_cycles = native_bt.ctf_clock_get_offset(self._ptr)
assert (ret == 0)
return bt2.ClockClassOffset(offset_s, offset_cycles)
def setUp(self):
self._cc = bt2.ClockClass('salut',
1000,
offset=bt2.ClockClassOffset(45, 354))
self._cv = self._cc(123)
def test_assign_offset(self):
self._cc.offset = bt2.ClockClassOffset(12, 56)
self.assertEqual(self._cc.offset, bt2.ClockClassOffset(12, 56))