def get_txip(self):
"""
Get current data transmission IP base in string form
"""
txip = self.txip.read()['data']['txip']
txip_str = tengbe.ip2str(txip)
return txip_str
def set_destination(self, ip_and_port):
ip, port = ip_and_port.split(':')
port = int(port)
ip_octets = [int(bit) for bit in ip.split('.')]
assert len(ip_octets) == 4, 'That\'s an odd IP address...'
ip_base = ip_octets[3]
ip_prefix = '%d.%d.%d.' % (ip_octets[0], ip_octets[1], ip_octets[2])
for gbectr, gbe in enumerate(self.tengbes):
this_ip = tengbe.str2ip('%s%d' % (ip_prefix, ip_base))
self.registers['gbe_iptx%i' % gbectr].write(reg=this_ip)
LOGGER.info('gbe(%s) sending to IP(%s) port(%i)' %
(gbe.name, tengbe.ip2str(this_ip), port))
ip_base += 1
self.registers.gbe_porttx.write(reg=port)
def set_destination(self, txip_str=None, txport=None, issue_meta=True):
"""Set destination for output of fxcorrelator.
"""
if txip_str is None:
txip = tengbe.str2ip(self.txip_str)
else:
txip = tengbe.str2ip(txip_str)
if txport is None:
txport = self.txport
for f in self.xhosts:
f.registers.txip.write(txip=txip)
f.registers.txport.write(txport=txport)
self.txip_str = tengbe.ip2str(txip)
self.txport = txport
if issue_meta:
self.spead_issue_meta()
def print_gbe_tx(only_eofs=False, num_lines=-1):
# read the tengbe snapshot on tx
stx = fdig.devices['snap_gbe_tx_ss']
txgbedata = stx.read(man_valid=False)['data']
if num_lines == -1:
num_lines = len(txgbedata['data'])
for ctr in range(0, num_lines):
pstr = '%05i ' % ctr
pstr2 = ''
for key in txgbedata.keys():
if key == 'ip':
pstr = '%s%s(%s) ' % (pstr, key, tengbe.ip2str(txgbedata[key][ctr]))
else:
pstr = '%s%s(%i) ' % (pstr, key, txgbedata[key][ctr])
pstr2 = '%s %i' % (pstr2, txgbedata[key][ctr])
if only_eofs:
if txgbedata['eof'][ctr]:
print pstr
else:
print pstr
fpgautils.threaded_fpga_function(fpgas, 10, 'disconnect')
raise RuntimeError
if args.rstcnt:
if 'unpack_cnt_rst' in fpgas[0].registers.control.field_names():
fpgautils.threaded_fpga_operation(fpgas, 10,
lambda fpga_: fpga_.registers.control.write(cnt_rst='pulse',
unpack_cnt_rst='pulse'))
else:
fpgautils.threaded_fpga_operation(fpgas, 10,
lambda fpga_: fpga_.registers.control.write(cnt_rst='pulse',
up_cnt_rst='pulse'))
tx_ips = {}
for fpga in fpgas:
tx_ips[fpga.host] = {'ip0': {}, 'ip1': {}, 'ip2': {}, 'ip3': {}, 'port0': {}, 'port1': {}, 'port2': {}, 'port3': {}}
print fpga.host, ip2str(fpga.registers.iptx_base.read()['data']['reg']), fpga.registers.tx_metadata.read()['data']
def get_fpga_data(fpga):
txips = {'ip0': {}, 'ip1': {}, 'ip2': {}, 'ip3': {}, 'port0': {}, 'port1': {}, 'port2': {}, 'port3': {}}
for ctr in range(0, 4):
txip = fpga.registers['txip%i'%ctr].read()['data']['ip']
txips['ip%i' % ctr] = txip
txport = fpga.registers.txpport01.read()['data']
txport.update(fpga.registers.txpport23.read()['data'])
for ctr in range(0, 4):
txips['port%i' % ctr] = txport['port%i'%ctr]
return txips
import signal
def signal_handler(sig, frame):
current_fchan = -1
coredata = fpga.tengbes[args.core].read_rxsnap()
print '.',
sys.stdout.flush()
for ctr in range(0, len(coredata[coredata.keys()[0]])):
packet_length_error = False
if coredata[eof_key][ctr]:
if args.spead and (packet_counter != spead_info['packet_length'] + 1):
packet_length_error = True
packet_counter = 0
if verbose:
print '%5d,%3d' % (ctr, packet_counter),
for key in key_order:
if key == ip_key:
if verbose:
print '%s(%s)' % (key, tengbe.ip2str(coredata[key][ctr])), '\t',
elif (key == data_key) and args.spead:
new_spead_info, spead_stringdata = process_spead(spead_info, coredata[data_key][ctr], packet_counter)
if new_spead_info != None:
spead_info = new_spead_info.copy()
if verbose:
print '%s(%s)' % (key, spead_stringdata), '\t',
else:
if verbose:
print '%s(%s)' % (key, coredata[key][ctr]), '\t',
if verbose:
print 'PACKET LENGTH ERROR' if packet_length_error else ''
packet_counter += 1
discovered_fchans.sort()
print discovered_fchans
for fpga in all_fpgas:
fpga.disconnect()
sys.exit()
def print_gbe_tx(only_eofs=False, num_lines=-1):
# read the tengbe snapshot on tx
stx = fdig.devices['snap_gbe_tx_ss']
txgbedata = stx.read(man_valid=False)['data']
if num_lines == -1:
num_lines = len(txgbedata['data'])
for ctr in range(0, num_lines):
pstr = '%05i ' % ctr
pstr2 = ''
for key in txgbedata.keys():
if key == 'ip':
pstr = '%s%s(%s) ' % (pstr, key, tengbe.ip2str(txgbedata[key][ctr]))
else:
pstr = '%s%s(%i) ' % (pstr, key, txgbedata[key][ctr])
pstr2 = '%s %i' % (pstr2, txgbedata[key][ctr])
if only_eofs:
if txgbedata['eof'][ctr]:
print(pstr
else:
print(pstr
def print_gbe_rx(only_eofs=False):
srx = ffpgas[0].devices['snap_gbe_rx00_ss']
rxgbedata = srx.read(man_trig=True, man_valid=True)['data']
for ctr in range(0, len(rxgbedata['data'])):
pstr = '%05i ' % ctr
for key in rxgbedata.keys():
print registers_missing
fpgautils.threaded_fpga_function(fpgas, 10, 'disconnect')
raise RuntimeError
if args.rstcnt:
if 'unpack_cnt_rst' in fpgas[0].registers.control.field_names():
fpgautils.threaded_fpga_operation(fpgas, 10,
lambda fpga_: fpga_.registers.control.write(cnt_rst='pulse',
unpack_cnt_rst='pulse'))
else:
fpgautils.threaded_fpga_operation(fpgas, 10,
lambda fpga_: fpga_.registers.control.write(cnt_rst='pulse',
up_cnt_rst='pulse'))
for f in fpgas:
print f.host, ip2str(f.registers.iptx_base.read()['data']['reg']), f.registers.tx_metadata.read()['data']
def get_fpga_data(fpga):
rv = {}
for necreg in regs:
tempdata = fpga.registers[necreg].read()['data']
for key, value in tempdata.items():
rv[key] = value
return rv
import signal
def signal_handler(sig, frame):
print sig, frame
fpgautils.threaded_fpga_function(fpgas, 10, 'disconnect')
scroll.screen_teardown()
