def set_txip(self, txip_str=None, issue_meta=True):
""" Set base transmission IP for SPEAD output
@param txip_str: IP address in string form
"""
if txip_str is None:
txip = tengbe.str2ip(self.config['data_product']['txip_str'])
else:
txip = tengbe.str2ip(txip_str)
self.txip.write(txip=txip)
def digitiser_start(dig_tx_tuple):
fdig = KatcpClientFpga(dhost)
fdig.deprogram()
stime = time.time()
print 'Programming digitiser',
sys.stdout.flush()
fdig.upload_to_ram_and_program(dbof)
print time.time() - stime
fdig.test_connection()
fdig.get_system_information()
# stop sending data
fdig.registers.control.write(gbe_txen = False)
# start the local timer on the test d-engine - mrst, then a fake sync
fdig.registers.control.write(mrst = 'pulse')
fdig.registers.control.write(msync = 'pulse')
# the all_fpgas have tengbe cores, so set them up
ip_bits = dip_start.split('.')
ipbase = int(ip_bits[3])
mac_bits = dmac_start.split(':')
macbase = int(mac_bits[5])
for ctr in range(0,4):
mac = '%s:%s:%s:%s:%s:%d' % (mac_bits[0], mac_bits[1], mac_bits[2], mac_bits[3], mac_bits[4], macbase + ctr)
ip = '%s.%s.%s.%d' % (ip_bits[0], ip_bits[1], ip_bits[2], ipbase + ctr)
fdig.tengbes['gbe%d' % ctr].setup(mac=mac, ipaddress=ip, port=7777)
for gbe in fdig.tengbes:
gbe.tap_start(True)
# set the destination IP and port for the tx
txaddr = dig_tx_tuple[0]
txaddr_bits = txaddr.split('.')
txaddr_base = int(txaddr_bits[3])
txaddr_prefix = '%s.%s.%s.' % (txaddr_bits[0], txaddr_bits[1], txaddr_bits[2])
print 'digitisers sending to: %s%d port %d' % (txaddr_prefix, txaddr_base + 0, dig_tx_tuple[2])
fdig.write_int('gbe_iptx0', tengbe.str2ip('%s%d' % (txaddr_prefix, txaddr_base + 0)))
fdig.write_int('gbe_iptx1', tengbe.str2ip('%s%d' % (txaddr_prefix, txaddr_base + 1)))
fdig.write_int('gbe_iptx2', tengbe.str2ip('%s%d' % (txaddr_prefix, txaddr_base + 2)))
fdig.write_int('gbe_iptx3', tengbe.str2ip('%s%d' % (txaddr_prefix, txaddr_base + 3)))
fdig.write_int('gbe_porttx', dig_tx_tuple[2])
fdig.registers.control.write(gbe_rst=False)
# enable the tvg on the digitiser and set up the pol id bits
fdig.registers.control.write(tvg_select0=True)
fdig.registers.control.write(tvg_select1=True)
fdig.registers.id2.write(pol1_id=1)
# start tx
print 'Starting dig TX...',
sys.stdout.flush()
fdig.registers.control.write(gbe_txen=True)
print 'done.'
sys.stdout.flush()
fdig.disconnect()
def set_destination(self, txip_str=None, txport=None, issue_meta=True):
"""Set destination for output of fxcorrelator.
"""
if txip_str is None:
txip = tengbe.str2ip(self.txip_str)
else:
txip = tengbe.str2ip(txip_str)
if txport is None:
txport = self.txport
for f in self.xhosts:
f.registers.txip.write(txip=txip)
f.registers.txport.write(txport=txport)
self.txip_str = tengbe.ip2str(txip)
self.txport = txport
if issue_meta:
self.spead_issue_meta()
def set_destination(self, ip_and_port):
ip, port = ip_and_port.split(':')
port = int(port)
ip_octets = [int(bit) for bit in ip.split('.')]
assert len(ip_octets) == 4, 'That\'s an odd IP address...'
ip_base = ip_octets[3]
ip_prefix = '%d.%d.%d.' % (ip_octets[0], ip_octets[1], ip_octets[2])
for gbectr, gbe in enumerate(self.tengbes):
this_ip = tengbe.str2ip('%s%d' % (ip_prefix, ip_base))
self.registers['gbe_iptx%i' % gbectr].write(reg=this_ip)
LOGGER.info('gbe(%s) sending to IP(%s) port(%i)' %
(gbe.name, tengbe.ip2str(this_ip), port))
ip_base += 1
self.registers.gbe_porttx.write(reg=port)
def _fengine_initialise(self):
"""
Set up f-engines on this device.
:return:
"""
feng_ip_octets = [int(bit) for bit in self.configd['fengine']['10gbe_start_ip'].split('.')]
assert len(feng_ip_octets) == 4, 'That\'s an odd IP address.'
feng_ip_base = feng_ip_octets[3]
feng_ip_prefix = '%d.%d.%d.' % (feng_ip_octets[0], feng_ip_octets[1], feng_ip_octets[2])
macbase = 10
board_id = 0
for ctr, f in enumerate(self.fhosts):
if use_demo_fengine:
f.registers.control.write(gbe_txen=False)
else:
f.registers.control.write(comms_en=False)
for ctr, f in enumerate(self.fhosts):
if use_demo_fengine:
f.registers.control.write(gbe_rst=False)
f.registers.control.write(clr_status='pulse', gbe_cnt_rst='pulse', cnt_rst='pulse')
else:
f.registers.control.write(comms_rst=True)
f.registers.control.write(status_clr='pulse', comms_status_clr='pulse')
# comms stuff
for gbe in f.tengbes:
gbe.setup(mac='02:02:00:00:01:%02x' % macbase, ipaddress='%s%d' % (feng_ip_prefix, feng_ip_base),
port=7777)
macbase += 1
feng_ip_base += 1
if use_demo_fengine:
f.registers.iptx_base.write_int(tengbe.str2ip(self.configd['xengine']['10gbe_start_ip']))
f.registers.tx_metadata.write(board_id=board_id, porttx=int(self.configd['xengine']['10gbe_start_port']))
else:
f.registers.board_id.write_int(board_id)
f.registers.txip.write_int(tengbe.str2ip(self.configd['xengine']['10gbe_start_ip']))
f.registers.txport.write_int(int(self.configd['xengine']['10gbe_start_port']))
board_id += 1
# start tap on the f-engines
for ctr, f in enumerate(self.fhosts):
for gbe in f.tengbes:
gbe.tap_start(True)
# release from reset
for ctr, f in enumerate(self.fhosts):
if use_demo_fengine:
f.registers.control.write(gbe_rst=False)
else:
f.registers.control.write(comms_rst=False)
# subscribe to multicast data
for ctr, f in enumerate(self.fhosts):
rxaddr = self.source_mcast[0][0]
rxaddr_bits = rxaddr.split('.')
rxaddr_base = int(rxaddr_bits[3])
rxaddr_prefix = '%s.%s.%s.' % (rxaddr_bits[0], rxaddr_bits[1], rxaddr_bits[2])
ctr = 0
for gbe in f.tengbes:
rxaddress = '%s%d' % (rxaddr_prefix, rxaddr_base + ctr)
print 'host %s %s subscribing to address %s' % (f.host, gbe.name, rxaddress)
gbe.multicast_receive(rxaddress, 0)
ctr += 1
mac_bits = mac_start.split(':')
macbase = int(mac_bits[5])
num_tengbes = len(fdig.tengbes)
if num_tengbes < 1:
raise RuntimeError('D-engine with no 10gbe cores %s' % fdig.host)
for ctr in range(num_tengbes):
mac = '%s:%s:%s:%s:%s:%d' % (mac_bits[0], mac_bits[1], mac_bits[2], mac_bits[3], mac_bits[4], macbase + ctr)
ip = '%s.%s.%s.%d' % (ip_bits[0], ip_bits[1], ip_bits[2], ipbase + ctr)
fdig.tengbes['gbe%d' % ctr].setup(mac=mac, ipaddress=ip, port=7777)
for gbe in fdig.tengbes:
gbe.tap_start(True)
# set the destination IP and port for the tx
if not args.unicast:
fdig.write_int('gbe_iptx0', tengbe.str2ip('239.2.0.64'))
fdig.write_int('gbe_iptx1', tengbe.str2ip('239.2.0.65'))
fdig.write_int('gbe_iptx2', tengbe.str2ip('239.2.0.66'))
fdig.write_int('gbe_iptx3', tengbe.str2ip('239.2.0.67'))
else:
fdig.write_int('gbe_iptx0', tengbe.str2ip('10.0.0.90'))
fdig.write_int('gbe_iptx1', tengbe.str2ip('10.0.0.91'))
fdig.write_int('gbe_iptx2', tengbe.str2ip('10.0.0.92'))
fdig.write_int('gbe_iptx3', tengbe.str2ip('10.0.0.93'))
fdig.write_int('gbe_porttx', 7777)
fdig.registers.control.write(gbe_rst=False)
# enable the tvg on the digitiser and set up the pol id bits
fdig.registers.control.write(tvg_select0=True)
fdig.registers.control.write(tvg_select1=True)
# the all_fpgas have tengbe cores, so set them up
fipbase = 150
xipbase = 110
fdig.tengbes.gbe0.setup(mac='02:02:00:00:00:01', ipaddress='10.0.0.70', port=7777)
fdig.tengbes.gbe1.setup(mac='02:02:00:00:00:02', ipaddress='10.0.0.71', port=7777)
fdig.tengbes.gbe2.setup(mac='02:02:00:00:00:03', ipaddress='10.0.0.72', port=7777)
fdig.tengbes.gbe3.setup(mac='02:02:00:00:00:04', ipaddress='10.0.0.73', port=7777)
macbase = 10
board_id = 0
for fpga in ffpgas:
for gbe in fpga.tengbes:
gbe.setup(mac='02:02:00:00:01:%02x' % macbase, ipaddress='10.0.0.%d' % fipbase, port=7777)
macbase += 1
fipbase += 1
fpga.registers.iptx_base.write_int(tengbe.str2ip('10.0.0.%d' % xipbase))
fpga.registers.tx_metadata.write(board_id=board_id, porttx=8778)
board_id += 1
macbase = 10
board_id = 0
for fpga in xfpgas:
for gbe in fpga.tengbes:
gbe.setup(mac='02:02:00:00:02:%02x' % macbase, ipaddress='10.0.0.%d' % xipbase, port=8778)
macbase += 1
xipbase += 1
fpga.registers.board_id.write_int(board_id)
board_id += 4 # see the model file as to why this must incrementby 4 - this needs to be changed!!
# tap start
for fpga in all_fpgas:
for gbe in fpga.tengbes:
macbase = int(mac_bits[5])
for ctr in range(0, 4):
mac = '%s:%s:%s:%s:%s:%d' % (mac_bits[0], mac_bits[1], mac_bits[2], mac_bits[3], mac_bits[4], macbase + ctr)
ip = '%s.%s.%s.%d' % (ip_bits[0], ip_bits[1], ip_bits[2], ipbase + ctr)
fdig.tengbes['gbe%d' % ctr].setup(mac=mac, ipaddress=ip, port=DIG_TX_PORT)
for gbe in fdig.tengbes:
gbe.tap_start(True)
# set the destination IP and port for the tx
txaddr = DIG_TX_IP_START
txaddr_bits = txaddr.split('.')
txaddr_base = int(txaddr_bits[3])
txaddr_prefix = '%s.%s.%s.' % (txaddr_bits[0], txaddr_bits[1], txaddr_bits[2])
for ctr in range(0, 4):
txip = txaddr_base + ctr
print '%s sending to: %s%d port %d' % (fdig.host, txaddr_prefix, txip, DIG_TX_PORT)
fdig.write_int('gbe_iptx%i' % ctr, tengbe.str2ip('%s%d' % (txaddr_prefix, txip)))
fdig.write_int('gbe_porttx', DIG_TX_PORT)
fdig.registers.control.write(gbe_rst=False)
# enable the tvg on the digitiser and set up the pol id bits
fdig.registers.control.write(tvg_select0=1)
fdig.registers.control.write(tvg_select1=1)
fdig.registers.id2.write(pol1_id=1)
else:
fdig.get_system_information()
if args.deprogram:
fdig.deprogram()
print 'Deprogrammed %s.' % fdig.host
if args.stop:
fdig.registers.control.write(gbe_txen=False)
