def runTest(self): config_file = "{}/tests/configs/config".format( os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload import characterizer reload(characterizer) from characterizer import functional if not OPTS.spice_exe: debug.error("Could not find {} simulator.".format(OPTS.spice_name), -1) from sram_config import sram_config c = sram_config(word_size=4, num_words=128, num_banks=1) c.words_per_row = 8 c.recompute_sizes() debug.info( 1, "Functional test for sram with " "{} bit words, {} words, {} words per row, {} banks".format( c.word_size, c.num_words, c.words_per_row, c.num_banks)) s = factory.create(module_type="sram", sram_config=c) tempspice = OPTS.openram_temp + "sram.sp" s.sp_write(tempspice) f = functional(s.s, tempspice) (fail, error) = f.run() self.assertTrue(fail, error) globals.end_openram()
def runTest(self): globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload import characterizer reload(characterizer) from characterizer import functional, delay from sram_config import sram_config c = sram_config(word_size=4, num_words=32, num_banks=1) c.words_per_row = 2 c.recompute_sizes() debug.info( 1, "Functional test for sram with " "{} bit words, {} words, {} words per row, {} banks".format( c.word_size, c.num_words, c.words_per_row, c.num_banks)) s = factory.create(module_type="sram", sram_config=c) tempspice = OPTS.openram_temp + "sram.sp" s.sp_write(tempspice) corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) f = functional(s.s, tempspice, corner) (fail, error) = f.run() self.assertTrue(fail, error) globals.end_openram()
def runTest(self): config_file = "{}/tests/configs/config".format( os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.use_pex = True # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload import characterizer reload(characterizer) from characterizer import functional from sram_config import sram_config c = sram_config(word_size=4, num_words=32, num_banks=1) c.words_per_row = 2 c.recompute_sizes() debug.info( 1, "Functional test for sram with " "{} bit words, {} words, {} words per row, {} banks".format( c.word_size, c.num_words, c.words_per_row, c.num_banks)) s = factory.create(module_type="sram", sram_config=c) tempspice = self.run_pex(s) corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) f = functional(s.s, tempspice, corner) (fail, error) = f.run() self.assertTrue(fail, error) globals.end_openram()
def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 1 # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload import characterizer reload(characterizer) from characterizer import functional, delay from sram import sram from sram_config import sram_config c = sram_config(word_size=4, num_words=32, num_banks=1) c.words_per_row=1 c.recompute_sizes() debug.info(1, "Functional test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, OPTS.num_r_ports, OPTS.num_w_ports, c.word_size, c.num_words, c.words_per_row, c.num_banks)) s = sram(c, name="sram") tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) f = functional(s.s, tempspice, corner) d = delay(s.s, tempspice, corner) feasible_period = self.find_feasible_test_period(d, s.s, f.load, f.slew) f.num_cycles = 10 (fail, error) = f.run() self.assertTrue(fail,error) globals.end_openram()
def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" OPTS.dummy_bitcell="dummy_pbitcell" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 1 # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload import characterizer reload(characterizer) from characterizer import functional, delay from sram_config import sram_config c = sram_config(word_size=2, num_words=32, num_banks=1) c.words_per_row=2 c.recompute_sizes() debug.info(1, "Functional test for {}rw,{}r,{}w psram with" "{} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, OPTS.num_r_ports, OPTS.num_w_ports, c.word_size, c.num_words, c.words_per_row, c.num_banks)) s = factory.create(module_type="sram", sram_config=c) tempspice = OPTS.openram_temp + "sram.sp" s.sp_write(tempspice) corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) f = functional(s.s, tempspice, corner) (fail, error) = f.run() self.assertTrue(fail,error) globals.end_openram()
def runTest(self): globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload import characterizer reload(characterizer) from characterizer import functional, delay if not OPTS.spice_exe: debug.error("Could not find {} simulator.".format(OPTS.spice_name), -1) from sram_config import sram_config c = sram_config(word_size=4, num_words=256, num_banks=1) c.words_per_row = 8 c.recompute_sizes() debug.info( 1, "Functional test for sram with {} bit words, {} words, {} words per row, {} banks" .format(c.word_size, c.num_words, c.words_per_row, c.num_banks)) s = factory.create(module_type="sram", sram_config=c) tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) f = functional(s.s, tempspice, corner) d = delay(s.s, tempspice, corner) feasible_period = self.find_feasible_test_period( d, s.s, f.load, f.slew) f.num_cycles = 10 (fail, error) = f.run() self.assertTrue(fail, error) globals.end_openram()
def save(self): """ Save all the output files while reporting time to do it as well. """ # Save the spice file start_time = datetime.datetime.now() spname = OPTS.output_path + self.s.name + ".sp" debug.print_raw("SP: Writing to {0}".format(spname)) self.sp_write(spname) functional(self.s, os.path.basename(spname), cycles=200, output_path=OPTS.output_path) print_time("Spice writing", datetime.datetime.now(), start_time) if not OPTS.netlist_only: # Write the layout start_time = datetime.datetime.now() gdsname = OPTS.output_path + self.s.name + ".gds" debug.print_raw("GDS: Writing to {0}".format(gdsname)) self.gds_write(gdsname) if OPTS.check_lvsdrc: verify.write_drc_script(cell_name=self.s.name, gds_name=os.path.basename(gdsname), extract=True, final_verification=True, output_path=OPTS.output_path) print_time("GDS", datetime.datetime.now(), start_time) # Create a LEF physical model start_time = datetime.datetime.now() lefname = OPTS.output_path + self.s.name + ".lef" debug.print_raw("LEF: Writing to {0}".format(lefname)) self.lef_write(lefname) print_time("LEF", datetime.datetime.now(), start_time) # Save the LVS file start_time = datetime.datetime.now() lvsname = OPTS.output_path + self.s.name + ".lvs.sp" debug.print_raw("LVS: Writing to {0}".format(lvsname)) self.lvs_write(lvsname) if not OPTS.netlist_only and OPTS.check_lvsdrc: verify.write_lvs_script(cell_name=self.s.name, gds_name=os.path.basename(gdsname), sp_name=os.path.basename(lvsname), final_verification=True, output_path=OPTS.output_path) print_time("LVS writing", datetime.datetime.now(), start_time) # Save the extracted spice file if OPTS.use_pex: start_time = datetime.datetime.now() # Output the extracted design if requested pexname = OPTS.output_path + self.s.name + ".pex.sp" spname = OPTS.output_path + self.s.name + ".sp" verify.run_pex(self.s.name, gdsname, spname, output=pexname) sp_file = pexname print_time("Extraction", datetime.datetime.now(), start_time) else: # Use generated spice file for characterization sp_file = spname # Save a functional simulation file # Characterize the design start_time = datetime.datetime.now() from characterizer import lib debug.print_raw("LIB: Characterizing... ") lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file) print_time("Characterization", datetime.datetime.now(), start_time) # Write the config file start_time = datetime.datetime.now() from shutil import copyfile copyfile(OPTS.config_file, OPTS.output_path + OPTS.output_name + '.py') debug.print_raw( "Config: Writing to {0}".format(OPTS.output_path + OPTS.output_name + '.py')) print_time("Config", datetime.datetime.now(), start_time) # Write the datasheet start_time = datetime.datetime.now() from datasheet_gen import datasheet_gen dname = OPTS.output_path + self.s.name + ".html" debug.print_raw("Datasheet: Writing to {0}".format(dname)) datasheet_gen.datasheet_write(dname) print_time("Datasheet", datetime.datetime.now(), start_time) # Write a verilog model start_time = datetime.datetime.now() vname = OPTS.output_path + self.s.name + ".v" debug.print_raw("Verilog: Writing to {0}".format(vname)) self.verilog_write(vname) print_time("Verilog", datetime.datetime.now(), start_time) # Write out options if specified if OPTS.output_extended_config: start_time = datetime.datetime.now() oname = OPTS.output_path + OPTS.output_name + "_extended.py" debug.print_raw("Extended Config: Writing to {0}".format(oname)) self.extended_config_write(oname) print_time("Extended Config", datetime.datetime.now(), start_time)