def gen_hdl_wrseldec(root, module, isigs, area, pfx, wrseldec):
proc = HDLComb()
proc.name = '{}WrSelDec'.format(pfx)
bus_addr = root.h_bus['adri']
proc.sensitivity.append(bus_addr)
for r in wrseldec:
for i in reversed(range(r.c_nwords)):
proc.stmts.append(HDLAssign(r.h_wrsel[i], bit_0))
sw = HDLSwitch(
HDLSlice(bus_addr, root.c_addr_word_bits,
ilog2(area.c_size) - root.c_addr_word_bits))
if isinstance(area, (tree.Block, tree.Submap)):
stmt = gen_hdl_area_decode(root, module, area, bus_addr)
stmt.then_stmts.append(sw)
stmt.else_stmts.append(HDLAssign(isigs.Loc_CRegWrOK, bit_0))
proc.stmts.append(stmt)
else:
proc.stmts.append(sw)
for reg in wrseldec:
if reg.h_has_mux:
proc.sensitivity.append(reg.h_regok)
regok = reg.h_regok
else:
regok = bit_1
for i in reversed(range(reg.c_nwords)):
ch = HDLChoiceExpr(reg.h_gena_regaddr[i])
ch.stmts.append(HDLAssign(reg.h_wrsel[i], bit_1))
ch.stmts.append(HDLAssign(isigs.Loc_CRegWrOK, regok))
sw.choices.append(ch)
ch = HDLChoiceDefault()
ch.stmts.append(HDLAssign(isigs.Loc_CRegWrOK, bit_0))
sw.choices.append(ch)
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def gen_hdl_areardmux(root, module, isigs, area, areas):
proc = HDLComb()
proc.name = 'AreaRdMux'
bus_addr = root.h_bus['adro']
proc.sensitivity.extend([bus_addr, isigs.MemRdData, isigs.MemRdDone])
first = []
last = first
for a in areas:
proc.sensitivity.extend([a.h_isigs.RdData, a.h_isigs.RdDone])
stmt = gen_hdl_area_decode(root, module, a, bus_addr)
stmt.then_stmts.append(HDLAssign(isigs.RdData, a.h_isigs.RdData))
stmt.then_stmts.append(HDLAssign(isigs.RdDone, a.h_isigs.RdDone))
if root.c_buserr:
proc.sensitivity.append(a.h_isigs.RdError)
stmt.then_stmts.append(HDLAssign(isigs.RdError, a.h_isigs.RdError))
if a.h_has_external:
proc.stmts.append(HDLAssign(a.h_rdsel_sig, bit_0))
stmt.then_stmts.append(HDLAssign(a.h_rdsel_sig, bit_1))
last.append(stmt)
last = stmt.else_stmts
gen_hdl_mem2top_rd(root, module, isigs, last)
proc.stmts.extend(first)
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def wire_bus_slave_sram(root, stmts, n):
stmts.append(HDLAssign(n.h_data_o, root.h_bus['dato']))
stmts.append(
HDLAssign(
n.h_addr_o,
HDLSlice(root.h_bus['adr'], root.c_addr_word_bits,
n.c_blk_bits - root.c_addr_word_bits)))
def gen_hdl_no_regrdmux(root, module, isigs):
module.stmts.append(HDLAssign(isigs.Loc_RegRdData, isigs.CRegRdData))
module.stmts.append(HDLAssign(isigs.Loc_RegRdOK, isigs.CRegRdOK))
module.stmts.append(HDLComment(None))
gen_hdl_locregrd2regrd(module.stmts, isigs)
module.stmts.append(HDLComment(None))
def add_read(s, n, off):
if n is not None:
if isinstance(n, tree.Reg):
s.append(HDLComment(n.name))
s.append(HDLAssign(rd_data, root.h_reg_rdat_int))
s.append(HDLAssign(rd_ack, root.h_rd_ack1_int))
elif isinstance(n, tree.Submap):
s.append(HDLComment("Submap {}".format(n.name)))
if n.c_interface == 'wb-32-be':
s.append(HDLAssign(rd_data, n.h_bus['dato']))
rdproc.stmts.append(HDLAssign(n.h_rd, bit_0))
s.append(HDLAssign(n.h_rd, isigs.rd_int))
s.append(HDLAssign(isigs.rd_ack, n.h_bus['ack']))
return
elif n.c_interface == 'sram':
return
else:
raise AssertionError
elif isinstance(n, tree.Array):
s.append(HDLComment("RAM {}".format(n.name)))
# TODO: handle list of registers!
r = n.children[0]
rdproc.sensitivity.append(r.h_sig_dato)
# Output ram data
s.append(HDLAssign(rd_data, r.h_sig_dato))
# Set rd signal to ram
s.append(HDLAssign(r.h_sig_rd, isigs.rd_int))
# But set it to 0 when the ram is not selected.
rdproc.stmts.append(HDLAssign(r.h_sig_rd, bit_0))
# Use delayed ack as ack.
s.append(HDLAssign(rd_ack, root.h_rd_ack1_int))
return
else:
# Blocks have been handled.
raise AssertionError
def gen_hdl_misc_root(root, module, isigs):
module.stmts.append(HDLAssign(root.h_bus['dato'], isigs.RdData))
module.stmts.append(HDLAssign(root.h_bus['rack'], isigs.RdDone))
module.stmts.append(HDLAssign(root.h_bus['wack'], isigs.WrDone))
if root.c_buserr:
module.stmts.append(HDLAssign(root.h_bus['rderr'], isigs.RdError))
module.stmts.append(HDLAssign(root.h_bus['wrerr'], isigs.WrError))
module.stmts.append(HDLComment(None))
def gen_hdl_no_cregrdmux_dff(root, module, isigs):
module.stmts.append(
HDLAssign(isigs.Loc_CRegRdData, HDLReplicate(bit_0, None)))
module.stmts.append(HDLAssign(isigs.Loc_CRegRdOK, bit_0))
module.stmts.append(HDLAssign(isigs.Loc_CRegWrOK, bit_0))
module.stmts.append(HDLComment(None))
gen_hdl_cregrdmux_asgn(module.stmts, isigs)
module.stmts.append(HDLComment(None))
def gen_hdl_no_area(root, module, isigs):
module.stmts.append(HDLAssign(isigs.RdData, isigs.MemRdData))
module.stmts.append(HDLAssign(isigs.RdDone, isigs.MemRdDone))
module.stmts.append(HDLAssign(isigs.WrDone, isigs.MemWrDone))
if root.c_buserr:
module.stmts.append(HDLAssign(isigs.RdError, isigs.MemRdError))
module.stmts.append(HDLAssign(isigs.WrError, isigs.MemWrError))
module.stmts.append(HDLComment(None))
def add_read_process(root, module, isigs):
# Register read
rd_data = root.h_bus['dato']
rd_ack = isigs.rd_ack
rd_adr = root.h_bus.get('adr', None)
rdproc = HDLComb()
if rd_adr is not None:
rdproc.sensitivity.append(rd_adr)
if root.h_max_delay >= 1:
rdproc.sensitivity.extend(
[root.h_reg_rdat_int, root.h_rd_ack1_int, isigs.rd_int])
module.stmts.append(rdproc)
# All the read are ack'ed (including the read to unassigned addresses).
rdproc.stmts.append(HDLComment("By default ack read requests"))
rdproc.stmts.append(
HDLAssign(rd_data, HDLReplicate(bit_0, root.c_word_bits)))
rdproc.stmts.append(HDLAssign(rd_ack, bit_1))
def add_read(s, n, off):
if n is not None:
if isinstance(n, tree.Reg):
s.append(HDLComment(n.name))
s.append(HDLAssign(rd_data, root.h_reg_rdat_int))
s.append(HDLAssign(rd_ack, root.h_rd_ack1_int))
elif isinstance(n, tree.Submap):
s.append(HDLComment("Submap {}".format(n.name)))
if n.c_interface == 'wb-32-be':
s.append(HDLAssign(rd_data, n.h_bus['dato']))
rdproc.stmts.append(HDLAssign(n.h_rd, bit_0))
s.append(HDLAssign(n.h_rd, isigs.rd_int))
s.append(HDLAssign(isigs.rd_ack, n.h_bus['ack']))
return
elif n.c_interface == 'sram':
return
else:
raise AssertionError
elif isinstance(n, tree.Array):
s.append(HDLComment("RAM {}".format(n.name)))
# TODO: handle list of registers!
r = n.children[0]
rdproc.sensitivity.append(r.h_sig_dato)
# Output ram data
s.append(HDLAssign(rd_data, r.h_sig_dato))
# Set rd signal to ram
s.append(HDLAssign(r.h_sig_rd, isigs.rd_int))
# But set it to 0 when the ram is not selected.
rdproc.stmts.append(HDLAssign(r.h_sig_rd, bit_0))
# Use delayed ack as ack.
s.append(HDLAssign(rd_ack, root.h_rd_ack1_int))
return
else:
# Blocks have been handled.
raise AssertionError
stmts = []
add_decoder(root, stmts, rd_adr, root, add_read)
rdproc.stmts.extend(stmts)
def add_decode_cern_be_vme(root, module, isigs):
"Generate internal signals used by decoder/processes from CERN-BE-VME bus."
isigs.rd_int = root.h_bus['rd']
isigs.wr_int = root.h_bus['wr']
isigs.rd_ack = HDLSignal('rd_ack_int') # Ack for read
isigs.wr_ack = HDLSignal('wr_ack_int') # Ack for write
module.decls.extend([isigs.rd_ack, isigs.wr_ack])
module.stmts.append(HDLAssign(root.h_bus['rack'], isigs.rd_ack))
module.stmts.append(HDLAssign(root.h_bus['wack'], isigs.wr_ack))
def gen_hdl_ext_bus_asgn(n, acc, root, module):
adr_sz = ilog2(n.c_size) - root.c_addr_word_bits
adr_lo = root.c_addr_word_bits
if not root.h_bussplit:
module.stmts.append(
HDLAssign(n.h_addr, HDLSlice(root.h_bus['adr'], adr_lo, adr_sz)))
module.stmts.append(HDLAssign(n.h_sel, n.h_sel_sig))
if acc in READ_ACCESS:
if root.h_bussplit:
module.stmts.append(
HDLAssign(n.h_rdaddr,
HDLSlice(root.h_bus['adro'], adr_lo, adr_sz)))
module.stmts.append(HDLAssign(n.h_rdsel, n.h_rdsel_sig))
module.stmts.append(
HDLAssign(n.h_rdmem, HDLAnd(n.h_rdsel_sig, root.h_bus['rd'])))
if acc in WRITE_ACCESS:
if root.h_bussplit:
module.stmts.append(
HDLAssign(n.h_wraddr,
HDLSlice(root.h_bus['adri'], adr_lo, adr_sz)))
module.stmts.append(HDLAssign(n.h_wrsel, n.h_wrsel_sig))
module.stmts.append(
HDLAssign(n.h_wrmem, HDLAnd(n.h_wrsel_sig, root.h_bus['wr'])))
module.stmts.append(HDLAssign(n.h_wrdata, root.h_bus['dati']))
module.stmts.append(HDLComment(None))
def wire_array_reg(root, module, reg):
if root.h_ram is None:
module.deps.append(('work', 'wbgen2_pkg'))
root.h_ram = True
root.h_ram_wr_dly = HDLSignal("wr_dly_int")
module.decls.append(root.h_ram_wr_dly)
inst = HDLInstance(reg.name + "_raminst", "wbgen2_dpssram")
module.stmts.append(inst)
inst.params.append(("g_data_width", HDLNumber(reg.c_rwidth)))
inst.params.append(("g_size", HDLNumber(1 << reg.h_addr_width)))
inst.params.append(("g_addr_width", HDLNumber(reg.h_addr_width)))
inst.params.append(("g_dual_clock", HDLBool(False)))
inst.params.append(("g_use_bwsel", HDLBool(False)))
inst.conns.append(("clk_a_i", root.h_bus['clk']))
inst.conns.append(("clk_b_i", root.h_bus['clk']))
inst.conns.append(
("addr_a_i", HDLSlice(root.h_bus['adr'], 0, reg.h_addr_width)))
inst.conns.append(("addr_b_i", reg.h_addr))
nbr_bytes = reg.c_rwidth // tree.BYTE_SIZE
reg.h_sig_bwsel = HDLSignal(reg.name + '_int_bwsel', nbr_bytes)
module.decls.append(reg.h_sig_bwsel)
inst.conns.append(("bwsel_b_i", reg.h_sig_bwsel))
inst.conns.append(("bwsel_a_i", reg.h_sig_bwsel))
if reg.access == 'ro':
raise AssertionError # TODO
inst.conns.append(("data_a_o", reg.h_dat))
inst.conns.append(("rd_a_i", rd_sig))
else:
# External port is RO.
reg.h_sig_dato = HDLSignal(reg.name + '_int_dato', reg.c_rwidth)
module.decls.append(reg.h_sig_dato)
reg.h_dat_ign = HDLSignal(reg.name + '_ext_dat', reg.c_rwidth)
module.decls.append(reg.h_dat_ign)
reg.h_sig_rd = HDLSignal(reg.name + '_int_rd')
module.decls.append(reg.h_sig_rd)
reg.h_sig_wr = HDLSignal(reg.name + '_int_wr')
module.decls.append(reg.h_sig_wr)
reg.h_ext_wr = HDLSignal(reg.name + '_ext_wr')
module.decls.append(reg.h_ext_wr)
module.stmts.append(HDLAssign(reg.h_ext_wr, bit_0))
inst.conns.append(("data_a_i", root.h_bus['dati']))
inst.conns.append(("data_a_o", reg.h_sig_dato))
inst.conns.append(("rd_a_i", reg.h_sig_rd))
inst.conns.append(("wr_a_i", reg.h_sig_wr))
inst.conns.append(("data_b_i", reg.h_dat_ign))
inst.conns.append(("data_b_o", reg.h_dat))
inst.conns.append(("rd_b_i", reg.h_rd))
inst.conns.append(("wr_b_i", reg.h_ext_wr))
module.stmts.append(
HDLAssign(reg.h_sig_bwsel, HDLReplicate(bit_1, nbr_bytes)))
def gen_hdl_strobeseq(root, module, isigs):
proc = HDLSync(root.h_bus['clk'], None)
proc.name = 'StrobeSeq'
proc.sync_stmts.append(
HDLAssign(
isigs.Loc_VMERdMem,
HDLConcat(HDLSlice(isigs.Loc_VMERdMem, 0, 2), root.h_bus['rd'])))
proc.sync_stmts.append(
HDLAssign(
isigs.Loc_VMEWrMem,
HDLConcat(HDLSlice(isigs.Loc_VMEWrMem, 0, None),
root.h_bus['wr'])))
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def gen_hdl_memwrmux(root, module, isigs, area, pfx, mems):
proc = HDLComb()
proc.name = pfx + 'MemWrMux'
bus_addr = root.h_bus['adri']
proc.sensitivity.extend([bus_addr, isigs.RegWrDone])
if root.c_buserr:
proc.sensitivity.append(isigs.RegWrError)
adr_sz = ilog2(area.c_size) - root.c_addr_word_bits
adr_lo = root.c_addr_word_bits
first = []
last = first
for m in mems:
data = m.children[0]
set_wrsel = data.access == 'wo' or (data.access == 'rw'
and root.c_bussplit)
if set_wrsel:
proc.stmts.append(HDLAssign(m.h_wrsel_sig, bit_0))
cond = HDLAnd(HDLGe(HDLSlice(bus_addr, adr_lo, adr_sz), m.h_gena_sta),
HDLLe(HDLSlice(bus_addr, adr_lo, adr_sz), m.h_gena_end))
stmt = HDLIfElse(cond)
if set_wrsel:
stmt.then_stmts.append(HDLAssign(m.h_wrsel_sig, bit_1))
if data.access in WRITE_ACCESS:
proc.sensitivity.append(m.h_wrdone)
done = m.h_wrdone
else:
done = bit_0
stmt.then_stmts.append(HDLAssign(isigs.Loc_MemWrDone, done))
if root.c_buserr:
if data.access in WRITE_ACCESS:
proc.sensitivity.append(m.h_wrerror)
err = m.h_wrerror
else:
err = root.h_bus['wr']
stmt.then_stmts.append(HDLAssign(isigs.Loc_MemWrError, err))
last.append(stmt)
last = stmt.else_stmts
gen_hdl_reg2locmem_wr(root, module, isigs, last)
if isinstance(area, (tree.Block, tree.Submap)):
stmt = gen_hdl_area_decode(root, module, area, bus_addr)
stmt.then_stmts.extend(first)
gen_hdl_reg2locmem_wr(root, module, isigs, stmt.else_stmts)
proc.stmts.append(stmt)
else:
proc.stmts.extend(first)
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def add_read_reg_process(root, module, isigs):
# Register read
rd_data = root.h_reg_rdat_int
rd_ack = root.h_rd_ack1_int
rdproc = HDLSync(root.h_bus['clk'], root.h_bus['rst'])
module.stmts.append(rdproc)
rdproc.rst_stmts.append(HDLAssign(rd_ack, bit_0))
rdproc.rst_stmts.append(
HDLAssign(rd_data, HDLReplicate(bit_x, root.c_word_bits)))
rdproc.sync_stmts.append(
HDLAssign(rd_data, HDLReplicate(bit_x, root.c_word_bits)))
rd_if = HDLIfElse(HDLAnd(HDLEq(isigs.rd_int, bit_1), HDLEq(rd_ack, bit_0)))
rdproc.sync_stmts.append(rd_if)
rd_if.then_stmts.append(HDLAssign(rd_ack, bit_1))
rd_if.else_stmts.append(HDLAssign(rd_ack, bit_0))
def add_read_reg(s, n, off):
for f in n.children:
if n.access in ['wo', 'rw']:
src = f.h_reg
elif n.access == 'ro':
src = f.h_iport
elif n.access == 'cst':
src = HDLConst(f.preset, f.c_rwidth)
else:
raise AssertionError
reg, dat = field_decode(root, n, f, off, src, rd_data)
if reg is None:
continue
s.append(HDLAssign(dat, reg))
def add_read(s, n, off):
if n is not None:
if isinstance(n, tree.Reg):
s.append(HDLComment(n.name))
if n.access != 'wo':
add_read_reg(s, n, off)
elif isinstance(n, tree.Submap):
pass
elif isinstance(n, tree.Array):
s.append(HDLComment("RAM {}".format(n.name)))
else:
# Blocks have been handled.
raise AssertionError
then_stmts = []
add_decoder(root, then_stmts, root.h_bus.get('adr', None), root, add_read)
rd_if.then_stmts.extend(then_stmts)
def gen_hdl_regrdmux(root, module, isigs, area, pfx, rd_reg):
proc = HDLComb()
proc.name = '{}RegRdMux'.format(pfx)
bus_addr = root.h_bus['adro']
proc.sensitivity.append(bus_addr)
proc.sensitivity.append(isigs.CRegRdData)
proc.sensitivity.append(isigs.CRegRdOK)
for reg in rd_reg:
if reg.h_rdsel:
for i in reversed(range(reg.c_nwords)):
proc.stmts.append(HDLAssign(reg.h_rdsel[i], bit_0))
sw = HDLSwitch(
HDLSlice(bus_addr, root.c_addr_word_bits,
ilog2(area.c_size) - root.c_addr_word_bits))
if isinstance(area, (tree.Block, tree.Submap)):
stmt = gen_hdl_area_decode(root, module, area, bus_addr)
stmt.then_stmts.append(sw)
stmt.else_stmts.append(HDLAssign(isigs.Loc_RegRdData,
isigs.CRegRdData))
stmt.else_stmts.append(HDLAssign(isigs.Loc_RegRdOK, isigs.CRegRdOK))
proc.stmts.append(stmt)
else:
proc.stmts.append(sw)
regok_sensitivity = []
for reg in rd_reg:
loc = reg.h_loc_SRFF or reg.h_loc
proc.sensitivity.append(loc)
if reg.h_has_mux:
regok_sensitivity.append(reg.h_regok)
regok = reg.h_regok
else:
regok = bit_1
for i in reversed(range(reg.c_nwords)):
ch = HDLChoiceExpr(reg.h_gena_regaddr[i])
val = loc
vwidth = reg.c_rwidth // reg.c_nwords
val = HDLSlice(val, i * root.c_word_bits, vwidth)
if vwidth < root.c_word_bits:
val = HDLZext(val, vwidth)
ch.stmts.append(HDLAssign(isigs.Loc_RegRdData, val))
ch.stmts.append(HDLAssign(isigs.Loc_RegRdOK, regok))
if reg.h_rdsel:
ch.stmts.append(HDLAssign(reg.h_rdsel[i], bit_1))
sw.choices.append(ch)
ch = HDLChoiceDefault()
ch.stmts.append(HDLAssign(isigs.Loc_RegRdData, isigs.CRegRdData))
ch.stmts.append(HDLAssign(isigs.Loc_RegRdOK, isigs.CRegRdOK))
proc.sensitivity.extend(regok_sensitivity)
sw.choices.append(ch)
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def gen_hdl_areawrmux(root, module, isigs, area, areas):
proc = HDLComb()
proc.name = 'AreaWrMux'
bus_addr = root.h_bus['adri']
proc.sensitivity.extend([bus_addr, isigs.MemWrDone])
first = []
last = first
for a in areas:
proc.sensitivity.append(a.h_isigs.WrDone)
stmt = gen_hdl_area_decode(root, module, a, bus_addr)
stmt.then_stmts.append(HDLAssign(isigs.WrDone, a.h_isigs.WrDone))
if root.c_buserr:
proc.sensitivity.append(a.h_isigs.WrError)
stmt.then_stmts.append(HDLAssign(isigs.WrError, a.h_isigs.WrError))
last.append(stmt)
last = stmt.else_stmts
gen_hdl_mem2top_wr(root, module, isigs, last)
proc.stmts.extend(first)
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def add_decode_wb(root, module, isigs):
"Generate internal signals used by decoder/processes from WB bus."
isigs.rd_int = HDLSignal('rd_int') # Read access
isigs.wr_int = HDLSignal('wr_int') # Write access
isigs.rd_ack = HDLSignal('rd_ack_int') # Ack for read
isigs.wr_ack = HDLSignal('wr_ack_int') # Ack for write
# Internal signals for wb.
isigs.wb_en = HDLSignal('wb_en')
isigs.ack_int = HDLSignal('ack_int') # Ack
module.decls.extend([
isigs.wb_en, isigs.rd_int, isigs.wr_int, isigs.ack_int, isigs.rd_ack,
isigs.wr_ack
])
module.stmts.append(
HDLAssign(isigs.wb_en, HDLAnd(root.h_bus['cyc'], root.h_bus['stb'])))
module.stmts.append(
HDLAssign(isigs.rd_int, HDLAnd(isigs.wb_en, HDLNot(root.h_bus['we']))))
module.stmts.append(
HDLAssign(isigs.wr_int, HDLAnd(isigs.wb_en, root.h_bus['we'])))
module.stmts.append(
HDLAssign(isigs.ack_int, HDLOr(isigs.rd_ack, isigs.wr_ack)))
module.stmts.append(HDLAssign(root.h_bus['ack'], isigs.ack_int))
module.stmts.append(
HDLAssign(root.h_bus['stall'],
HDLAnd(HDLNot(isigs.ack_int), isigs.wb_en)))
def gen_hdl_memrdmux(root, module, isigs, area, pfx, mems):
proc = HDLComb()
proc.name = pfx + 'MemRdMux'
bus_addr = root.h_bus['adro']
proc.sensitivity.extend([bus_addr, isigs.RegRdData, isigs.RegRdDone])
if root.c_buserr:
proc.sensitivity.append(isigs.RegRdError)
adr_sz = ilog2(area.c_size) - root.c_addr_word_bits
adr_lo = root.c_addr_word_bits
first = []
last = first
for m in mems:
data = m.children[0]
if data.access in READ_ACCESS:
proc.sensitivity.extend([m.h_rddata, m.h_rddone])
if root.c_buserr:
proc.sensitivity.append(m.h_rderror)
proc.stmts.append(HDLAssign(m.h_rdsel_sig, bit_0))
cond = HDLAnd(HDLGe(HDLSlice(bus_addr, adr_lo, adr_sz), m.h_gena_sta),
HDLLe(HDLSlice(bus_addr, adr_lo, adr_sz), m.h_gena_end))
stmt = HDLIfElse(cond)
if data.access in READ_ACCESS:
stmt.then_stmts.append(HDLAssign(m.h_rdsel_sig, bit_1))
stmt.then_stmts.append(HDLAssign(isigs.Loc_MemRdData, m.h_rddata))
stmt.then_stmts.append(HDLAssign(isigs.Loc_MemRdDone, m.h_rddone))
if root.c_buserr:
stmt.then_stmts.append(
HDLAssign(isigs.Loc_MemRdError, m.h_rderror))
else:
stmt.then_stmts.append(
HDLAssign(isigs.Loc_MemRdData, HDLReplicate(bit_0,
data.width)))
stmt.then_stmts.append(HDLAssign(isigs.Loc_MemRdDone, bit_0))
if root.c_buserr:
stmt.then_stmts.append(
HDLAssign(isigs.Loc_MemRdError, root.h_bus['rd']))
last.append(stmt)
last = stmt.else_stmts
gen_hdl_reg2locmem_rd(root, module, isigs, last)
if isinstance(area, (tree.Block, tree.Submap)):
stmt = gen_hdl_area_decode(root, module, area, bus_addr)
stmt.then_stmts.extend(first)
gen_hdl_reg2locmem_rd(root, module, isigs, stmt.else_stmts)
proc.stmts.append(stmt)
else:
proc.stmts.extend(first)
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def add_write_reg(s, n, off):
for f in n.children:
# Reset code
if f.h_reg is not None:
v = 0 if f.preset is None else f.preset
cst = HDLConst(v, f.c_iowidth if f.c_iowidth != 1 else None)
wrproc.rst_stmts.append(HDLAssign(f.h_reg, cst))
# Assign code
if f.hdl_type == 'reg':
r = f.h_reg
elif f.hdl_type == 'wire':
r = f.h_oport
else:
raise AssertionError
reg, dat = field_decode(root, n, f, off, r, wr_data)
if reg is None:
continue
s.append(HDLAssign(reg, dat))
if f.h_wport is not None:
s.append(HDLAssign(f.h_wport, bit_1))
wrproc.rst_stmts.append(HDLAssign(f.h_wport, bit_0))
wrproc.sync_stmts.append(HDLAssign(f.h_wport, bit_0))
def gen_hdl_regdone(root, module, isigs, root_isigs, rd_delay, wr_delay):
asgn = HDLAssign(
isigs.RegRdDone,
HDLAnd(HDLIndex(root_isigs.Loc_VMERdMem, rd_delay), isigs.RegRdOK))
module.stmts.append(asgn)
asgn = HDLAssign(
isigs.RegWrDone,
HDLAnd(HDLIndex(root_isigs.Loc_VMEWrMem, wr_delay), isigs.CRegWrOK))
module.stmts.append(asgn)
module.stmts.append(HDLComment(None))
if root.c_buserr:
asgn = HDLAssign(
isigs.RegRdError,
HDLAnd(HDLIndex(root_isigs.Loc_VMERdMem, rd_delay),
HDLNot(isigs.RegRdOK)))
module.stmts.append(asgn)
asgn = HDLAssign(
isigs.RegWrError,
HDLAnd(HDLIndex(root_isigs.Loc_VMEWrMem, wr_delay),
HDLNot(isigs.CRegWrOK)))
module.stmts.append(asgn)
module.stmts.append(HDLComment(None))
def wire_bus_slave_wb32(root, stmts, n):
stmts.append(HDLComment("Assignments for submap {}".format(n.name)))
stmts.append(HDLAssign(n.h_bus['cyc'], HDLOr(n.h_wr, n.h_rd)))
stmts.append(HDLAssign(n.h_bus['stb'], HDLOr(n.h_wr, n.h_rd)))
stmts.append(HDLAssign(n.h_bus['adr'], root.h_bus['adr']))
stmts.append(HDLAssign(n.h_bus['sel'], HDLReplicate(bit_1, 4)))
stmts.append(HDLAssign(n.h_bus['we'], n.h_wr))
stmts.append(HDLAssign(n.h_bus['dati'], root.h_bus['dati']))
def gen_hdl_reg_rdmux(reg, pfx, root, module, isigs):
proc = HDLComb()
proc.name = 'Reg_{}{}_RdMux'.format(pfx, reg.name)
sel_field = reg.h_mux.sel
proc.sensitivity.append(sel_field._parent.h_loc)
sel_val, sel_width = gen_hdl_field(sel_field._parent.h_loc, sel_field)
sw = HDLSwitch(sel_val)
proc.stmts.append(sw)
m = 0
for suff, val in reg.h_mux.codelist:
ch = HDLChoiceExpr(HDLBinConst(val, sel_width))
ch.stmts.append(HDLAssign(reg.h_loc, reg.h_loc_mux[m]))
proc.sensitivity.append(reg.h_loc_mux[m])
ch.stmts.append(HDLAssign(reg.h_regok, bit_1))
sw.choices.append(ch)
m += 1
ch = HDLChoiceDefault()
ch.stmts.append(
HDLAssign(reg.h_loc, HDLReplicate(bit_0, sel_field.c_rwidth)))
ch.stmts.append(HDLAssign(reg.h_regok, bit_0))
sw.choices.append(ch)
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def add_read_reg(s, n, off):
for f in n.children:
if n.access in ['wo', 'rw']:
src = f.h_reg
elif n.access == 'ro':
src = f.h_iport
elif n.access == 'cst':
src = HDLConst(f.preset, f.c_rwidth)
else:
raise AssertionError
reg, dat = field_decode(root, n, f, off, src, rd_data)
if reg is None:
continue
s.append(HDLAssign(dat, reg))
def gen_hdl_reg_wrseldec(reg, pfx, root, module, isigs):
proc = HDLComb()
proc.name = 'Reg_{}{}_WrSelDec'.format(pfx, reg.name)
sel_field = reg.h_mux.sel
proc.sensitivity.append(sel_field._parent.h_loc)
sel_val, sel_width = gen_hdl_field(sel_field._parent.h_loc, sel_field)
sw = HDLSwitch(sel_val)
for i in reversed(range(reg.c_nwords)):
proc.sensitivity.append(reg.h_wrsel[i])
for i in reversed(range(reg.c_nwords)):
for m in range(len(reg.h_mux.codelist)):
proc.stmts.append(HDLAssign(reg.h_wrsel_mux[i][m], bit_0))
m = 0
for _, val in reg.h_mux.codelist:
ch = HDLChoiceExpr(HDLBinConst(val, sel_width))
for i in reversed(range(reg.c_nwords)):
ch.stmts.append(HDLAssign(reg.h_wrsel_mux[i][m], reg.h_wrsel[i]))
m += 1
sw.choices.append(ch)
ch = HDLChoiceDefault()
sw.choices.append(ch)
proc.stmts.append(sw)
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def gen_hdl_cregrdmux(root, module, isigs, area, pfx, wrseldec):
proc = HDLComb()
proc.name = '{}CRegRdMux'.format(pfx)
bus_addr = root.h_bus['adro']
proc.sensitivity.append(bus_addr)
sw = HDLSwitch(
HDLSlice(bus_addr, root.c_addr_word_bits,
ilog2(area.c_size) - root.c_addr_word_bits))
if isinstance(area, (tree.Block, tree.Submap)):
stmt = gen_hdl_area_decode(root, module, area, bus_addr)
stmt.then_stmts.append(sw)
stmt.else_stmts.append(
HDLAssign(isigs.Loc_CRegRdData, HDLReplicate(bit_0, None)))
stmt.else_stmts.append(HDLAssign(isigs.Loc_CRegRdOK, bit_0))
proc.stmts.append(stmt)
else:
proc.stmts.append(sw)
regok_sensitivity = []
for reg in wrseldec:
if reg.h_loc:
# NOTE: not needed for WO registers!
proc.sensitivity.append(reg.h_loc)
for i in reversed(range(reg.c_nwords)):
ch = HDLChoiceExpr(reg.h_gena_regaddr[i])
if reg.access == 'wo':
val = HDLReplicate(bit_0, None)
ok = bit_0
else:
val = reg.h_loc
regw = reg.c_rwidth // reg.c_nwords
val = HDLSlice(val, i * regw, regw)
if regw < root.c_word_bits:
val = HDLZext(val, root.c_word_bits)
if reg.h_has_mux:
if i == 0:
regok_sensitivity.append(reg.h_regok)
ok = reg.h_regok
else:
ok = bit_1
ch.stmts.append(HDLAssign(isigs.Loc_CRegRdData, val))
ch.stmts.append(HDLAssign(isigs.Loc_CRegRdOK, ok))
sw.choices.append(ch)
ch = HDLChoiceDefault()
ch.stmts.append(HDLAssign(isigs.Loc_CRegRdData, HDLReplicate(bit_0, None)))
ch.stmts.append(HDLAssign(isigs.Loc_CRegRdOK, bit_0))
proc.sensitivity.extend(regok_sensitivity)
sw.choices.append(ch)
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def wire_regs(root, module, isigs, node):
"""Create assignment from register to outputs."""
stmts = module.stmts
for n in node.children:
if isinstance(n, tree.Block):
wire_regs(root, module, isigs, n)
elif isinstance(n, tree.Submap):
if n.interface == 'include':
wire_regs(root, module, isigs, n.c_submap)
else:
wire_submap(root, module, n, stmts)
elif isinstance(n, tree.Array):
for c in n.children:
if isinstance(c, tree.Reg):
# Ram
wire_array_reg(root, module, c)
else:
raise AssertionError(c)
elif isinstance(n, tree.Reg):
for f in n.children:
if f.h_reg is not None and f.h_oport is not None:
stmts.append(HDLAssign(f.h_oport, f.h_reg))
else:
raise AssertionError
def add_write(s, n, off):
if n is not None:
if isinstance(n, tree.Reg):
s.append(HDLComment(n.name))
if n.access in ['wo', 'rw']:
add_write_reg(s, n, off)
elif isinstance(n, tree.Submap):
s.append(HDLComment("Submap {}".format(n.name)))
if n.c_interface == 'wb-32-be':
wrproc.rst_stmts.append(HDLAssign(n.h_wr, bit_0))
wr_if.then_stmts.append(HDLAssign(n.h_wr, bit_0))
s.append(HDLAssign(n.h_wr, bit_1))
s.append(HDLAssign(isigs.wr_ack, n.h_bus['ack']))
return
elif n.c_interface == 'sram':
s.append(HDLAssign(n.h_wr_o, bit_1))
return
else:
raise AssertionError
elif isinstance(n, tree.Array):
# TODO: handle list of registers!
r = n.children[0]
wrproc.rst_stmts.append(HDLAssign(r.h_sig_wr, bit_0))
wr_if.else_stmts.append(HDLAssign(r.h_sig_wr, bit_0))
s2 = HDLIfElse(HDLEq(root.h_ram_wr_dly, bit_0))
s.append(s2)
s2.then_stmts.append(HDLAssign(r.h_sig_wr, bit_1))
s2.then_stmts.append(HDLAssign(root.h_ram_wr_dly, bit_1))
s2.else_stmts.append(HDLAssign(root.h_ram_wr_dly, bit_0))
s2.else_stmts.append(HDLAssign(isigs.wr_ack, bit_1))
return
else:
# Including blocks.
raise AssertionError
# All the write are ack'ed (including the write to unassigned
# addresses)
s.append(HDLAssign(isigs.wr_ack, bit_1))
def add_write_process(root, module, isigs):
# Register write
wrproc = HDLSync(root.h_bus['clk'], root.h_bus['rst'])
module.stmts.append(wrproc)
if root.h_ram_wr_dly is not None:
wrproc.rst_stmts.append(HDLAssign(root.h_ram_wr_dly, bit_0))
wr_if = HDLIfElse(
HDLAnd(HDLEq(isigs.wr_int, bit_1), HDLEq(isigs.wr_ack, bit_0)))
wr_if.else_stmts.append(HDLAssign(isigs.wr_ack, bit_0))
wr_data = root.h_bus['dati']
def add_write_reg(s, n, off):
for f in n.children:
# Reset code
if f.h_reg is not None:
v = 0 if f.preset is None else f.preset
cst = HDLConst(v, f.c_iowidth if f.c_iowidth != 1 else None)
wrproc.rst_stmts.append(HDLAssign(f.h_reg, cst))
# Assign code
if f.hdl_type == 'reg':
r = f.h_reg
elif f.hdl_type == 'wire':
r = f.h_oport
else:
raise AssertionError
reg, dat = field_decode(root, n, f, off, r, wr_data)
if reg is None:
continue
s.append(HDLAssign(reg, dat))
if f.h_wport is not None:
s.append(HDLAssign(f.h_wport, bit_1))
wrproc.rst_stmts.append(HDLAssign(f.h_wport, bit_0))
wrproc.sync_stmts.append(HDLAssign(f.h_wport, bit_0))
def add_write(s, n, off):
if n is not None:
if isinstance(n, tree.Reg):
s.append(HDLComment(n.name))
if n.access in ['wo', 'rw']:
add_write_reg(s, n, off)
elif isinstance(n, tree.Submap):
s.append(HDLComment("Submap {}".format(n.name)))
if n.c_interface == 'wb-32-be':
wrproc.rst_stmts.append(HDLAssign(n.h_wr, bit_0))
wr_if.then_stmts.append(HDLAssign(n.h_wr, bit_0))
s.append(HDLAssign(n.h_wr, bit_1))
s.append(HDLAssign(isigs.wr_ack, n.h_bus['ack']))
return
elif n.c_interface == 'sram':
s.append(HDLAssign(n.h_wr_o, bit_1))
return
else:
raise AssertionError
elif isinstance(n, tree.Array):
# TODO: handle list of registers!
r = n.children[0]
wrproc.rst_stmts.append(HDLAssign(r.h_sig_wr, bit_0))
wr_if.else_stmts.append(HDLAssign(r.h_sig_wr, bit_0))
s2 = HDLIfElse(HDLEq(root.h_ram_wr_dly, bit_0))
s.append(s2)
s2.then_stmts.append(HDLAssign(r.h_sig_wr, bit_1))
s2.then_stmts.append(HDLAssign(root.h_ram_wr_dly, bit_1))
s2.else_stmts.append(HDLAssign(root.h_ram_wr_dly, bit_0))
s2.else_stmts.append(HDLAssign(isigs.wr_ack, bit_1))
return
else:
# Including blocks.
raise AssertionError
# All the write are ack'ed (including the write to unassigned
# addresses)
s.append(HDLAssign(isigs.wr_ack, bit_1))
then_stmts = []
add_decoder(root, then_stmts, root.h_bus.get('adr', None), root, add_write)
wr_if.then_stmts.extend(then_stmts)
wrproc.sync_stmts.append(wr_if)
def gen_hdl_mem2top_wr(root, module, isigs, stmts):
stmts.append(HDLAssign(isigs.WrDone, isigs.MemWrDone))
if root.c_buserr:
stmts.append(HDLAssign(isigs.WrError, isigs.MemWrError))