def get_cw_type(sn=None):
""" Gets the scope type of the connected ChipWhisperer
If multiple connected, sn must be specified
"""
from chipwhisperer.hardware.naeusb.naeusb import NAEUSB
from chipwhisperer.capture import scopes
possible_ids = [0xace0, 0xace2, 0xace3]
cwusb = NAEUSB()
possible_sn = cwusb.get_possible_devices(idProduct=possible_ids)
name = ""
if len(possible_sn) == 0:
raise OSError("USB Device not found. Did you connect it first?")
if (len(possible_sn) > 1):
if sn is None:
serial_numbers = []
for d in possible_sn:
serial_numbers.append("sn = {} ({})".format(str(d['sn']), str(d['product'])))
raise Warning("Multiple chipwhisperers connected, but device and/or serial number not specified.\nDevices:\n{}".format(serial_numbers))
else:
for d in possible_sn:
if d['sn'] == sn:
name = d['product']
else:
name = possible_sn[0]['product']
#print(name)
if (name == "ChipWhisperer Lite") or (name == "ChipWhisperer CW1200"):
return scopes.OpenADC
elif name == "ChipWhisperer Nano":
return scopes.CWNano
def __init__(self):
self._cwusb = NAEUSB()
# Connect required modules up here
self.fpga = FPGA(self._cwusb)
self.xmega = XMEGAPDI(self._cwusb)
self.avr = AVRISP(self._cwusb)
self.usart = USART(self._cwusb)
self.getParams().addChildren([{
'name':
"CW-Lite XMEGA Programmer",
'tip':
"Open XMEGA Programmer (ChipWhisperer-Lite Only)",
'type':
"menu",
"action":
lambda _: self.getCwliteXMEGA().show()
}, {
'name':
"CW-Lite AVR Programmer",
'tip':
"Open AVR Programmer (ChipWhisperer-Lite Only)",
'type':
"menu",
"action":
lambda _: self.getCwliteAVR().show()
}])
def __init__(self):
ScopeTemplate.__init__(self)
self._is_connected = False
self.params.init()
self._cwusb = NAEUSB()
self.ser = self._cwusb
self.scopetype = self
self.dev = self
self.xmega = XMEGAPDI(self._cwusb)
self.avr = AVRISP(self._cwusb)
self.usart = USART(self._cwusb)
self.serialstm32f = STM32FSerial(cwserial=self.usart)
self.serialstm32f.scope = self
self.io = GPIOSettings(self._cwusb)
self.adc = ADCSettings(self._cwusb)
self.glitch = GlitchSettings(self._cwusb)
self._timeout = 2
self._lasttrace = None
self.getParams().addChildren([
{'name':"CW-Lite XMEGA Programmer", 'tip':"Open XMEGA Programmer (ChipWhisperer-Lite Only)", 'type':"menu", "action":lambda _:self.getCwliteXMEGA().show()},
{'name':"CW-Lite AVR Programmer", 'tip':"Open AVR Programmer (ChipWhisperer-Lite Only)", 'type':"menu", "action":lambda _:self.getCwliteAVR().show()},
{'name':'Serial STM32F Programmer', 'tip':"Open STM32F Programmer (Serial/ChipWhisperer)", 'type':"menu", "action":lambda _:self.getSerialSTM32F().show()}
])
self.disable_newattr()
def __init__(self):
self._cwusb = NAEUSB()
# Connect required modules up here
self.fpga = FPGA(self._cwusb)
self.xmega = XMEGAPDI(self._cwusb)
self.avr = AVRISP(self._cwusb)
self.usart = USART(self._cwusb)
self.serialstm32f = STM32FSerial(cwserial=self.usart, cwapi=None)
def __init__(self,
target,
scope,
defines_files=None,
bs='',
force_bitfile=False):
"""
Args:
target: SimpleSerial target
scope: CW scope
naeusb: NewAE USB interface
platform (string): CW305 or CW610 (PhyWhisperer)
defines_files (list of 2 strings): path to defines_trace.v and defines_pw.v
"""
super().__init__()
self._trace_port_width = 4
self._base_target_clock = 7.384e6
self._base_baud = 38400
self._usb_clock = 96e6
self._uart_clock = self._usb_clock * 2
self.expected_verilog_defines = 107
self.swo_mode = False
self.board_rev = 4
self._scope = scope
# Detect whether we exist on CW305 or CW610 based on the target we're given:
if target._name == 'Simple Serial':
self.platform = 'CW610'
self._ss = target
self._naeusb = NAEUSB()
self._naeusb.con(idProduct=[0xC610])
# we're using the CW NAEUSB, which has no knowledge of PW firmware, so let's manually
# check the FW version here:
fw_latest = [1, 1]
if self._naeusb.readFwVersion()[0] < fw_latest[0]:
logging.warning(
'Your PhyWhisperer firmware is outdated - latest is %d.%d'
% (fw_latest[0], fw_latest[1]) +
'. Suggested to update firmware, as you may experience errors.'
)
self._fpga = FPGA(self._naeusb)
if not self._fpga.isFPGAProgrammed() or force_bitfile:
if not bs:
bs = pkg_resources.resource_filename(
'chipwhisperer',
'hardware/firmware/tracewhisperer_top.bit')
self._fpga.FPGAProgram(open(bs, 'rb'),
exceptOnDoneFailure=False)
else:
self.platform = 'CW305'
self._ss = cw.target(scope)
self._naeusb = target._naeusb
self.slurp_defines(defines_files)
self._set_defaults()
def __init__(self):
TargetTemplate.__init__(self)
self._naeusb = NAEUSB()
self.pll = PLLCDCE906(self._naeusb, ref_freq=12.0E6)
self.fpga = FPGA(self._naeusb)
self.hw = None
self.oa = None
self._woffset = 0x400
self._woffset_sam3U = 0x000
self._clksleeptime = 1
self._clkusbautooff = True
self.last_key = bytearray([0] * 16)
def __init__(self):
TargetTemplate.__init__(self)
self._naeusb = NAEUSB()
self.pll = PLLCDCE906(self._naeusb, ref_freq = 12.0E6, parent=self)
self.fpga = FPGA(self._naeusb)
self.hw = None
# self._fpgabs = QSettings().value("cw305-bitstream", '')
self.oa = None
self._woffset = 0x400
self.params.addChildren([
{'name':'PLL Settings', 'key':'pll', 'type':'group', 'children':[
{'name':'Enabled', 'key':'pllenabled', 'type':'bool', 'default':False, 'set':self.pll.pll_enable_set, 'get':self.pll.pll_enable_get, 'psync':False},
{'name':'CLK-SMA (X6)', 'key':'pll0', 'type':'group', 'children':[
{'name':'CLK-SMA Enabled', 'key':'pll0enabled', 'type':'bool', 'default':False, 'set':partial(self.pll.pll_outenable_set, outnum=0), 'get':partial(self.pll.pll_outenable_get, outnum=0), 'psync':False},
{'name':'CLK-SMA Source', 'key':'pll0source', 'type':'list', 'values':['PLL0', 'PLL1', 'PLL2'], 'default':'PLL0', 'set':partial(self.pll.pll_outsource_set, outnum=0), 'get':partial(self.pll.pll_outsource_get, outnum=0), 'psync':False},
{'name':'CLK-SMA Slew Rate', 'key':'pll0slew', 'type':'list', 'values':['+3nS', '+2nS', '+1nS', '+0nS'], 'default':'+0nS', 'set':partial(self.pll.pll_outslew_set, outnum=0), 'get':partial(self.pll.pll_outslew_get, outnum=0), 'psync':False},
{'name':'PLL0 Frequency', 'key':'pll0freq', 'type':'float', 'limits':(0.625E6, 167E6), 'default':0, 'step':1E6,
'siPrefix':True, 'suffix':'Hz', 'set':partial(self.pll.pll_outfreq_set, outnum=0), 'get':partial(self.pll.pll_outfreq_get, outnum=0), 'psync':False},
]},
{'name':'CLK-N13 (FGPA Pin N13)', 'key':'pll1', 'type':'group', 'children':[
{'name':'CLK-N13 Enabled', 'key':'pll1enabled', 'type':'bool', 'default':False, 'set':partial(self.pll.pll_outenable_set, outnum=1), 'get':partial(self.pll.pll_outenable_get, outnum=1), 'psync':False},
{'name':'CLK-N13 Source', 'key':'pll1source', 'type':'list', 'values':['PLL1'], 'value':'PLL1'},
{'name':'CLK-N13 Slew Rate', 'key':'pll1slew', 'type':'list', 'values':['+3nS', '+2nS', '+1nS', '+0nS'], 'default':'+0nS', 'set':partial(self.pll.pll_outslew_set, outnum=1), 'get':partial(self.pll.pll_outslew_get, outnum=1), 'psync':False},
{'name':'PLL1 Frequency', 'key':'pll1freq', 'type':'float', 'limits':(0.625E6, 167E6), 'default':0, 'step':1E6,
'siPrefix':True, 'suffix':'Hz', 'set':partial(self.pll.pll_outfreq_set, outnum=1), 'get':partial(self.pll.pll_outfreq_get, outnum=1), 'psync':False},
]},
{'name':'CLK-E12 (FGPA Pin E12)', 'key':'pll2', 'type':'group', 'children':[
{'name':'CLK-E12 Enabled', 'key':'pll2enabled', 'type':'bool', 'default':False, 'set':partial(self.pll.pll_outenable_set, outnum=2), 'get':partial(self.pll.pll_outenable_get, outnum=2), 'psync':False},
{'name':'CLK-E12 Source', 'key':'pll2source', 'type':'list', 'values':['PLL2'], 'value':'PLL2'},
{'name':'CLK-E12 Slew Rate', 'key':'pll2slew', 'type':'list', 'values':['+0nS', '+1nS', '+2nS', '+3nS'], 'default':'+0nS', 'set':partial(self.pll.pll_outslew_set, outnum=2), 'get':partial(self.pll.pll_outslew_get, outnum=2), 'psync':False},
{'name':'PLL2 Frequency', 'key':'pll2freq', 'type':'float', 'limits':(0.625E6, 167E6), 'default':0, 'step':1E6,
'siPrefix':True, 'suffix':'Hz', 'set':partial(self.pll.pll_outfreq_set, outnum=2), 'get':partial(self.pll.pll_outfreq_get, outnum=2), 'psync':False},
]},
{'name':'Save as Default (stored in EEPROM)', 'type':'action', 'action':lambda _ : self.pll.pll_writedefaults()},
]},
{'name':'Disable CLKUSB For Capture', 'key':'clkusbautooff', 'type':'bool', 'value':True},
{'name':'Time CLKUSB Disabled for', 'key':'clksleeptime', 'type':'int', 'range':(1, 50000), 'value':50, 'suffix':'mS'},
{'name':'CLKUSB Manual Setting', 'key':'clkusboff', 'type':'bool', 'value':True, 'action':self.usb_clk_setenabled_action},
{'name':'Send Trigger', 'type':'action', 'action':self.usb_trigger_toggle},
{'name':'VCC-INT', 'key':'vccint', 'type':'float', 'default':1.00, 'range':(0.6, 1.10), 'suffix':' V', 'decimals':3, 'set':self.vccint_set, 'get':self.vccint_get, 'step':0.01},
{'name':'FPGA Bitstream', 'type':'group', 'children':[
{'name':'Bitstream File', 'key':'fpgabsfile', 'type':'file', 'value':"", "filter":'*.bit'},
{'name':'Program FPGA', 'type':'action', 'action':self.gui_programfpga},
]},
])
def __init__(self):
TargetTemplate.__init__(self)
self._naeusb = NAEUSB()
self.pll = PLLCDCE906(self._naeusb, ref_freq=12.0E6)
self.fpga = FPGA(self._naeusb)
self.hw = None
self.oa = None
self._woffset_sam3U = 0x000
self.default_verilog_defines = 'cw305_defines.v'
self.default_verilog_defines_full_path = '../../hardware/victims/cw305_artixtarget/fpga/common/' + self.default_verilog_defines
self.registers = 12 # number of registers we expect to find
self.bytecount_size = 7 # pBYTECNT_SIZE in Verilog
self._clksleeptime = 1
self._clkusbautooff = True
self.last_key = bytearray([0] * 16)
self.target_name = 'AES'
def __init__(self):
ScopeTemplate.__init__(self)
self._is_connected = False
self._cwusb = NAEUSB()
self.ser = self._cwusb
self.scopetype = self
self.dev = self
self.xmega = XMEGAPDI(self._cwusb)
self.avr = AVRISP(self._cwusb)
self.usart = USART(self._cwusb)
self.serialstm32f = STM32FSerial(cwserial=self.usart)
self.serialstm32f.scope = self
self.io = GPIOSettings(self._cwusb)
self.adc = ADCSettings(self._cwusb)
self.glitch = GlitchSettings(self._cwusb)
self._timeout = 2
self._lasttrace = None
self.disable_newattr()
def __init__(self):
self._cwusb = NAEUSB()
# Connect required modules up here
self.fpga = FPGA(self._cwusb)
self.xmega = XMEGAPDI(self._cwusb)
self.avr = AVRISP(self._cwusb)
self.usart = USART(self._cwusb)
self.serialstm32f = STM32FSerial(cwserial=self.usart,
cwapi=CWCoreAPI.getInstance())
self.getParams().addChildren([{
'name':
"CW-Lite XMEGA Programmer",
'tip':
"Open XMEGA Programmer (ChipWhisperer-Lite Only)",
'type':
"menu",
"action":
lambda _: self.getCwliteXMEGA().show()
}, {
'name':
"CW-Lite AVR Programmer",
'tip':
"Open AVR Programmer (ChipWhisperer-Lite Only)",
'type':
"menu",
"action":
lambda _: self.getCwliteAVR().show()
}, {
'name':
'Serial STM32F Programmer',
'tip':
"Open STM32F Programmer (Serial/ChipWhisperer)",
'type':
"menu",
"action":
lambda _: self.getSerialSTM32F().show()
}])
def __init__(self, *args, **kwargs):
# maybe later can hijack cw305 stuff, but for now don't
pass
import chipwhisperer as cw
self._naeusb = NAEUSB()
self.pll = PLLCDCE906(self._naeusb, ref_freq=12.0E6)
self.fpga = FPGA(self._naeusb)
self.hw = None
self.oa = None
self._woffset_sam3U = 0x000
self.default_verilog_defines = 'cw305_defines.v'
self.default_verilog_defines_full_path = os.path.dirname(
cw.__file__
) + '/../../hardware/victims/cw305_artixtarget/fpga/common/' + self.default_verilog_defines
self.registers = 12 # number of registers we expect to find
self.bytecount_size = 7 # pBYTECNT_SIZE in Verilog
self._clksleeptime = 1
self._clkusbautooff = True
self.last_key = bytearray([0] * 16)
self.target_name = 'AES'
