def __init__(self, dut, num_samples, input_width):
clk = Clock(dut.clk_i, 40)
clk_3x = Clock(dut.clk_3x_i, 120)
self.multiclock = MultiClock([clk, clk_3x])
self.dut = dut
self.re_inputs = random_samples(input_width, num_samples)
self.im_inputs = random_samples(input_width, num_samples)
self.outputs = np.fft.fft(self.re_inputs + 1j * self.im_inputs)
def __init__(
self,
dut,
num_samples,
input_width,
twiddle_width,
discretize_twiddles: bool = False,
use_max: bool = False,
):
clk = Clock(dut.clk, 40)
self.clk = clk
self.dut = dut
self.twiddle_width = twiddle_width
self.discretize_twiddles = discretize_twiddles
self.length = num_samples
if use_max:
self.re_inputs = np.array(
[2**(input_width - 1) - 1 for _ in range(num_samples)])
self.im_inputs = np.array(
[2**(input_width - 1) - 1 for _ in range(num_samples)])
else:
self.re_inputs = random_samples(6, num_samples)
# self.im_inputs = random_samples(input_width, num_samples)
self.im_inputs = np.array([0 for _ in range(num_samples)])
self.gen_outputs()
async def fpga_write_sequence(dut):
"""
Write a series of values from the FPGA to the FT245 and ensure the
correct data is written to the FT2232H data bus.
"""
ft245 = FT245_TB(dut)
await ft245.setup()
num_writes = 1000
input_width = 64
wrdata = random_samples(input_width, num_writes)
cocotb.fork(ft245.fpga_write_continuous(wrdata))
ft245.dut.txe_n <= 0
ft245.dut.rxf_n <= 1
ft245.dut.suspend_n <= 1
i = 0
while i < num_writes:
await ReadOnly()
# print(wrdata[i])
# print(ft245.dut.ft_data)
await RisingEdge(ft245.dut.ft_clk)
i += 1
def __init__(self, dut, num_samples, input_width):
self.clk = Clock(dut.clk, 40)
self.clk_en = ClockEnable(dut.clk, dut.clk_en, dut.rst_n, 20)
self.dut = dut
self.inputs = random_samples(input_width, num_samples)
self.coeffs = np.kaiser(num_samples, 6)
self.outputs = np.multiply(self.inputs, self.coeffs)
async def rand_samples(dut):
top = TopTB(dut)
await top.setup()
num_writes = 100000
input_width = 7
wrdata = random_samples(input_width, num_writes)
cocotb.fork(top.gen_samples(wrdata))
# top.dut.ft_rxf_n_i <= 0
# top.dut.ft_data_io <= 1
# await RisingEdge(top.dut.ft_clkout_i)
# top.dut.ft_data_io <= 1
# await RisingEdge(top.dut.ft_clkout_i)
# top.dut.ft_rxf_n_i <= 1
# await RisingEdge(top.dut.ft_clkout_i)
await top.pc_request_mode("raw")
# top.dut.ft_txe_n_i <= 0
await top.pc_request_data()
i = 0
while i < num_writes:
# await ReadOnly()
# print(wrdata[i])
# print(top.dut.ft_data_io)
await RisingEdge(top.dut.ft_clkout_i)
i += 1
def __init__(self, dut, num_samples, input_width, tap_width):
self.clk = Clock(dut.clk, 40)
self.clk_en = ClockEnable(dut.clk, dut.clk_2mhz_pos_en, dut.rst_n, 20)
self.dut = dut
self.inputs = random_samples(input_width, num_samples)
self.downsample_factor = 20
self.fir = FIR(
numtaps=120,
bands=[0, 1e6, 1.5e6, 20e6],
band_gain=[1, 0],
fs=40e6,
pass_db=0.5,
stop_db=-40,
)
self.norm_shift = self.fir.tap_normalization_shift()
self.taps = self.fir.taps
self.outputs = self.gen_outputs()