Exemplo n.º 1
0
    def expect_setup(self, epaddr, expected_data):
        actual_data = []
        # wait for data to appear
        for i in range(128):
            self.dut._log.debug("Prime loop {}".format(i))
            status = yield self.read(self.csrs['usb_setup_status'])
            have = status & 0x10
            if have:
                break
            yield RisingEdge(self.dut.clk12)

        for i in range(48):
            self.dut._log.debug("Read loop {}".format(i))
            status = yield self.read(self.csrs['usb_setup_status'])
            have = status & 0x10
            if not have:
                break
            v = yield self.read(self.csrs['usb_setup_data'])
            actual_data.append(v)
            yield RisingEdge(self.dut.clk12)

        if len(actual_data) < 2:
            raise TestFailure("data was short (got {}, expected {})".format(
                expected_data, actual_data))
        actual_data, actual_crc16 = actual_data[:-2], actual_data[-2:]

        self.print_ep(epaddr, "Got: %r (expected: %r)", actual_data,
                      expected_data)
        assertEqual(expected_data, actual_data, "SETUP packet not received")
        assertEqual(crc16(expected_data), actual_crc16, "CRC16 not valid")
        # Acknowledge that we've handled the setup packet
        yield self.write(self.csrs['usb_setup_ctrl'], 2)
Exemplo n.º 2
0
    def expect_data(self, epaddr, expected_data, expected):
        actual_data = []
        # wait for data to appear
        for i in range(128):
            self.dut._log.debug("Prime loop {}".format(i))
            status = yield self.read(self.csrs['usb_out_status'])
            have = status & (1 << 4)
            if have:
                break
            yield RisingEdge(self.dut.clk12)

        for i in range(256):
            self.dut._log.debug("Read loop {}".format(i))
            status = yield self.read(self.csrs['usb_out_status'])
            have = status & (1 << 4)
            if not have:
                break
            v = yield self.read(self.csrs['usb_out_data'])
            actual_data.append(v)
            yield RisingEdge(self.dut.clk12)

        if expected == PID.ACK:
            if len(actual_data) < 2:
                raise TestFailure("data {} was short".format(actual_data))
            actual_data, actual_crc16 = actual_data[:-2], actual_data[-2:]

            self.print_ep(epaddr, "Got: %r (expected: %r)", actual_data,
                          expected_data)
            assertEqual(expected_data, actual_data,
                        "DATA packet not correctly received")
            assertEqual(crc16(expected_data), actual_crc16, "CRC16 not valid")
            pending = yield self.read(self.csrs['usb_out_ev_pending'])
            if pending != 1:
                raise TestFailure('event not generated')
            yield self.write(self.csrs['usb_out_ev_pending'], pending)