def getOptionList():
return [
DTSLv1.tabSet("options", "Options", childOptions=
[DTSLv1.tabPage("rams", "Cache RAMs", childOptions=[
# Turn cache debug mode on/off
DTSLv1.booleanOption('cacheDebug', 'Cache debug mode',
description='Turning cache debug mode on enables reading the cache RAMs. Enabling it may adversely impact debug performance.',
defaultValue=False, isDynamic=True),
DTSLv1.booleanOption('cachePreserve', 'Preserve cache contents in debug state',
description='Preserve the contents of caches while the core is stopped.',
defaultValue=False, isDynamic=True),
])]
)
]
def getOptionList():
return [
DTSLv1.tabSet("options", "Options", childOptions=[
DTSLv1.tabPage("trace", "Trace Capture", childOptions=[
DTSLv1.enumOption('traceCapture', 'Trace capture method', defaultValue="none",
values = [("none", "None"), ("DSTREAM", "DSTREAM 4GB Trace Buffer")],
setter=DtslScript.setTraceCaptureMethod),
]),
DTSLv1.tabPage("cortexM3", "Cortex-M3", childOptions=[
DTSLv1.booleanOption('coreTrace', 'Enable Cortex-M3 core trace', defaultValue=False,
childOptions =
# Allow each source to be enabled/disabled individually
[ DTSLv1.booleanOption('Cortex_M3_%d' % c, "Enable Cortex-M3 %d trace" % c, defaultValue=True)
for c in range(0, NUM_CORES_CORTEX_M3) ]
),
]),
DTSLv1.tabPage("itm", "ITM", childOptions=[
DTSLv1.booleanOption('ITM0', 'Enable ITM 0 trace', defaultValue=False),
]),
])
]
def getOptionList():
return [
DTSLv1.tabSet("options", "Options", childOptions=[
DTSLv1.tabPage("trace", "Trace Capture", childOptions=[
DTSLv1.enumOption('traceCapture', 'Trace capture method', defaultValue="none",
values = [("none", "None"), ("DSTREAM", "DSTREAM 4GB Trace Buffer")],
setter=DtslScript.setTraceCaptureMethod),
]),
DTSLv1.tabPage("cortexM3", "Cortex-M3", childOptions=[
DTSLv1.booleanOption('coreTrace', 'Enable Cortex-M3 core trace', defaultValue=False,
childOptions =
# Allow each source to be enabled/disabled individually
[ DTSLv1.booleanOption('Cortex_M3_%d' % c, "Enable Cortex-M3 %d trace" % c, defaultValue=True)
for c in range(0, NUM_CORES_CORTEX_M3) ]
),
]),
DTSLv1.tabPage("itm", "ITM", childOptions=[
DTSLv1.booleanOption('ITM0', 'Enable ITM 0 trace', defaultValue=False),
]),
])
]
def getOptionList():
return [
DTSLv1.tabSet(
"options",
"Options",
childOptions=[
DTSLv1.tabPage(
"trace",
"Trace Capture",
childOptions=[
DTSLv1.enumOption(
'traceCapture',
'Trace capture method',
defaultValue="none",
values=[
("none", "None"),
("ETF0",
"On Chip Trace Buffer (ETF0/TMC)"),
("ETR0",
"System Memory Trace Buffer (ETR0/TMC)")
],
setter=DtslScript.setTraceCaptureMethod),
]),
DTSLv1.tabPage(
"cortexA57",
"Cortex-A57",
childOptions=[
DTSLv1.booleanOption(
'coreTrace',
'Enable Cortex-A57 core trace',
defaultValue=False,
childOptions=
# Allow each source to be enabled/disabled individually
[
DTSLv1.booleanOption(
'Cortex_A57_%d' % c,
"Enable Cortex-A57 %d trace" % c,
defaultValue=True)
for c in range(0, NUM_CORES_CORTEX_A57)
] + [
ETMv4TraceSource.cycleAccurateOption(
DtslScript.getETMsForCortex_A57)
] +
[ # Trace range selection (e.g. for linux kernel)
DTSLv1.booleanOption(
'traceRange',
'Trace capture range',
description=TRACE_RANGE_DESCRIPTION,
defaultValue=False,
childOptions=[
DTSLv1.integerOption(
'start',
'Start address',
description=
'Start address for trace capture',
defaultValue=0,
display=IIntegerOption.
DisplayFormat.HEX),
DTSLv1.integerOption(
'end',
'End address',
description=
'End address for trace capture',
defaultValue=0xFFFFFFFF,
display=IIntegerOption.
DisplayFormat.HEX)
])
]),
]),
DTSLv1.tabPage(
"ETR",
"ETR",
childOptions=[
DTSLv1.booleanOption(
'etrBuffer0',
'Configure the system memory trace buffer to be used by the ETR0/TMC device',
defaultValue=False,
childOptions=[
DTSLv1.integerOption(
'start',
'Start address',
description=
'Start address of the system memory trace buffer to be used by the ETR0/TMC device',
defaultValue=0x00100000,
display=IIntegerOption.DisplayFormat.
HEX),
DTSLv1.integerOption(
'size',
'Size in Words',
description=
'Size of the system memory trace buffer in Words (total bytes/system memory width)',
defaultValue=0x8000,
isDynamic=True,
display=IIntegerOption.DisplayFormat.
HEX),
DTSLv1.booleanOption(
'scatterGather',
'Enable scatter-gather mode',
defaultValue=False,
description=
'When enabling scatter-gather mode, the start address of the on-chip trace buffer must point to a configured scatter-gather table'
)
]),
]),
DTSLv1.tabPage(
"stm",
"STM",
childOptions=[
DTSLv1.booleanOption('STM0',
'Enable STM 0 trace',
defaultValue=False),
DTSLv1.booleanOption('STM1',
'Enable STM 1 trace',
defaultValue=False),
]),
DTSLv1.tabPage(
"rams",
"Cache RAMs",
childOptions=[
# Turn cache debug mode on/off
DTSLv1.booleanOption(
'cacheDebug',
'Cache debug mode',
description=
'Turning cache debug mode on enables reading the cache RAMs. Enabling it may adversely impact debug performance.',
defaultValue=False,
isDynamic=True),
DTSLv1.booleanOption(
'cachePreserve',
'Preserve cache contents in debug state',
description=
'Preserve the contents of caches while the core is stopped.',
defaultValue=False,
isDynamic=True),
]),
])
]
def getOptionList():
return [
DTSLv1.tabSet("options", "Options", childOptions=[
])
]
def getOptionList():
return [
DTSLv1.tabSet(
"options",
"Options",
childOptions=[
DTSLv1.tabPage(
"trace",
"Trace Capture",
childOptions=[
DTSLv1.enumOption(
'traceCapture',
'Trace capture method',
defaultValue="none",
values=[
("none", "None"),
("ETF0",
"On Chip Trace Buffer (ETF0/TMC)"),
("ETF1",
"On Chip Trace Buffer (ETF1/TMC)"),
("ETF2",
"On Chip Trace Buffer (ETF2/TMC)"),
("ETF3",
"On Chip Trace Buffer (ETF3/TMC)"),
("ETR0",
"System Memory Trace Buffer (ETR0/TMC)")
],
setter=DtslScript.setTraceCaptureMethod),
DTSLv1.integerOption(
'timestampFrequency',
'Timestamp frequency',
defaultValue=25000000,
isDynamic=False,
description=
"This value will be used to set the Counter Base Frequency ID Register of the Timestamp generator.\nIt represents the number of ticks per second and is used to translate the timestamp value reported into a number of seconds.\nNote that changing this value may not result in a change in the observed frequency."
),
]),
DTSLv1.tabPage(
"cortexA53",
"Cortex-A53",
childOptions=[
DTSLv1.booleanOption(
'coreTrace',
'Enable Cortex-A53 core trace',
defaultValue=False,
childOptions=
# Allow each source to be enabled/disabled individually
[
DTSLv1.booleanOption(
'Cortex_A53_%d' % c,
"Enable Cortex-A53 %d trace" % c,
defaultValue=True)
for c in range(0, NUM_CORES_CORTEX_A53)
] + [
DTSLv1.booleanOption(
'timestamp',
"Enable ETM Timestamps",
description=
"Controls the output of timestamps into the ETM output streams",
defaultValue=True)
] + [
DTSLv1.booleanOption(
'contextIDs',
"Enable ETM Context IDs",
description=
"Controls the output of context ID values into the ETM output streams",
defaultValue=True,
childOptions=[
DTSLv1.enumOption(
'contextIDsSize',
'Context ID Size',
defaultValue="32",
values=[("8", "8 bit"),
("16", "16 bit"),
("32", "32 bit")])
]),
] + [
ETMv4TraceSource.cycleAccurateOption(
DtslScript.getETMsForCortex_A53)
]),
]),
DTSLv1.tabPage(
"ETR",
"ETR",
childOptions=[
DTSLv1.booleanOption(
'etrBuffer0',
'Configure the system memory trace buffer to be used by the ETR0/TMC device',
defaultValue=False,
childOptions=[
DTSLv1.integerOption(
'start',
'Start address',
description=
'Start address of the system memory trace buffer to be used by the ETR0/TMC device',
defaultValue=0x00100000,
display=IIntegerOption.DisplayFormat.
HEX),
DTSLv1.integerOption(
'size',
'Size in Words',
description=
'Size of the system memory trace buffer in Words (total bytes/system memory width)',
defaultValue=0x8000,
isDynamic=True,
display=IIntegerOption.DisplayFormat.
HEX),
DTSLv1.booleanOption(
'scatterGather',
'Enable scatter-gather mode',
defaultValue=False,
description=
'When enabling scatter-gather mode, the start address of the on-chip trace buffer must point to a configured scatter-gather table'
)
]),
]),
DTSLv1.tabPage(
"stm",
"STM",
childOptions=[
DTSLv1.booleanOption('STM0',
'Enable STM 0 trace',
defaultValue=False),
DTSLv1.booleanOption('STM1',
'Enable STM 1 trace',
defaultValue=False),
]),
DTSLv1.tabPage(
"rams",
"Cache RAMs",
childOptions=[
# Turn cache debug mode on/off
DTSLv1.booleanOption(
'cacheDebug',
'Cache debug mode',
description=
'Turning cache debug mode on enables reading the cache RAMs. Enabling it may adversely impact debug performance.',
defaultValue=False,
isDynamic=True),
DTSLv1.booleanOption(
'cachePreserve',
'Preserve cache contents in debug state',
description=
'Preserve the contents of caches while the core is stopped.',
defaultValue=False,
isDynamic=True),
]),
])
]
def getOptionList():
return [
DTSLv1.tabSet(
"options",
"Options",
childOptions=[
DTSLv1.tabPage(
"trace_%d" % c,
"Cluster %d Trace" % c,
childOptions=[
DTSLv1.enumOption(
'traceCapture',
'Trace capture method',
defaultValue="none",
values=[("none", "None"),
("ETB_%d" % c,
"On Chip Trace Buffer (ETB)")]),
DTSLv1.booleanOption(
'cortexA15coreTrace',
'Enable Cortex-A15 core trace',
defaultValue=False,
childOptions=
# Allow each source to be enabled/disabled individually
[
DTSLv1.booleanOption(
'Cortex_A15_%d' % core,
"Enable Cortex-A15 %d trace" % core,
defaultValue=True)
for core in range(CLUSTER_SIZES[c])
] +
# Pull in common options for PTMs (cycle accurate etc)
PTMTraceSource.defaultOptions(
DtslScript.getPTMs) +
[ # Trace range selection (e.g. for linux kernel)
DTSLv1.booleanOption(
'traceRange',
'Trace capture range',
description=TRACE_RANGE_DESCRIPTION,
defaultValue=False,
childOptions=[
DTSLv1.integerOption(
'start',
'Start address',
description=
'Start address for trace capture',
defaultValue=0,
display=IIntegerOption.
DisplayFormat.HEX),
DTSLv1.integerOption(
'end',
'End address',
description=
'End address for trace capture',
defaultValue=0xFFFFFFFF,
display=IIntegerOption.
DisplayFormat.HEX)
])
]),
]) for c in range(NUM_CLUSTERS)
] + [
DTSLv1.tabPage(
"trace_sys",
"System Trace",
childOptions=[
DTSLv1.booleanOption(
'sys', 'System STM trace', defaultValue=False),
DTSLv1.booleanOption('ccn',
'CCN-504 STM trace',
defaultValue=False),
])
])
]
def getOptionList():
return [
DTSLv1.tabSet("options", "Options", childOptions=[
])
]
