def create(args):
''' Create and configure the system object. '''
system = SimpleSeSystem(args)
# Tell components about the expected physical memory ranges. This
# is, for example, used by the MemConfig helper to determine where
# to map DRAMs in the physical address space.
system.mem_ranges = [ AddrRange(start=0, size=args.mem_size) ]
# Configure the off-chip memory system.
MemConfig.config_mem(args, system)
# Parse the command line and get a list of Processes instances
# that we can pass to gem5.
processes = get_processes(args.commands_to_run)
if len(processes) != args.num_cores:
print("Error: Cannot map %d command(s) onto %d CPU(s)" %
(len(processes), args.num_cores))
sys.exit(1)
# Assign one workload to each CPU
for cpu, workload in zip(system.cpu_cluster.cpus, processes):
cpu.workload = workload
return system
def build_system(options):
# create the system we are going to simulate
system = System()
# use timing mode for the interaction between master-slave ports
system.mem_mode = 'timing'
# set the clock fequency of the system
clk = '100GHz'
vd = VoltageDomain(voltage='1V')
system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd)
# add traffic generators to the system
system.tgen = [TrafficGen(config_file=options.tgen_cfg_file) for i in
range(options.num_tgen)]
# Config memory system with given HMC arch
MemConfig.config_mem(options, system)
# Connect the traffic generatiors
if options.arch == "distributed":
for i in range(options.num_tgen):
system.tgen[i].port = system.membus.slave
# connect the system port even if it is not used in this example
system.system_port = system.membus.slave
if options.arch == "mixed":
for i in range(int(options.num_tgen/2)):
system.tgen[i].port = system.membus.slave
hh = system.hmc_host
if options.enable_global_monitor:
system.tgen[2].port = hh.lmonitor[2].slave
hh.lmonitor[2].master = hh.seriallink[2].slave
system.tgen[3].port = hh.lmonitor[3].slave
hh.lmonitor[3].master = hh.seriallink[3].slave
else:
system.tgen[2].port = hh.seriallink[2].slave
system.tgen[3].port = hh.seriallink[3].slave
# connect the system port even if it is not used in this example
system.system_port = system.membus.slave
if options.arch == "same":
hh = system.hmc_host
for i in range(options.num_links_controllers):
if options.enable_global_monitor:
system.tgen[i].port = hh.lmonitor[i].slave
else:
system.tgen[i].port = hh.seriallink[i].slave
# set up the root SimObject
root = Root(full_system=False, system=system)
return root
# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock
# is actually used only by the caches connected to the CPU.
system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
voltage_domain =
system.cpu_voltage_domain)
# All cpus belong to a common cpu_clk_domain, therefore running at a common
# frequency.
for cpu in system.cpu:
cpu.clk_domain = system.cpu_clk_domain
# BaseCPU no longer has default values for the BaseCPU.isa
# createThreads() is needed to fill in the cpu.isa
for cpu in system.cpu:
cpu.createThreads()
# Assign input trace files to the Trace CPU
system.cpu.instTraceFile=options.inst_trace_file
system.cpu.dataTraceFile=options.data_trace_file
# Configure the classic memory system options
MemClass = Simulation.setMemClass(options)
system.membus = SystemXBar()
system.system_port = system.membus.slave
CacheConfig.config_cache(options, system)
MemConfig.config_mem(options, system)
root = Root(full_system = False, system = system)
Simulation.run(options, root, system, FutureClass)
def build_test_system(np):
cmdline = cmd_line_template()
if buildEnv['TARGET_ISA'] == "alpha":
test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby,
cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "mips":
test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "x86":
test_sys = makeLinuxX86System(test_mem_mode, np, bm[0], options.ruby,
cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "arm":
test_sys = makeArmSystem(test_mem_mode, options.machine_type, np,
bm[0], options.dtb_filename,
bare_metal=options.bare_metal,
cmdline=cmdline,
external_memory=
options.external_memory_system,
ruby=options.ruby,
security=options.enable_security_extensions)
if options.enable_context_switch_stats_dump:
test_sys.enable_context_switch_stats_dump = True
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
# Set the cache line size for the entire system
test_sys.cache_line_size = options.cacheline_size
# Create a top-level voltage domain
test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
# Create a source clock for the system and set the clock period
test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
voltage_domain = test_sys.voltage_domain)
# Create a CPU voltage domain
test_sys.cpu_voltage_domain = VoltageDomain()
# Create a source clock for the CPUs and set the clock period
test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
voltage_domain =
test_sys.cpu_voltage_domain)
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
else:
print("Error: a kernel must be provided to run in full system mode")
sys.exit(1)
if options.script is not None:
test_sys.readfile = options.script
if options.lpae:
test_sys.have_lpae = True
if options.virtualisation:
test_sys.have_virtualization = True
test_sys.init_param = options.init_param
# For now, assign all the CPUs to the same clock domain
test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
for i in range(np)]
if CpuConfig.is_kvm_cpu(TestCPUClass) or CpuConfig.is_kvm_cpu(FutureClass):
test_sys.kvm_vm = KvmVM()
if options.ruby:
bootmem = getattr(test_sys, 'bootmem', None)
Ruby.create_system(options, True, test_sys, test_sys.iobus,
test_sys._dma_ports, bootmem)
# Create a seperate clock domain for Ruby
test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = test_sys.voltage_domain)
# Connect the ruby io port to the PIO bus,
# assuming that there is just one such port.
test_sys.iobus.master = test_sys.ruby._io_port.slave
for (i, cpu) in enumerate(test_sys.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
cpu.clk_domain = test_sys.cpu_clk_domain
cpu.createThreads()
cpu.createInterruptController()
cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
if buildEnv['TARGET_ISA'] in ("x86", "arm"):
cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
if buildEnv['TARGET_ISA'] in "x86":
cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master
else:
if options.caches or options.l2cache:
# By default the IOCache runs at the system clock
test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
elif not options.external_memory_system:
test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
# Sanity check
if options.simpoint_profile:
if not CpuConfig.is_noncaching_cpu(TestCPUClass):
fatal("SimPoint generation should be done with atomic cpu")
if np > 1:
fatal("SimPoint generation not supported with more than one CPUs")
for i in range(np):
if options.simpoint_profile:
test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
if options.checker:
test_sys.cpu[i].addCheckerCpu()
if options.bp_type:
bpClass = BPConfig.get(options.bp_type)
test_sys.cpu[i].branchPred = bpClass()
if options.indirect_bp_type:
IndirectBPClass = \
BPConfig.get_indirect(options.indirect_bp_type)
test_sys.cpu[i].branchPred.indirectBranchPred = \
IndirectBPClass()
test_sys.cpu[i].createThreads()
# If elastic tracing is enabled when not restoring from checkpoint and
# when not fast forwarding using the atomic cpu, then check that the
# TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check
# passes then attach the elastic trace probe.
# If restoring from checkpoint or fast forwarding, the code that does this for
# FutureCPUClass is in the Simulation module. If the check passes then the
# elastic trace probe is attached to the switch CPUs.
if options.elastic_trace_en and options.checkpoint_restore == None and \
not options.fast_forward:
CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options)
CacheConfig.config_cache(options, test_sys)
MemConfig.config_mem(options, test_sys)
return test_sys
def create(args):
''' Create and configure the system object. '''
if not args.dtb:
dtb_file = SysPaths.binary("armv8_gem5_v1_%icpu.%s.dtb" %
(args.num_cores, default_dist_version))
else:
dtb_file = args.dtb
if args.script and not os.path.isfile(args.script):
print "Error: Bootscript %s does not exist" % args.script
sys.exit(1)
cpu_class = cpu_types[args.cpu][0]
mem_mode = cpu_class.memory_mode()
# Only simulate caches when using a timing CPU (e.g., the HPI model)
want_caches = True if mem_mode == "timing" else False
system = devices.SimpleSystem(want_caches,
args.mem_size,
mem_mode=mem_mode,
dtb_filename=dtb_file,
kernel=SysPaths.binary(args.kernel),
readfile=args.script,
machine_type="DTOnly")
MemConfig.config_mem(args, system)
# Add the PCI devices we need for this system. The base system
# doesn't have any PCI devices by default since they are assumed
# to be added by the configurastion scripts needin them.
system.pci_devices = [
# Create a VirtIO block device for the system's boot
# disk. Attach the disk image using gem5's Copy-on-Write
# functionality to avoid writing changes to the stored copy of
# the disk image.
PciVirtIO(vio=VirtIOBlock(image=create_cow_image(args.disk_image))),
]
# Attach the PCI devices to the system. The helper method in the
# system assigns a unique PCI bus ID to each of the devices and
# connects them to the IO bus.
for dev in system.pci_devices:
system.attach_pci(dev)
# Wire up the system's memory system
system.connect()
# Add CPU clusters to the system
system.cpu_cluster = [
devices.CpuCluster(system,
args.num_cores,
args.cpu_freq, "1.0V",
*cpu_types[args.cpu]),
]
# Create a cache hierarchy for the cluster. We are assuming that
# clusters have core-private L1 caches and an L2 that's shared
# within the cluster.
for cluster in system.cpu_cluster:
system.addCaches(want_caches, last_cache_level=2)
# Setup gem5's minimal Linux boot loader.
system.realview.setupBootLoader(system.membus, system, SysPaths.binary)
# Linux boot command flags
kernel_cmd = [
# Tell Linux to use the simulated serial port as a console
"console=ttyAMA0",
# Hard-code timi
"lpj=19988480",
# Disable address space randomisation to get a consistent
# memory layout.
"norandmaps",
# Tell Linux where to find the root disk image.
"root=/dev/vda1",
# Mount the root disk read-write by default.
"rw",
# Tell Linux about the amount of physical memory present.
"mem=%s" % args.mem_size,
]
system.boot_osflags = " ".join(kernel_cmd)
return system
def build_test_system(np):
cmdline = cmd_line_template()
if buildEnv['TARGET_ISA'] == "alpha":
test_sys = makeLinuxAlphaSystem(test_mem_mode,
bm[0],
options.ruby,
cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "mips":
test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "x86":
test_sys = makeLinuxX86System(test_mem_mode,
options.num_cpus,
bm[0],
options.ruby,
cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "arm":
test_sys = makeArmSystem(
test_mem_mode,
options.machine_type,
options.num_cpus,
bm[0],
options.dtb_filename,
bare_metal=options.bare_metal,
cmdline=cmdline,
external_memory=options.external_memory_system,
ruby=options.ruby)
if options.enable_context_switch_stats_dump:
test_sys.enable_context_switch_stats_dump = True
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
# Set the cache line size for the entire system
test_sys.cache_line_size = options.cacheline_size
# Create a top-level voltage domain
test_sys.voltage_domain = VoltageDomain(voltage=options.sys_voltage)
# Create a source clock for the system and set the clock period
test_sys.clk_domain = SrcClockDomain(
clock=options.sys_clock, voltage_domain=test_sys.voltage_domain)
# Create a CPU voltage domain
test_sys.cpu_voltage_domain = VoltageDomain()
# Create a source clock for the CPUs and set the clock period
test_sys.cpu_clk_domain = SrcClockDomain(
clock=options.cpu_clock, voltage_domain=test_sys.cpu_voltage_domain)
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
if options.script is not None:
test_sys.readfile = options.script
if options.lpae:
test_sys.have_lpae = True
if options.virtualisation:
test_sys.have_virtualization = True
test_sys.init_param = options.init_param
# For now, assign all the CPUs to the same clock domain
test_sys.cpu = [
TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
for i in xrange(np)
]
if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
test_sys.vm = KvmVM()
if options.ruby:
# Check for timing mode because ruby does not support atomic accesses
if not (options.cpu_type == "detailed"
or options.cpu_type == "timing"):
print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
sys.exit(1)
Ruby.create_system(options, True, test_sys, test_sys.iobus,
test_sys._dma_ports)
# Create a seperate clock domain for Ruby
test_sys.ruby.clk_domain = SrcClockDomain(
clock=options.ruby_clock, voltage_domain=test_sys.voltage_domain)
# Connect the ruby io port to the PIO bus,
# assuming that there is just one such port.
test_sys.iobus.master = test_sys.ruby._io_port.slave
for (i, cpu) in enumerate(test_sys.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
cpu.clk_domain = test_sys.cpu_clk_domain
cpu.createThreads()
cpu.createInterruptController()
cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
if buildEnv['TARGET_ISA'] in ("x86", "arm"):
cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
if buildEnv['TARGET_ISA'] in "x86":
cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[
i].slave
cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[
i].master
else:
if options.caches or options.l2cache:
# By default the IOCache runs at the system clock
test_sys.iocache = IOCache(addr_ranges=test_sys.mem_ranges)
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
elif not options.external_memory_system:
test_sys.iobridge = Bridge(delay='50ns',
ranges=test_sys.mem_ranges)
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
# Sanity check
if options.fastmem:
if TestCPUClass != AtomicSimpleCPU:
fatal("Fastmem can only be used with atomic CPU!")
if (options.caches or options.l2cache):
fatal("You cannot use fastmem in combination with caches!")
if options.simpoint_profile:
if not options.fastmem:
# Atomic CPU checked with fastmem option already
fatal(
"SimPoint generation should be done with atomic cpu and fastmem"
)
if np > 1:
fatal(
"SimPoint generation not supported with more than one CPUs"
)
for i in xrange(np):
if options.fastmem:
test_sys.cpu[i].fastmem = True
if options.simpoint_profile:
test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
if options.checker:
test_sys.cpu[i].addCheckerCpu()
test_sys.cpu[i].createThreads()
# If elastic tracing is enabled when not restoring from checkpoint and
# when not fast forwarding using the atomic cpu, then check that the
# TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check
# passes then attach the elastic trace probe.
# If restoring from checkpoint or fast forwarding, the code that does this for
# FutureCPUClass is in the Simulation module. If the check passes then the
# elastic trace probe is attached to the switch CPUs.
if options.elastic_trace_en and options.checkpoint_restore == None and \
not options.fast_forward:
CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options)
CacheConfig.config_cache(options, test_sys)
MemConfig.config_mem(options, test_sys)
return test_sys
assert(options.num_cpus == len(system.ruby._cpu_ports))
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = system.voltage_domain)
for i in xrange(np):
ruby_port = system.ruby._cpu_ports[i]
# Create the interrupt controller and connect its ports to Ruby
# Note that the interrupt controller is always present but only
# in x86 does it have message ports that need to be connected
system.cpu[i].createInterruptController()
# Connect the cpu's cache ports to Ruby
system.cpu[i].icache_port = ruby_port.slave
system.cpu[i].dcache_port = ruby_port.slave
if buildEnv['TARGET_ISA'] == 'x86':
system.cpu[i].interrupts[0].pio = ruby_port.master
system.cpu[i].interrupts[0].int_master = ruby_port.slave
system.cpu[i].interrupts[0].int_slave = ruby_port.master
system.cpu[i].itb.walker.port = ruby_port.slave
system.cpu[i].dtb.walker.port = ruby_port.slave
else:
MemClass = Simulation.setMemClass(options)
system.membus = SystemXBar()
system.system_port = system.membus.slave
CacheConfig.config_cache(options, system)
MemConfig.config_mem(options, system)
root = Root(full_system = False, system = system)
Simulation.run(options, root, system, FutureClass)
def build_test_system(np, simplessd):
cmdline = cmd_line_template()
if buildEnv['TARGET_ISA'] == "alpha":
test_sys = makeLinuxAlphaSystem(test_mem_mode,
bm[0],
options.ruby,
cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "mips":
test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "x86":
test_sys = makeLinuxX86System(test_mem_mode,
simplessd,
options.num_cpus,
bm[0],
options.ruby,
cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "arm":
test_sys = makeArmSystem(
test_mem_mode,
options.machine_type,
simplessd,
options.num_cpus,
bm[0],
options.dtb_filename,
bare_metal=options.bare_metal,
cmdline=cmdline,
external_memory=options.external_memory_system,
ruby=options.ruby,
security=options.enable_security_extensions)
if options.enable_context_switch_stats_dump:
test_sys.enable_context_switch_stats_dump = True
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
# Set the cache line size for the entire system
test_sys.cache_line_size = options.cacheline_size
# Create a top-level voltage domain
test_sys.voltage_domain = VoltageDomain(voltage=options.sys_voltage)
# Create a source clock for the system and set the clock period
test_sys.clk_domain = SrcClockDomain(
clock=options.sys_clock, voltage_domain=test_sys.voltage_domain)
# Create a CPU voltage domain
test_sys.cpu_voltage_domain = VoltageDomain()
# Create a source clock for the CPUs and set the clock period
test_sys.cpu_clk_domain = SrcClockDomain(
clock=options.cpu_clock, voltage_domain=test_sys.cpu_voltage_domain)
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
if options.script is not None:
test_sys.readfile = options.script
if options.lpae:
test_sys.have_lpae = True
if options.virtualisation:
test_sys.have_virtualization = True
test_sys.init_param = options.init_param
# For now, assign all the CPUs to the same clock domain
test_sys.cpu = [
TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
for i in range(np)
]
if CpuConfig.is_kvm_cpu(TestCPUClass) or CpuConfig.is_kvm_cpu(FutureClass):
test_sys.kvm_vm = KvmVM()
if buildEnv['TARGET_ISA'] in "x86":
test_sys.eventq_index = np
if options.ruby:
bootmem = getattr(test_sys, 'bootmem', None)
Ruby.create_system(options, True, test_sys, test_sys.iobus,
test_sys._dma_ports, bootmem)
# Create a seperate clock domain for Ruby
test_sys.ruby.clk_domain = SrcClockDomain(
clock=options.ruby_clock, voltage_domain=test_sys.voltage_domain)
# Connect the ruby io port to the PIO bus,
# assuming that there is just one such port.
test_sys.iobus.master = test_sys.ruby._io_port.slave
for (i, cpu) in enumerate(test_sys.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
cpu.clk_domain = test_sys.cpu_clk_domain
cpu.createThreads()
cpu.createInterruptController()
cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
if buildEnv['TARGET_ISA'] in ("x86", "arm"):
cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
if buildEnv['TARGET_ISA'] in "x86":
cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[
i].slave
cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[
i].master
else:
gicv2m_range = AddrRange(0x2c1c0000, 0x2c1d0000 - 1)
if options.caches or options.l2cache:
# By default the IOCache runs at the system clock
test_sys.iocache = IOCache(addr_ranges=test_sys.mem_ranges)
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
if buildEnv['TARGET_ISA'] in "arm":
if options.machine_type == "VExpress_GEM5_V1":
test_sys.iobridge = Bridge(delay='50ns',
ranges=[gicv2m_range])
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
elif not options.external_memory_system:
mem_ranges = list(test_sys.mem_ranges) # Copy list not reference
# Bypass MSI/MSI-X
if buildEnv['TARGET_ISA'] in "arm":
if options.machine_type == "VExpress_GEM5_V1":
mem_ranges.append(gicv2m_range)
test_sys.iobridge = Bridge(delay='50ns', ranges=mem_ranges)
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
# Sanity check
if options.simpoint_profile:
if not CpuConfig.is_noncaching_cpu(TestCPUClass):
fatal("SimPoint generation should be done with atomic cpu")
if np > 1:
fatal(
"SimPoint generation not supported with more than one CPUs"
)
for i in range(np):
if options.simpoint_profile:
test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
if options.checker:
test_sys.cpu[i].addCheckerCpu()
if options.bp_type:
bpClass = BPConfig.get(options.bp_type)
test_sys.cpu[i].branchPred = bpClass()
test_sys.cpu[i].createThreads()
# If elastic tracing is enabled when not restoring from checkpoint and
# when not fast forwarding using the atomic cpu, then check that the
# TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check
# passes then attach the elastic trace probe.
# If restoring from checkpoint or fast forwarding, the code that does this for
# FutureCPUClass is in the Simulation module. If the check passes then the
# elastic trace probe is attached to the switch CPUs.
if options.elastic_trace_en and options.checkpoint_restore == None and \
not options.fast_forward:
CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options)
CacheConfig.config_cache(options, test_sys)
MemConfig.config_mem(options, test_sys)
if buildEnv['TARGET_ISA'] in "x86":
lapics = []
for i in range(np):
lapics.append(test_sys.cpu[i].interrupts[0])
test_sys.msi_handler.lapics = lapics
if buildEnv['TARGET_ISA'] in "x86" and test_sys.eventq_index == np:
test_sys.eventq_index = 0
for idx, cpu in enumerate(test_sys.cpu):
for obj in cpu.descendants():
obj.eventq_index = test_sys.eventq_index
cpu.eventq_index = idx + 1
return test_sys
def run_system_with_cpu(
process,
options,
output_dir,
warmup_cpu_class=None,
warmup_instructions=0,
real_cpu_create_function=lambda cpu_id: DerivO3CPU(cpu_id=cpu_id),
):
# Override the -d outdir --outdir option to gem5
m5.options.outdir = output_dir
m5.core.setOutputDir(m5.options.outdir)
m5.stats.reset()
max_tick = options.abs_max_tick
if options.rel_max_tick:
max_tick = options.rel_max_tick
elif options.maxtime:
max_tick = int(options.maxtime * 1000 * 1000 * 1000 * 1000)
eprint("Simulating until tick=%s" % (max_tick))
real_cpus = [real_cpu_create_function(0)]
mem_mode = real_cpus[0].memory_mode()
if warmup_cpu_class:
warmup_cpus = [warmup_cpu_class(cpu_id=0)]
warmup_cpus[0].max_insts_any_thread = warmup_instructions
else:
warmup_cpus = real_cpus
system = System(cpu=warmup_cpus,
mem_mode=mem_mode,
mem_ranges=[AddrRange(options.mem_size)],
cache_line_size=options.cacheline_size)
system.multi_thread = False
system.voltage_domain = VoltageDomain(voltage=options.sys_voltage)
system.clk_domain = SrcClockDomain(clock=options.sys_clock,
voltage_domain=system.voltage_domain)
system.cpu_voltage_domain = VoltageDomain()
system.cpu_clk_domain = SrcClockDomain(
clock=options.cpu_clock, voltage_domain=system.cpu_voltage_domain)
system.cache_line_size = options.cacheline_size
if warmup_cpu_class:
for cpu in real_cpus:
cpu.clk_domain = system.cpu_clk_domain
cpu.workload = process
cpu.system = system
cpu.switched_out = True
cpu.createThreads()
system.switch_cpus = real_cpus
for cpu in system.cpu:
cpu.clk_domain = system.cpu_clk_domain
cpu.workload = process
if options.prog_interval:
cpu.progress_interval = options.prog_interval
cpu.createThreads()
MemClass = Simulation.setMemClass(options)
system.membus = SystemXBar()
system.system_port = system.membus.slave
system.cpu[0].connectAllPorts(system.membus)
MemConfig.config_mem(options, system)
root = Root(full_system=False, system=system)
m5.options.outdir = output_dir
m5.instantiate(None) # None == no checkpoint
if warmup_cpu_class:
eprint("Running warmup with warmup CPU class (%d instrs.)" %
(warmup_instructions))
eprint("Starting simulation")
exit_event = m5.simulate(max_tick)
if warmup_cpu_class:
max_tick -= m5.curTick()
m5.stats.reset()
debug_print("Finished warmup; running real simulation")
m5.switchCpus(system, real_cpus)
exit_event = m5.simulate(max_tick)
eprint("Done simulation @ tick = %s: %s" %
(m5.curTick(), exit_event.getCause()))
m5.stats.dump()
def create(args):
''' Create and configure the system object. '''
if args.script and not os.path.isfile(args.script):
print("Error: Bootscript %s does not exist" % args.script)
sys.exit(1)
cpu_class = cpu_types[args.cpu][0]
mem_mode = cpu_class.memory_mode()
# Only simulate caches when using a timing CPU (e.g., the HPI model)
want_caches = True if mem_mode == "timing" else False
system = devices.SimpleSystem(want_caches,
args.mem_size,
mem_mode=mem_mode,
workload=ArmFsLinux(
object_file=
SysPaths.binary(args.kernel)),
readfile=args.script)
MemConfig.config_mem(args, system)
# Add the PCI devices we need for this system. The base system
# doesn't have any PCI devices by default since they are assumed
# to be added by the configuration scripts needing them.
system.pci_devices = [
# Create a VirtIO block device for the system's boot
# disk. Attach the disk image using gem5's Copy-on-Write
# functionality to avoid writing changes to the stored copy of
# the disk image.
PciVirtIO(vio=VirtIOBlock(image=create_cow_image(args.disk_image))),
]
# Attach the PCI devices to the system. The helper method in the
# system assigns a unique PCI bus ID to each of the devices and
# connects them to the IO bus.
for dev in system.pci_devices:
system.attach_pci(dev)
# Wire up the system's memory system
system.connect()
# Add CPU clusters to the system
system.cpu_cluster = [
devices.CpuCluster(system,
args.num_cores,
args.cpu_freq, "1.0V",
*cpu_types[args.cpu]),
]
# Create a cache hierarchy for the cluster. We are assuming that
# clusters have core-private L1 caches and an L2 that's shared
# within the cluster.
system.addCaches(want_caches, last_cache_level=2)
# Setup gem5's minimal Linux boot loader.
system.realview.setupBootLoader(system, SysPaths.binary)
if args.dtb:
system.workload.dtb_filename = args.dtb
else:
# No DTB specified: autogenerate DTB
system.workload.dtb_filename = \
os.path.join(m5.options.outdir, 'system.dtb')
system.generateDtb(system.workload.dtb_filename)
# Linux boot command flags
kernel_cmd = [
# Tell Linux to use the simulated serial port as a console
"console=ttyAMA0",
# Hard-code timi
"lpj=19988480",
# Disable address space randomisation to get a consistent
# memory layout.
"norandmaps",
# Tell Linux where to find the root disk image.
"root=%s" % args.root_device,
# Mount the root disk read-write by default.
"rw",
# Tell Linux about the amount of physical memory present.
"mem=%s" % args.mem_size,
]
system.workload.command_line = " ".join(kernel_cmd)
return system
def run_system_with_cpu(
process,
options,
output_dir,
warmup_instructions=0,
):
warmup = True
# Override the -d outdir --outdir option to gem5
m5.options.outdir = output_dir
m5.core.setOutputDir(m5.options.outdir)
m5.stats.reset()
max_tick = options.abs_max_tick
if options.rel_max_tick:
max_tick = options.rel_max_tick
elif options.maxtime:
max_tick = int(options.maxtime * 1000 * 1000 * 1000 * 1000)
eprint("Simulating until tick=%s" % (max_tick))
# DerivO3CPU is the configurable out-of-order CPU model supplied by gem5
the_cpu = DerivO3CPU(cpu_id=0, switched_out=warmup)
icache = L1_ICache(size=options.l1i_size, assoc=options.l1i_assoc)
dcache = L1_DCache(size=options.l1d_size, assoc=options.l1d_assoc)
the_cpu.branchPred = LocalBP()
# Parameter values
the_cpu.numROBEntries = options.ROB
the_cpu.numIQEntries = options.IQ
real_cpus = [the_cpu]
mem_mode = real_cpus[0].memory_mode()
if warmup:
the_w_cpu = TimingSimpleCPU(cpu_id=0)
the_w_cpu.branchPred = LocalBP()
# Parameter values
the_w_cpu[0].addPrivateSplitL1Caches(icache, dcache, None, None)
the_w_cpu[0].createInterruptController()
warmup_cpus = [the_w_cpu]
if warmup_instructions:
warmup_cpus[0].max_insts_any_thread = warmup_instructions
else:
warmup_cpus = real_cpus
system = System(cpu=warmup_cpus,
mem_mode=mem_mode,
mem_ranges=[AddrRange(options.mem_size)],
cache_line_size=options.cacheline_size)
system.multi_thread = False
system.voltage_domain = VoltageDomain(voltage=options.sys_voltage)
system.clk_domain = SrcClockDomain(clock=options.sys_clock,
voltage_domain=system.voltage_domain)
system.cpu_voltage_domain = VoltageDomain()
system.cpu_clk_domain = SrcClockDomain(
clock=options.cpu_clock, voltage_domain=system.cpu_voltage_domain)
system.cache_line_size = options.cacheline_size
cache_line_size = options.cacheline_size
for cpu in system.cpu:
cpu.clk_domain = system.cpu_clk_domain
cpu.workload = process
if options.prog_interval:
cpu.progress_interval = options.prog_interval
cpu.createThreads()
MemClass = Simulation.setMemClass(options)
system.membus = SystemXBar()
system.system_port = system.membus.slave
system.cpu[0].connectAllPorts(system.membus)
MemConfig.config_mem(options, system)
root = Root(full_system=False, system=system)
if warmup:
for cpu in real_cpus:
cpu.clk_domain = system.cpu_clk_domain
cpu.workload = process
cpu.system = system
cpu.switched_out = True
cpu.createThreads()
root.switch_cpus = real_cpus
m5.options.outdir = output_dir
m5.instantiate(None) # None == no checkpoint
if warmup:
eprint("Running warmup with warmup CPU class ({} instrs.)".format(
warmup_instructions))
eprint("Starting simulation")
exit_event = m5.simulate(max_tick)
eprint("exit_event: {}".format(exit_event))
if warmup:
max_tick -= m5.curTick()
m5.stats.reset()
eprint("Finished warmup; running real simulation")
m5.switchCpus(system, list(zip(warmup_cpus, real_cpus)))
exit_event = m5.simulate(max_tick)
eprint("Done simulation @ tick = %s: %s" %
(m5.curTick(), exit_event.getCause()))
m5.stats.dump()
# We are fine with 256 MB memory for now.
mem_range = AddrRange('256MB')
# Start address is 0
system.mem_ranges = [mem_range]
# Do not worry about reserving space for the backing store
system.mmap_using_noreserve = True
# Force a single channel to match the assumptions in the DRAM traffic
# generator
args.mem_channels = 1
args.external_memory_system = 0
args.tlm_memory = 0
args.elastic_trace_en = 0
MemConfig.config_mem(args, system)
# Sanity check for memory controller class.
if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl):
fatal("This script assumes the memory is a DRAMCtrl subclass")
# There is no point slowing things down by saving any data.
system.mem_ctrls[0].null = True
# Set the address mapping based on input argument
system.mem_ctrls[0].addr_mapping = args.addr_map
system.mem_ctrls[0].page_policy = args.page_policy
# We create a traffic generator state for each param combination we want to
# test. Each traffic generator state is specified in the config file and the
# generator remains in the state for specific period. This period is 0.25 ms.
def build_test_system(np):
cmdline = cmd_line_template()
if buildEnv['TARGET_ISA'] == "alpha":
test_sys = makeLinuxAlphaSystem(test_mem_mode,
bm[0],
options.ruby,
cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "mips":
test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "x86":
test_sys = makeLinuxX86System(test_mem_mode,
options.num_cpus,
bm[0],
options.ruby,
cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "arm":
test_sys = makeArmSystem(
test_mem_mode,
options.machine_type,
options.membus_width,
options,
options.num_cpus,
bm[0],
options.dtb_filename,
bare_metal=options.bare_metal,
cmdline=cmdline,
ignore_dtb=options.generate_dtb,
external_memory=options.external_memory_system,
ruby=options.ruby,
security=options.enable_security_extensions)
if options.enable_context_switch_stats_dump:
test_sys.enable_context_switch_stats_dump = True
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
# Set the cache line size for the entire system
test_sys.cache_line_size = options.cacheline_size
# Create a top-level voltage domain
test_sys.voltage_domain = VoltageDomain(voltage=options.sys_voltage)
# Create a source clock for the system and set the clock period
test_sys.clk_domain = SrcClockDomain(
clock=options.sys_clock, voltage_domain=test_sys.voltage_domain)
# Create a CPU voltage domain
test_sys.cpu_voltage_domain = VoltageDomain()
# Create a source clock for the CPUs and set the clock period
test_sys.cpu_clk_domain = SrcClockDomain(
clock=options.cpu_clock, voltage_domain=test_sys.cpu_voltage_domain)
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
if options.script is not None:
test_sys.readfile = options.script
if options.lpae:
test_sys.have_lpae = True
if options.virtualisation:
test_sys.have_virtualization = True
test_sys.init_param = options.init_param
# For now, assign all the CPUs to the same clock domain
test_sys.cpu = [
TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
for i in xrange(np)
]
if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
test_sys.kvm_vm = KvmVM()
if options.ruby:
bootmem = getattr(test_sys, 'bootmem', None)
Ruby.create_system(options, True, test_sys, test_sys.iobus,
test_sys._dma_ports, bootmem)
# Create a seperate clock domain for Ruby
test_sys.ruby.clk_domain = SrcClockDomain(
clock=options.ruby_clock, voltage_domain=test_sys.voltage_domain)
# Connect the ruby io port to the PIO bus,
# assuming that there is just one such port.
test_sys.iobus.master = test_sys.ruby._io_port.slave
for (i, cpu) in enumerate(test_sys.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
cpu.clk_domain = test_sys.cpu_clk_domain
cpu.createThreads()
cpu.createInterruptController()
cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
if buildEnv['TARGET_ISA'] in ("x86", "arm"):
cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
if buildEnv['TARGET_ISA'] in "x86":
cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[
i].slave
cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[
i].master
else:
if options.caches or options.l2cache:
# By default the IOCache runs at the system clock
test_sys.iocache = IOCache(addr_ranges=test_sys.mem_ranges)
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
elif not options.external_memory_system:
test_sys.iobridge = Bridge(delay='50ns',
ranges=test_sys.mem_ranges)
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
# Sanity check
if options.fastmem:
if TestCPUClass != AtomicSimpleCPU:
fatal("Fastmem can only be used with atomic CPU!")
if (options.caches or options.l2cache):
fatal("You cannot use fastmem in combination with caches!")
if options.simpoint_profile:
if not options.fastmem:
# Atomic CPU checked with fastmem option already
fatal(
"SimPoint generation should be done with atomic cpu and fastmem"
)
if np > 1:
fatal(
"SimPoint generation not supported with more than one CPUs"
)
for i in xrange(np):
if options.fastmem:
test_sys.cpu[i].fastmem = True
if options.simpoint_profile:
test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
if options.checker:
test_sys.cpu[i].addCheckerCpu()
test_sys.cpu[i].createThreads()
# If elastic tracing is enabled when not restoring from checkpoint and
# when not fast forwarding using the atomic cpu, then check that the
# TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check
# passes then attach the elastic trace probe.
# If restoring from checkpoint or fast forwarding, the code that does this for
# FutureCPUClass is in the Simulation module. If the check passes then the
# elastic trace probe is attached to the switch CPUs.
if options.elastic_trace_en and options.checkpoint_restore == None and \
not options.fast_forward:
CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options)
if buildEnv['TARGET_ISA'] != "arm" and options.workload_automation_vio:
warn("Ignoring --workload-automation-vio. It is unsupported on "
"non-ARM systems.")
elif options.workload_automation_vio:
from m5.objects import PciVirtIO, VirtIO9PDiod
viopci = PciVirtIO(
pci_bus=0,
pci_dev=test_sys.realview._num_pci_dev,
pci_func=0,
InterruptPin=1,
InterruptLine=test_sys.realview._num_pci_int_line)
test_sys.realview._num_pci_dev = test_sys.realview._num_pci_dev + 1
test_sys.realview._num_pci_int_line = test_sys.realview._num_pci_int_line + 1
viopci.vio = VirtIO9PDiod()
viopci.vio.root = options.workload_automation_vio
viopci.vio.socketPath = "/home/yqureshi/shares/local/scrap/temp"
test_sys.realview.viopci = viopci
test_sys.realview.viopci.dma = test_sys.iobus.slave
test_sys.realview.viopci.pio = test_sys.iobus.master
CacheConfig.config_cache(options, test_sys)
MemConfig.config_mem(options, test_sys)
return test_sys
def create(args):
''' Create and configure the system object. '''
if args.readfile and not os.path.isfile(args.readfile):
print("Error: Bootscript %s does not exist" % args.readfile)
sys.exit(1)
object_file = args.kernel if args.kernel else ""
cpu_class = cpu_types[args.cpu][0]
mem_mode = cpu_class.memory_mode()
# Only simulate caches when using a timing CPU (e.g., the HPI model)
want_caches = True if mem_mode == "timing" else False
platform = ObjectList.platform_list.get(args.machine_type)
system = devices.simpleSystem(ArmSystem,
want_caches,
args.mem_size,
platform=platform(),
mem_mode=mem_mode,
readfile=args.readfile)
MemConfig.config_mem(args, system)
if args.semi_enable:
system.semihosting = ArmSemihosting(stdin=args.semi_stdin,
stdout=args.semi_stdout,
stderr=args.semi_stderr,
files_root_dir=args.semi_path,
cmd_line=" ".join([object_file] +
args.args))
# Add the PCI devices we need for this system. The base system
# doesn't have any PCI devices by default since they are assumed
# to be added by the configurastion scripts needin them.
pci_devices = []
if args.disk_image:
# Create a VirtIO block device for the system's boot
# disk. Attach the disk image using gem5's Copy-on-Write
# functionality to avoid writing changes to the stored copy of
# the disk image.
system.disk = PciVirtIO(vio=VirtIOBlock(
image=create_cow_image(args.disk_image)))
pci_devices.append(system.disk)
# Attach the PCI devices to the system. The helper method in the
# system assigns a unique PCI bus ID to each of the devices and
# connects them to the IO bus.
for dev in pci_devices:
system.attach_pci(dev)
# Wire up the system's memory system
system.connect()
# Add CPU clusters to the system
system.cpu_cluster = [
devices.CpuCluster(system, args.num_cores, args.cpu_freq, "1.0V",
*cpu_types[args.cpu]),
]
# Create a cache hierarchy for the cluster. We are assuming that
# clusters have core-private L1 caches and an L2 that's shared
# within the cluster.
for cluster in system.cpu_cluster:
system.addCaches(want_caches, last_cache_level=2)
# Setup gem5's minimal Linux boot loader.
system.auto_reset_addr = True
# Using GICv3
system.realview.gic.gicv4 = False
system.highest_el_is_64 = True
system.have_virtualization = True
system.have_security = True
workload_class = workloads.workload_list.get(args.workload)
system.workload = workload_class(object_file, system)
return system
def build_test_system(np):
cmdline = cmd_line_template()
if buildEnv['TARGET_ISA'] == "mips":
test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "riscv":
test_sys = makeBareMetalRiscvSystem(test_mem_mode,
bm[0],
cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "x86":
test_sys = makeLinuxX86System(test_mem_mode,
np,
bm[0],
options.ruby,
cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "arm":
test_sys = makeArmSystem(
test_mem_mode,
options.machine_type,
np,
bm[0],
options.dtb_filename,
bare_metal=options.bare_metal,
cmdline=cmdline,
external_memory=options.external_memory_system,
ruby=options.ruby,
security=options.enable_security_extensions,
vio_9p=options.vio_9p,
bootloader=options.bootloader,
)
if options.enable_context_switch_stats_dump:
test_sys.enable_context_switch_stats_dump = True
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
# Set the cache line size for the entire system
test_sys.cache_line_size = options.cacheline_size
# Create a top-level voltage domain
test_sys.voltage_domain = VoltageDomain(voltage=options.sys_voltage)
# Create a source clock for the system and set the clock period
test_sys.clk_domain = SrcClockDomain(
clock=options.sys_clock, voltage_domain=test_sys.voltage_domain)
# Create a CPU voltage domain
test_sys.cpu_voltage_domain = VoltageDomain()
# Create a source clock for the CPUs and set the clock period
test_sys.cpu_clk_domain = SrcClockDomain(
clock=options.cpu_clock, voltage_domain=test_sys.cpu_voltage_domain)
if buildEnv['TARGET_ISA'] == 'riscv':
test_sys.workload.bootloader = options.kernel
elif options.kernel is not None:
test_sys.workload.object_file = binary(options.kernel)
if options.script is not None:
test_sys.readfile = options.script
if options.lpae:
test_sys.have_lpae = True
if options.virtualisation:
test_sys.have_virtualization = True
test_sys.init_param = options.init_param
# For now, assign all the CPUs to the same clock domain
test_sys.cpu = [
TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
for i in range(np)
]
if ObjectList.is_kvm_cpu(TestCPUClass) or \
ObjectList.is_kvm_cpu(FutureClass):
test_sys.kvm_vm = KvmVM()
if options.ruby:
bootmem = getattr(test_sys, '_bootmem', None)
Ruby.create_system(options, True, test_sys, test_sys.iobus,
test_sys._dma_ports, bootmem)
# Create a seperate clock domain for Ruby
test_sys.ruby.clk_domain = SrcClockDomain(
clock=options.ruby_clock, voltage_domain=test_sys.voltage_domain)
# Connect the ruby io port to the PIO bus,
# assuming that there is just one such port.
test_sys.iobus.master = test_sys.ruby._io_port.slave
for (i, cpu) in enumerate(test_sys.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
cpu.clk_domain = test_sys.cpu_clk_domain
cpu.createThreads()
cpu.createInterruptController()
test_sys.ruby._cpu_ports[i].connectCpuPorts(cpu)
else:
if options.caches or options.l2cache:
# By default the IOCache runs at the system clock
test_sys.iocache = IOCache(addr_ranges=test_sys.mem_ranges)
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
elif not options.external_memory_system:
test_sys.iobridge = Bridge(delay='50ns',
ranges=test_sys.mem_ranges)
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
# Sanity check
if options.simpoint_profile:
if not ObjectList.is_noncaching_cpu(TestCPUClass):
fatal("SimPoint generation should be done with atomic cpu")
if np > 1:
fatal(
"SimPoint generation not supported with more than one CPUs"
)
for i in range(np):
if options.simpoint_profile:
test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
if options.checker:
test_sys.cpu[i].addCheckerCpu()
if not ObjectList.is_kvm_cpu(TestCPUClass):
if options.bp_type:
bpClass = ObjectList.bp_list.get(options.bp_type)
test_sys.cpu[i].branchPred = bpClass()
if options.indirect_bp_type:
IndirectBPClass = ObjectList.indirect_bp_list.get(
options.indirect_bp_type)
test_sys.cpu[i].branchPred.indirectBranchPred = \
IndirectBPClass()
test_sys.cpu[i].createThreads()
# If elastic tracing is enabled when not restoring from checkpoint and
# when not fast forwarding using the atomic cpu, then check that the
# TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check
# passes then attach the elastic trace probe.
# If restoring from checkpoint or fast forwarding, the code that does this for
# FutureCPUClass is in the Simulation module. If the check passes then the
# elastic trace probe is attached to the switch CPUs.
if options.elastic_trace_en and options.checkpoint_restore == None and \
not options.fast_forward:
CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options)
CacheConfig.config_cache(options, test_sys)
MemConfig.config_mem(options, test_sys)
return test_sys
def create(args):
''' Create and configure the system object. '''
if args.readfile and not os.path.isfile(args.readfile):
print("Error: Bootscript %s does not exist" % args.readfile)
sys.exit(1)
object_file = args.kernel if args.kernel else ""
cpu_class = cpu_types[args.cpu][0]
mem_mode = cpu_class.memory_mode()
# Only simulate caches when using a timing CPU (e.g., the HPI model)
want_caches = True if mem_mode == "timing" else False
platform = ObjectList.platform_list.get(args.machine_type)
system = devices.SimpleSystem(want_caches,
args.mem_size,
platform=platform(),
mem_mode=mem_mode,
readfile=args.readfile)
MemConfig.config_mem(args, system)
if args.semi_enable:
system.semihosting = ArmSemihosting(
stdin=args.semi_stdin,
stdout=args.semi_stdout,
stderr=args.semi_stderr,
files_root_dir=args.semi_path,
cmd_line = " ".join([ object_file ] + args.args)
)
if args.disk_image:
# Create a VirtIO block device for the system's boot
# disk. Attach the disk image using gem5's Copy-on-Write
# functionality to avoid writing changes to the stored copy of
# the disk image.
system.realview.vio[0].vio = VirtIOBlock(
image=create_cow_image(args.disk_image))
# Wire up the system's memory system
system.connect()
# Add CPU clusters to the system
system.cpu_cluster = [
devices.CpuCluster(system,
args.num_cores,
args.cpu_freq, "1.0V",
*cpu_types[args.cpu]),
]
# Create a cache hierarchy for the cluster. We are assuming that
# clusters have core-private L1 caches and an L2 that's shared
# within the cluster.
system.addCaches(want_caches, last_cache_level=2)
# Setup gem5's minimal Linux boot loader.
system.auto_reset_addr = True
# Using GICv3
system.realview.gic.gicv4 = False
system.highest_el_is_64 = True
system.release.add(ArmExtension('SECURITY'))
system.release.add(ArmExtension('VIRTUALIZATION'))
workload_class = workloads.workload_list.get(args.workload)
system.workload = workload_class(
object_file, system)
return system
