def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
from supply_router import supply_router as router
if False:
from control_logic import control_logic
cell = control_logic(16)
layer_stack =("metal3","via3","metal4")
rtr=router(layer_stack, cell)
self.assertTrue(rtr.route())
else:
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=32,
num_banks=1)
c.words_per_row=1
sram = sram(c, "sram1")
cell = sram.s
self.local_check(cell,True)
# fails if there are any DRC errors on any cells
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import control_logic
import tech
debug.info(1, "Testing sample for control_logic")
a = control_logic.control_logic(num_rows=128)
self.local_check(a)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
import control_logic
import tech
debug.info(1, "Testing sample for control_logic")
a = control_logic.control_logic(num_rows=128)
OPTS.check_lvsdrc = True
self.local_check(a)
def __init__(self, name):
design.__init__(self, "top")
# Instantiate a GDS cell with the design
globals.setup_paths()
from control_logic import control_logic
cell = control_logic(16)
#from pinv import pinv
#cell = pinv()
#gds_file = "{0}/{1}.gds".format(os.path.dirname(os.path.realpath(__file__)),"control_logic")
#cell = gds_cell(name, gds_file)
self.add_inst(name=name,
mod=cell,
offset=[0,0])
self.connect_inst(cell.pin_map.keys())
r=router(module=cell)
layer_stack =("metal3","via2","metal2")
self.assertTrue(r.route(self,layer_stack))
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import control_logic
import tech
# check control logic for single port
debug.info(1, "Testing sample for control_logic")
a = control_logic.control_logic(num_rows=128,
words_per_row=1,
word_size=32)
self.local_check(a)
# check control logic for multi-port
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell = "replica_pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
debug.info(1, "Testing sample for control_logic for multiport")
a = control_logic.control_logic(num_rows=128,
words_per_row=1,
word_size=8)
self.local_check(a)
# Check port specific control logic
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
debug.info(
1,
"Testing sample for control_logic for multiport, only write control logic"
)
a = control_logic.control_logic(num_rows=128,
words_per_row=1,
word_size=8,
port_type="rw")
self.local_check(a)
OPTS.num_rw_ports = 0
OPTS.num_w_ports = 1
debug.info(
1,
"Testing sample for control_logic for multiport, only write control logic"
)
a = control_logic.control_logic(num_rows=128,
words_per_row=1,
word_size=8,
port_type="w")
self.local_check(a)
OPTS.num_w_ports = 0
OPTS.num_r_ports = 1
debug.info(
1,
"Testing sample for control_logic for multiport, only read control logic"
)
a = control_logic.control_logic(num_rows=128,
words_per_row=1,
word_size=8,
port_type="r")
self.local_check(a)
globals.end_openram()