def parse(self, filename):
     """ Parse an Altium file into a design """
     design = Design()
     f = open(filename, "w")
     #TODO: Read!
     f.close()
     return design
    def parse(self, filename, library_filename=None):
        """ Parse a kicad file into a design """

        # Rough'n'dirty parsing, assume nothing useful comes before
        # the description
        circuit = Design()
        segments = set()  # each wire segment
        junctions = set()  # wire junction point (connects all wires under it)

        if library_filename is None:
            library_filename = splitext(filename)[0] + '-cache.lib'
            if exists(library_filename):
                self.parse_library(library_filename, circuit)

        f = open(filename)

        # Read until the end of the description
        while f.readline().strip() != "$EndDescr":
            pass

        # Now parse wires and components, ignore connections, we get
        # connectivity from wire segments

        line = f.readline()
        while line:
            element = line.split()[0]  # whats next on the list
            if element == "Wire":  # Wire Segment, coords on 2nd line
                x1, y1, x2, y2 = [int(i) for i in f.readline().split()]
                if not (x1 == x2 and y1 == y2):  # ignore zero-length segments
                    segments.add(((x1, y1), (x2, y2)))
            elif element == "Connection":  # Store these to apply later
                x, y = [int(i) for i in line.split()[2:4]]
                junctions.add((x, y))
            elif element == "$Comp":  # Component Instance
                # name & reference
                prefix, name, reference = f.readline().split()
                assert prefix == 'L'

                # timestamp
                prefix, _ = f.readline().split(None, 1)
                assert prefix == 'U'

                # position
                prefix, compx, compy = f.readline().split()
                assert prefix == 'P'
                compx, compy = int(compx), int(compy)

                # TODO(ajray): ignore all the fields for now, probably
                # could make these annotations

                while f.readline().strip() not in ("$EndComp", ''):
                    pass

                # TODO: calculate rotation
                inst = ComponentInstance(reference, name, 0)
                inst.add_symbol_attribute(SymbolAttribute(compx, compy, 0))

                circuit.add_component_instance(inst)

            line = f.readline()

        f.close()

        segments = self.divide(segments, junctions)
        circuit.nets = self.calc_nets(segments)

        return circuit
# 0) ...
# 1) ???
# 2) Profit!!!
from core.design import Design
from xml.etree.ElementTree import ElementTree


class Eagle:
    """ The Eagle Format Parser """

    def __init__(self):
        pass


    def parse(self, filename):
        """ Parse an Eagle file into a design """
<<<<<<< HEAD
        #design = design()
        #import an xmltree from the file provided
       	xmltree = ElementTree(file=filename)
        xmlroot = xmltree.getroot()
		
        return xmltree
=======
        design = Design()
        f = open(filename, "w")
        #TODO: Read!
        f.close()
        return design
>>>>>>> 5abb89ac932f010195dea31c734cf01a4d7fff5f