def test_load_program():
we = Signal(bool(0))
sig_in = Signal(intbv(0)[WIDTH:])
sig_out = Signal(intbv(0)[WIDTH:])
address = Signal(intbv(0)[WIDTH:])
clk = Signal(bool(0))
mem = memory(we, address, sig_in, sig_out, clk)
instructions = []
file_in = open("programs/program2.o", "rb")
data_in = None
try:
short = file_in.read(2)
while short:
instructions.append(struct.unpack('<H', short))
short = file_in.read(2)
finally:
file_in.close()
"""for lol in instructions:
print "{0:016b}".format(int(lol[0]))"""
@always(delay(10))
def clkgen():
clk.next = not clk
@instance
def stimulus():
# read program into memory
for index, item in enumerate(instructions):
we.next = True
address.next = index
sig_in.next = item[0]
yield clk.posedge
yield clk.negedge
# assert that program has landed in memory properly
for index, item in enumerate(instructions):
we.next = False
address.next = index
yield clk.posedge
yield clk.negedge
assert item[0] == sig_out
# run program
raise StopSimulation
return mem, clkgen, stimulus
def step(s, cpu): if s.opcode == 'MOV': dst = cpu.memory(s.op1) if s.op2.isdigit() and dst: return dst.store(int(s.op2)) elif dst: return cpu.move(src, dst) else: return cpu.DATA_ABORT elif s.opcode == 'ADD':
def test_memory():
we = Signal(bool(0))
sig_in = Signal(intbv(0)[WIDTH:])
sig_out = Signal(intbv(0)[WIDTH:])
address = Signal(intbv(0)[WIDTH:])
clk = Signal(bool(0))
dut = memory(we, address, sig_in, sig_out, clk)
@always(delay(10))
def clkgen():
clk.next = not clk
@instance
def stimulus():
# Memory at address = 1 gets value 5
we.next = True
address.next = Signal(intbv(1)[WIDTH:])
sig_in.next = Signal(intbv(5)[WIDTH:])
yield clk.posedge
yield clk.negedge
assert sig_out == 5
# Write value 31 in memory with address=0
we.next = True
address.next = Signal(intbv(0)[WIDTH:])
sig_in.next = Signal(intbv(31)[WIDTH:])
yield clk.posedge
yield clk.negedge
assert sig_out == 31
# The address=1 is 'blocked', so we can only read the old value
we.next = False
address.next = Signal(intbv(1)[WIDTH:])
yield clk.posedge
yield clk.negedge
assert sig_out == 5
# Now we 'block' adress=0 and read the old value
we.next = False
address.next = Signal(intbv(0)[WIDTH:])
yield clk.posedge
yield clk.negedge
assert sig_out == 31
raise StopSimulation
return dut, stimulus, clkgen
